External Memory Interfaces in Stratix II and Stratix II GX Devices

External Memory Interfaces in Stratix II and Stratix II GX Devices
3. External Memory
Interfaces in Stratix II and
Stratix II GX Devices
SII52003-4.5
Introduction
Stratix® II and Stratix II GX devices support a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, DDR2
SDRAM, RLDRAM II, QDRII SRAM, and single data rate (SDR) SDRAM.
Its dedicated phase-shift circuitry allows the Stratix II or Stratix II GX
device to interface with an external memory at twice the system clock
speed (up to 300 MHz/600 megabits per second (Mbps) with
RLDRAM II). In addition to external memory interfaces, you can also use
the dedicated phase-shift circuitry for other applications that require a
shifted input signal.
Typical I/O architectures transmit a single data word on each positive
clock edge and are limited to the associated clock speed. To achieve a
400-Mbps transfer rate, a SDR system requires a 400-MHz clock. Many
new applications have introduced a DDR I/O architecture as an
alternative to SDR architectures. While SDR architectures capture data on
one edge of a clock, the DDR architectures captures data on both the
rising and falling edges of the clock, doubling the throughput for a given
clock frequency and accelerating performance. For example, a 200-MHz
clock can capture a 400-Mbps data stream, enhancing system
performance and simplifying board design.
Most new memory architectures use a DDR I/O interface. Although
Stratix II and Stratix II GX devices also support the mature and well
established SDR external memory, this chapter focuses on DDR memory
standards. These DDR memory standards cover a broad range of
applications for embedded processor systems, image processing, storage,
communications, and networking.
Stratix II devices offer external memory support in every I/O bank. The
side I/O banks support the PLL-based interfaces running at up to
200 MHz, while the top and bottom I/O banks support PLL- and
DLL-based interfaces. Figure 3–1 shows Stratix II device memory
support.
Altera Corporation
January 2008
3–1
Introduction
Figure 3–1. External Memory Support
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
DQS5T
VREF3B3
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
PLL1
PLL4
Support PLL-Based
Implementation
Support PLL-Based
Implementation
VR EF1B6
VREF 3B6
VREF 4B6
VREF 0B1
VREF 1B1
Support PLL- and
DLL-Based Implementations
VREF 2B6
Bank 6
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
Bank 5
VREF 4B5
VREF 0B2
VR EF3B5
Bank 2
Support PLL- and
DLL-Based Implementations
VR EF1B2
VR EF2B2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
Bank 12
Bank 8
Bank 10
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
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Stratix II Device Handbook, Volume 2
VREF0B8
DQS5B
PLL12
PLL6
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–1 summarizes the maximum clock rate Stratix II and Stratix II GX
devices can support with external memory devices.
Table 3–1. Stratix II and Stratix II GX Maximum Clock Rate Support for External Memory Interfaces
Notes (1), (2)
–3 Speed Grade (MHz)
–4 Speed Grade (MHz)
–5 Speed Grade (MHz)
Memory Standards
DLL-Based
PLL-Based
DLL-Based PLL-Based
DDR2 SDRAM (3), (5)
333
200
267
DDR SDRAM (3)
200
150
200
DLL-Based
PLL-Based
167
233
167
133
200
100
RLDRAM II
300
200
250 (4)
175
200
175
QDRII SRAM
300
200
250
167
250
167
QDRII+ SRAM
300
(6)
250
(6)
250
(6)
Notes to Table 3–1:
(1)
(2)
(3)
(4)
(5)
(6)
Memory interface timing specifications are dependent on the memory, board, physical interface, and core logic.
Refer to each memory interface application note for more details on how each specification was generated.
The respective Altera MegaCore function and the EP2S60F1020C3 timing information featured in the Quartus® II
software version 6.0 was used to define these clock rates.
This applies for interfaces with both modules and components.
You must underclock a 300-MHz RLDRAM II device to achieve this clock rate.
To achieve speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps), you must use the Altera DDR2
SDRAM Controller MegaCore function that features a new dynamic auto-calibration circuit in the data path for
resynchronization. For more information, see the Altera web site at www.altera.com. For interfaces running at
267 MHz or below, continue to use the static resynchronization data path currently supported by the released
version of the MegaCore function.
The lowest frequency at which a QDRII+ SRAM device can operate is 238 MHz. Therefore, the PLL-based
implementation does not support the QDRII+ SRAM interface.
This chapter describes the hardware features in Stratix II and Stratix II GX
devices that facilitate the high-speed memory interfacing for each DDR
memory standard. This chapter focuses primarily on the DLL-based
implementation. The PLL-based implementation is described in
application notes. It then lists the Stratix II and Stratix II GX feature
enhancements from Stratix devices and briefly explains how each
memory standard uses the Stratix II and Stratix II GX features.
f
You can use this document with the following documents:
■
■
■
■
Altera Corporation
January 2008
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix,
& Stratix GX Devices
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
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Stratix II Device Handbook, Volume 2
External Memory Standards
External
Memory
Standards
The following sections briefly describe the external memory standards
supported by Stratix II and Stratix II GX devices. Altera offers a complete
solution for these memories, including clear-text data path, memory
controller, and timing analysis.
DDR and DDR2 SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed. These devices transfer data on both the rising
and falling edge of the clock signal. DDR2 SDRAM is a second generation
memory based on the DDR SDRAM architecture and transfers data to
Stratix II and Stratix II GX devices at up to 333 MHz/667 Mbps. Stratix II
and Stratix II GX devices can support DDR SDRAM at up to
200 MHz/400 Mbps. For PLL-based implementations, Stratix II and
Stratix II GX devices support DDR and DDR2 SDRAM up to 150 MHz
and 200 MHz, respectively.
Interface Pins
DDR and DDR2 SDRAM devices use interface pins such as data (DQ),
data strobe (DQS), clock, command, and address pins. Data is sent and
captured at twice the system clock rate by transferring data on the clock’s
positive and negative edge. The commands and addresses still only use
one active (positive) edge of a clock. DDR and DDR2 SDRAM use
single-ended data strobes (DQS). DDR2 SDRAM can also use optional
differential data strobes (DQS and DQS#). However, Stratix II and
Stratix II GX devices do not use the optional differential data strobes for
DDR2 SDRAM interfaces since DQS and DQSn pins in Stratix II and
Stratix II GX devices are not differential. You can leave the DDR SDRAM
memory DQS# pin unconnected. Only the shifted DQS signal from the
DQS logic block is used to capture data.
DDR and DDR2 SDRAM ×16 devices use two DQS pins, and each DQS
pin is associated with eight DQ pins. However, this is not the same as the
×16/×18 mode in Stratix II and Stratix II GX devices (see “Data and Data
Strobe Pins” on page 3–14). To support a ×16 DDR SDRAM device, you
need to configure Stratix II and Stratix II GX devices to use two sets of DQ
pins in ×8/×9 mode. Similarly if your ×32 memory device uses four DQS
pins where each DQS pin is associated with eight DQ pins, you need to
configure Stratix II and Stratix II GX devices to use four sets of DQS/DQ
groups in ×8/×9 mode.
Connect the memory device’s DQ and DQS pins to Stratix II and
Stratix II GX DQ and DQS pins, respectively, as listed in Stratix II and
Stratix II GX pin tables. DDR and DDR2 SDRAM also uses active-high
data mask, DM, pins for writes. You can connect the memory’s DM pins
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
to any of Stratix II and Stratix II GX I/O pins in the same bank as the DQ
pins of the FPGA. There is one DM pin per DQS/DQ group in a DDR or
DDR2 SDRAM device.
You can also use I/O pins in banks 1, 2, 5, or 6 to interface with DDR and
DDR2 SDRAM devices. These banks do not have dedicated circuitry,
though, and can only support DDR SDRAM at speeds up to 150 MHz and
DDR2 SDRAM at speeds up to 200 MHz. DDR2 SDRAM interfaces using
these banks are supported using the SSTL-18 Class I I/O standard.
f
For more information, see AN 327: Interfacing DDR SDRAM with
Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II
Devices.
If the DDR or DDR2 SDRAM device supports error correction coding
(ECC), the design will use an extra DQS/DQ group for the ECC pins.
You can use any of the user I/O pins for commands and addresses to the
DDR and DDR2 SDRAM. You may need to generate these signals from
the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK# pins. Use any of
the user I/O pins via the DDR registers to generate the CK and CK#
signals to meet the DDR SDRAM or DDR2 SDRAM device’s tDQSS
requirement. The memory device’s tDQSS specification requires that the
write DQS signal’s positive edge must be within 25% of the positive edge
of the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/O
pins for CK and CK# also ensures that any PVT variations on the DQS
signals are tracked the same way by these CK and CK# pins. Figure 3–2
shows a diagram that illustrates how to generate these clocks.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
External Memory Standards
Figure 3–2. Clock Generation for External Memory Interfaces in Stratix II and Stratix II GX Devices
LE
VCC
IOE
GND
D
Q
D
Q
D
Q
D
Q
VCC
CK (1)
DK (2)
VCC
GND
VCC
CK# (1)
DK# (2)
clk
Notes to Figure 3–2:
(1)
(2)
CK and CK# are the clocks to the memory devices.
DK and DK# are for RLDRAM II interfaces. You can generate DK# and DK from separate pins if the difference of
the Quartus II software’s reported clock-to-out time for these pins meets the RLDRAM II device’s tCKDK
specification.
Read and Write Operations
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned with respect to the data strobe. To properly read the
data in, the data strobe needs to be center-aligned with respect to the data
inside the FPGA. Stratix II and Stratix II GX devices feature dedicated
circuitry to shift this data strobe to the middle of the data window.
Figure 3–3 shows an example of how the memory sends out the data and
data strobe for a burst-of-two operation.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–3. Example of a 90° Shift on the DQS Signal
Notes (1), (2)
DQS pin to
register delay
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
DQS at
IOE registers
90˚ degree (3)
DQ at
IOE registers
DQ pin to
register delay
Notes to Figure 3–3:
(1)
(2)
(3)
RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
DDR2 SDRAM does not support a burst length of two.
The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
needs to send the data to the memory center-aligned with respect to the
data strobe. Stratix II and Stratix II GX devices use a PLL to center-align
the data by generating a 0° phase-shifted system clock for the write data
strobes and a –90° phase-shifted write clock for the write data pins for
DDR and DDR2 SDRAM. Figure 3–4 shows an example of the
relationship between the data and data strobe during a burst-of-four
write.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
External Memory Standards
Figure 3–4. DQ and DQS Relationship During a DDR and DDR2 SDRAM Write
Notes (1), (2)
DQS at
FPGA Pin
DQ at
FPGA Pin
Notes to Figure 3–4:
(1)
(2)
This example shows a write for a burst length of four. DDR SDRAM also supports burst lengths of two.
The write clock signals never go to hi-Z state on RLDRAM II and QDRII SRAM memory interfaces because they use
free-running clocks. However, the general timing relationship between data and the read clock shown in this figure
still applies.
f
For more information on DDR SDRAM and DDR2 SDRAM
specifications, refer to JEDEC standard publications JESD79C and
JESD79-2, respectively, from www.jedec.org, or see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 327: Interfacing DDR
SDRAM with Stratix II Devices.
RLDRAM II
RLDRAM II provides fast random access as well as high bandwidth and
high density, making this memory technology ideal for high-speed
network and communication data storage applications. The fast random
access speeds in RLDRAM II devices make them a viable alternative to
SRAM devices at a lower cost. Additionally, RLDRAM II devices have
minimal latency to support designs that require fast response times.
Interface Pins
RLDRAM II devices use interface pins such as data, clock, command, and
address pins. There are two types of RLDRAM II memory: common I/O
(CIO) and separate I/O (SIO). The data pins in a RLDRAM II CIO device
are bidirectional while the data pins in a RLDRAM II SIO device are
unidirectional. Instead of bidirectional data strobes, RLDRAM II uses
differential free-running read and write clocks to accompany the data. As
in DDR or DDR2 SDRAM, data is sent and captured at twice the system
clock rate by transferring data on the clock’s positive and negative edge.
The commands and addresses still only use one active (positive) edge of
a clock.
If the data pins are bidirectional, as in RLDRAM II CIO devices, connect
them to Stratix II and Stratix II GX DQ pins. If the data pins are
unidirectional, as in RLDRAM II SIO devices, connect the RLDRAM II
device Q ports to the Stratix II and Stratix II GX device DQ pins and
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
connect the D ports to any user I/O pins in I/O banks 3, 4, 7, or 8 for
optimal performance. RLDRAM II also uses active-high data mask, DM,
pins for writes. You can connect DM pins to any of the I/O pins in the
same bank as the DQ pins of the FPGA when interfacing with
RLDRAM II CIO devices to any of the I/O pins in the same bank as the D
pins when interfacing with RLDRAM II SIO devices. There is one DM pin
per RLDRAM II device. You can also use I/O pins in banks 1, 2, 5, or 6 to
interface with RLDRAM II devices. However, these banks do not have
dedicated circuitry and can only support RLDRAM II devices at speeds
up to 200 MHz. RLDRAM II interfaces using these banks are supported
using the 1.8-V HSTL Class I I/O support.
Connect the RLDRAM II device’s read clock pins (QK) to Stratix II or
Stratix II GX DQS pins. Because of software requirements, you must
configure the DQS signals as bidirectional pins. However, since QK pins
are output-only pins from the memory, RLDRAM II memory interfacing
in Stratix II and Stratix II GX devices requires that you ground the DQS
pin output enables. Stratix II and Stratix II GX devices use the shifted QK
signal from the DQS logic block to capture data. You can leave the QK#
signal of the RLDRAM II device unconnected, as DQS and DQSn in
Stratix II and Stratix II GX devices are not differential pins.
RLDRAM II devices also have input clocks (CK and CK#) and write
clocks (DK and DK#).
You can use any of the user I/O pins for commands and addresses.
RLDRAM II also offers QVLD pins to indicate the read data availability.
Connect the QVLD pins to the Stratix II or Stratix II GX DQVLD pins,
listed in the pin table.
1
Because the Quartus II software treats the DQVLD pins like DQ
pins, you should ensure that the DQVLD pin is assigned to the
pin table’s recommended pin.
Read and Write Operations
When reading from the RLDRAM II device, data is sent edge-aligned
with the read clock QK and QK#. When writing to the RLDRAM II device,
data must be center-aligned with the write clock (DK and DK#). The
RLDRAM II interface uses the same scheme as in DDR or DDR2 SDRAM
interfaces, where the dedicated circuitry is used during reads to
center-align the data and the read clock inside the FPGA and the PLL
center-aligns the data and write clock outputs. The data and clock
relationship for reads and writes in RLDRAM II is similar to those in DDR
and DDR2 SDRAM as shown in Figures 3–3 and 3–4.
Altera Corporation
January 2008
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External Memory Standards
f
For details on RLDRAM II, see AN 325: Interfacing RLDRAM II with
Stratix II & Stratix GX Devices.
QDRII SRAM
QDRII SRAM is the second generation of QDR SRAM devices. Both
devices can transfer four words per clock cycle, fulfilling the
requirements facing next-generation communications system designers.
QDRII SRAM devices provide concurrent reads and writes, zero latency,
and increased data throughput, allowing simultaneous access to the same
address location. QDRII SRAM is available in burst-of-2 and burst-of-4
devices. Burst-of-2 devices support two-word data transfer on all read
and write transactions, and burst-of-4 devices support four-word data
transfer
Interface Pins
QDRII SRAM uses two separate, unidirectional data ports for read and
write operations, enabling QDR data transfer. QDRII SRAM uses shared
address lines for reads and writes. QDRII SRAM burst-of-two devices
sample the read address on the rising edge of the clock and sample the
write address on the falling edge of the clock while QDRII SRAM
burst-of-four devices sample both read and write addresses on the clock’s
rising edge. Connect the memory device’s Q ports (read data) to the
Stratix II or Stratix II GX DQ pins. You can use any of the Stratix II or
Stratix II GX device user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports
(write data), commands, and addresses. The control signals are sampled
on the rising edge of the clock. You can also use I/O pins in banks 1, 2, 5,
or 6 to interface with QDRII SRAM devices. However, these banks do not
have dedicated circuitry and can only support QDRII SRAM devices at
speeds up to 200 MHz. QDRII SRAM interfaces using these banks are
supported using the 1.8-V HSTL Class I I/O support.
QDRII SRAM uses the following clock signals:
■
■
■
Input clocks K and K#
Output clocks C and C#
Echo clocks CQ and CQ#
Clocks C#, K#, and CQ# are logical complements of clocks C, K, and CQ,
respectively. Clocks C, C#, K, and K# are inputs to the QDRII SRAM while
clocks CQ and CQ# are outputs from the QDRII SRAM. Stratix II and
Stratix II GX devices use single-clock mode for single-device QDRII
SRAM interfacing where the K and K# are used for write operations, and
CQ and CQ# are used for read operations. You should use both C or C#
and K or K# clocks when interfacing with a bank of multiple QDRII
SRAM devices with a single controller.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
You can generate C, C#, K, and K# clocks using any of the I/O registers
via the DDR registers. Because of strict skew requirements between K and
K# signals, use adjacent pins to generate the clock pair.
Connect CQ and CQ# pins to the Stratix II or Stratix II GX DQS and DQSn
pins for DLL-based implementations. You must configure DQS and
DQSn as bidirectional pins. However, since CQ and CQ# pins are
output-only pins from the memory, the Stratix II or Stratix II GX device
QDRII SRAM memory interface requires that you ground the DQS and
DQSn output enable. To capture data presented by the memory, connect
the shifted CQ signal to the input latch and connect the active-high input
registers and the shifted CQ# signal is connected to the active-low input
register. For PLL-based implementations, connect QK to the input of the
read PLL and leave QK# unconnected.
Read and Write Operations
Figure 3–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. Data is output one-and-a-half
clock cycles after a read command is latched into memory. QDRII SRAM
devices send data within a tCO time after each rising edge of the read clock
C or C# in multi-clock mode, or the input clock K or K# in single clock
mode. Data is valid until tDOH time after each rising edge of the read clock
C or C# in multi-clock mode or the input clock K or K# in single clock
mode. The CQ and CQ# clocks are edge-aligned with the read data signal.
These clocks accompany the read data for data capture in Stratix II and
Stratix II GX devices.
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January 2008
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External Memory Standards
Figure 3–5. Data and Clock Relationship During a QDRII SRAM Read
Note (1)
C/K
C#/K#
tCO (2)
Q
tCO (2)
QA
tCLZ (3)
QA + 1
tDOH (2)
QA + 2
QA + 3
tCHZ (3)
CQ
tCQD (4)
CQ#
tCCQO (5)
tCQOH (5)
tCQD (4)
Notes to Figure 3–5:
(1)
(2)
(3)
(4)
(5)
This relationship is at the memory device. The timing parameter nomenclature is based on the Cypress QDRII
SRAM data sheet for CY7C1313V18.
tCO is the data clock-to-out time and tDOH is the data output hold time between burst.
tCLZ and tCHZ are bus turn-on and turn-off times respectively.
tCQD is the skew between the rising edge of CQ or CQ# and the data edges.
tCCQO and tCQOH are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)
and the CQ or CQ# clocks.
When reading from the QDRII SRAM, data is sent edge-aligned with the
rising edge of the echo clocks CQ and CQ#. Both CQ and CQ# are shifted
inside the FPGA using DQS and DQSn logic blocks to capture the data in
the DDR IOE registers in DLL-based implementations. In PLL-based
implementations, CQ feeds a PLL, which generates the clock to capture
the data in the DDR IOE registers.
When writing to QDRII SRAM devices, data is generated by the write
clock while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
Read and write operations occur during the same clock cycle on
independent read and write data paths along with the cycle-shared
address bus. Performing concurrent reads and writes does not change the
functionality of either transaction. If a read request occurs simultaneously
with a write request at the same address, the new data on D is forwarded
to Q. Therefore, latency is not required to access valid data.
f
For more information on QDRII SRAM, go to www.qdrsram.com or see
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &
Stratix GX Devices.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Stratix II and
Stratix II GX
DDR Memory
Support
Overview
This section describes Stratix II and Stratix II GX features that enable
high-speed memory interfacing. It first describes Stratix II and
Stratix II GX memory pins and then the DQS phase-shift circuitry and the
DDR I/O registers. Table 3–2 shows the I/O standard associated with the
external memory interfaces.
Table 3–2. External Memory Support in Stratix II and Stratix II GX Devices
Memory Standard
I/O Standard
DDR SDRAM
SSTL-2 Class II
DDR2 SDRAM
SSTL-18 Class II(1)
RLDRAM II (2)
1.8-V HSTL Class I or II (1)
QDRII SRAM (2)
1.8-V HSTL Class I or II (1)
Notes to Table 3–2:
(1)
(2)
Stratix II and Stratix II GX devices support 1.8-V HSTL/SSTL-18 Class I and II
I/O standards in I/O banks 3, 4, 7, and 8. In I/O banks 1, 2, 5, and 6, Class I is
supported for both input and output operations, while Class II is only supported
for input operations for these I/O standards.
For maximum performance, Altera recommends using the 1.8-V HSTL I/O
standard. RLDRAM II and QDRII SRAM devices also support the 1.5-V HSTL
I/O standard.
Stratix II and Stratix II GX devices support the data strobe or read clock
signal (DQS) used in DDR SDRAM, DDR2 SDRAM, RLDRAM II, and
QDRII SRAM devices with dedicated circuitry. Stratix II and Stratix II GX
devices also support the DQSn signal (the DQS complement signal) for
external memory types that require them, for example QDRII SRAM.
DQS and DQSn signals are usually associated with a group of data (DQ)
pins. However, these are not differential buffers and cannot be used in
DDR2 SDRAM or RLDRAM II interfaces.
1
f
You can also interface with these external memory devices
without the use of dedicated circuitry at a lower performance.
For more information, see the appropriate Stratix II or Stratix II GX
memory interfaces application note available at www.altera.com.
Stratix II and Stratix II GX devices contain dedicated circuitry to shift the
incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°,
120°, or 144°, depending on the delay-locked loop (DLL) mode. There are
four DLL modes. The DQS phase-shift circuitry uses a frequency
reference to dynamically generate control signals for the delay chains in
each of the DQS and DQSn pins, allowing it to compensate for process,
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January 2008
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Stratix II and Stratix II GX DDR Memory Support Overview
voltage, and temperature (PVT) variations. This phase-shift circuitry has
been enhanced in Stratix II and Stratix II GX devices to support more
phase-shift options with less jitter.
Besides the DQS dedicated phase-shift circuitry, each DQS and DQSn pin
has its own DQS logic block that sets the delay for the signal input to the
pin. Using the DQS dedicated phase-shift circuitry with the DQS logic
block allows for phase-shift fine-tuning. Additionally, every IOE in a
Stratix II or Stratix II GX device contains six registers and one latch to
achieve DDR operation.
DDR Memory Interface Pins
Stratix II and Stratix II GX devices use data (DQ), data strobe (DQS and
DQSn), and clock pins to interface with external memory.
Figure 3–6 shows the DQ, DQS, and DQSn pins in the Stratix II or
Stratix II GX I/O banks on the top of the device. A similar arrangement is
repeated at the bottom of the device.
Figure 3–6. DQ and DQS Pins Per I/O Bank
Up to 8 Sets of
DQ & DQS Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
I/O
Bank 3
DQSn
Pin
DQ
Pins
PLL 11
PLL 5
I/O
Bank 11
I/O
Bank 9
DQS
Pin
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
Pin
DQS
Pin
Data and Data Strobe Pins
Stratix II and Stratix II GX data pins for the DDR memory interfaces are
called DQ pins. Stratix II and Stratix II GX devices can use either
bidirectional data strobes or unidirectional read clocks. Depending on the
external memory interface, either the memory device’s read data strobes
or read clocks feed the Stratix II or Stratix II GX DQS (and DQSn) pins.
3–14
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Stratix II and Stratix II GX DQS pins connect to the DQS pins in DDR and
DDR2 SDRAM interfaces or to the QK pins in RLDRAM II interfaces. The
DQSn pins are not used in these interfaces. Connect the Stratix II or
Stratix II GX DQS and DQSn pins to the QDRII SRAM CQ and CQ# pins,
respectively.
In every Stratix II or Stratix II GX device, the I/O banks at the top (I/O
banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR
memory up to 300 MHz/600 Mbps (with RLDRAM II). These I/O banks
support DQS signals and its complement DQSn signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
In ×4 mode, each DQS/DQSn pin drives up to four DQ pins within that
group. In ×8/×9 mode, each DQS/DQSn pin drives up to nine DQ pins
within that group to support one parity bit and the eight data bits. If the
parity bit or any data bit is not used, the extra DQ pins can be used as
regular user I/O pins. Similarly, with ×16/×18 and ×32/×36 modes, each
DQS/DQSn pin drives up to 18 and 36 DQ pins respectively. There are
two parity bits in the ×16/×18 mode and four parity bits in the ×32/×36
mode. Tables 3–3 through 3–6 show the number of DQS/DQ groups and
non-DQS /DQ supported in each Stratix II or Stratix II GX
density/package combination, respectively, for DLL-based
implementations.
Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 1 of 2)
Number of
×4 Groups
Number of
×8/×9 Groups
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
484-pin Hybrid FineLine BGA
8
4
0
0
Device
EP2S15
EP2S30
EP2S60
EP2S90
Note (1)
Package
Number of
Number of
×16/×18 Groups ×32/×36 Groups
780-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
EP2S130 780-pin FineLine BGA
Altera Corporation
January 2008
3–15
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 2 of 2)
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
EP2S180 1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
Device
Package
Number of
Number of
×16/×18 Groups ×32/×36 Groups
Note to Table 3–3:
(1)
Check the pin table for each DQS/DQ group in the different modes.
Table 3–4. Stratix II non-DQS and DQ Bus Mode Support
Device
Package
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
13
7
Number of
Number of
×16/×18 Groups ×32/×36 Groups
EP2S15
484-pin FineLine BGA
672-pin FineLine BGA
24
9
4
2
EP2S30
484-pin FineLine BGA
13
7
3
1
672-pin FineLine BGA
36
15
7
3
EP2S60
484-pin FineLine BGA
13
7
3
1
EP2S90
3
1
672-pin FineLine BGA
36
15
7
3
1,020-pin FineLine BGA
51
26
13
6
780-pin FineLine BGA
40
24
12
6
1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
40
24
12
6
1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
EP2S180 1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
EP2S130 780-pin FineLine BGA
Note to Table 3–4:
(1)
Check the pin table for each DQS/DQ group in the different modes.
3–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–5. Stratix II GX DQS and DQ Bus Mode Support
Device
Package
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
Number of
×16/×18 Groups ×32/×36 Groups
EP2SGX30C
EP2SGX30D
780-pin FineLine BGA
18
8
4
0
EP2SGX60C
EP2SGX60D
780-pin FineLine BGA
18
8
4
0
EP2SGX60E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90F
1,508-pin FineLine BGA
36
18
8
4
EP2SGX130G 1,508-pin FineLine BGA
36
18
8
4
Note to Table 3–5:
(1)
Check the pin table for each DQS/DQ group in the different modes.
Table 3–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)
Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
Number of
×16/×18 Groups ×32/×36 Groups
8
4
2
EP2SGX30
780-pin FineLine BGA
18
EP2SGX60
780-pin FineLine BGA
18
8
4
2
1,152-pin FineLine BGA
25
13
6
3
EP2SGX90
EP2SGX130
1,152-pin FineLine BGA
25
13
6
3
1,508-pin FineLine BGA
25
12
6
3
1,508-pin FineLine BGA
25
12
6
3
Note to Table 3–6:
(1)
Check the pin table for each DQS/DQ group in the different modes.
1
Altera Corporation
January 2008
To support the RLDRAM II QVLD pin, some of the unused ×4
DQS pins, whose DQ pins were combined to make the bigger
×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
The DQS pins are listed in the Stratix II or Stratix II GX pin tables as
DQS[17..0]T or DQS[17..0]B. The T denotes pins on the top of the
device and the B denotes pins on the bottom of the device. The
complement DQSn pins are marked as DQSn[17..0]T or
DQSn[17..0]B. The corresponding DQ pins are marked as
DQ[17..0]T[3..0], where [17..0] indicates which DQS group the
pins belong to. Similarly, the corresponding DQVLD pins are marked as
DQVLD[8..0]T, where [8..0] indicates which DQS group the pins
belong to. The numbering scheme starts from right to left on the package
bottom view. When not used as DQ, DQS, or DQSn pins, these pins are
available as regular I/O pins. Figure 3–7 shows the DQS pins in Stratix II
or Stratix II GX I/O banks.
1
The Quartus II software treats DQVLD pins as regular DQ pins.
Therefore, you must ensure that the DQVLD pin assigned in
your design corresponds to the pin table’s recommended
DQVLD pins.
Figure 3–7. DQS Pins in Stratix II and Stratix II GX I/O Banks
Notes (1), (2), (3)
Up to 8 Sets of
DQ & DQS Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
I/O
Bank 3
DQSn
Pin
DQS
Pin
DQ
Pins
PLL 11
PLL 5
I/O
Bank 11
I/O
Bank 9
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
Pin
DQS
Pin
Notes to Figure 3–7:
(1)
(2)
(3)
There are up to 18 pairs of DQS and DQSn pins on both the top and bottom of the device. See Table 3–3 for the exact
number of DQS and DQSn pin pairs in each device package.
See Table 3–7 for the available DQS and DQSn pins in each mode and package.
Each DQS pin has a complement DQSn pin. DQS and DQSn pins are not differential.
The DQ pin numbering is based on ×4 mode. There are up to 8 DQS/DQ
groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ groups in
×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4 DQS/DQ
groups plus one parity pin are combined; one pair of DQS/DQSn pins
from the combined groups can drive all the DQ and parity pins. Since
there is an even number of DQS/DQ groups in an I/O bank, combining
groups is efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQ
groups plus two parity pins are combined and one pair of DQS/DQSn
pins from the combined groups can drive all the DQ and parity pins. In
3–18
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
×32/×36 mode, eight adjacent DQS/DQ groups are combined and one
pair of DQS/DQSn pins can drive all the DQ and parity pins in the
combined groups.
Table 3–7 shows which DQS and DQSn pins are available in each mode
and package in the Stratix II or Stratix II GX device family.
Table 3–7. Available DQS and DQSn Pins in Each Mode and Package
Note (1)
Package
Mode
484-Pin FineLine BGA
484-Pin Hybrid FineLine BGA
672-Pin FineLine BGA
780-Pin FineLine BGA
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
×4
7, 9, 11, 13
Odd-numbered pins only
All DQS and DQSn pins
×8/×9
7,11
3, 7, 11, 15
Even-numbered pins only
×16/×18
N/A
5, 13
3, 7, 11, 15
×32/×36
N/A
N/A
5, 13
Note to Table 3–7:
(1)
The numbers correspond to the DQS and DQSn pin numbering in the Stratix II or Stratix II GX pin table. There are
two sets of DQS/DQ groups, one corresponding with the top side of the device and one with the bottom side of
the device.
1
On the top and bottom side of the device, the DQ and DQS pins
must be configured as bidirectional DDR pins to enable the DQS
phase-shift circuitry. The DQSn pins can be configured as input,
output, or bidirectional pins. You can use the altdq and
altdqs megafunctions to configure the DQ and DQS/DQSn
paths, respectively. However, Altera highly recommends that
you use the respective Altera memory controller IP Tool Bench
for your external memory interface data paths. The data path is
clear-text and free to use. You are responsible for your own
timing analysis if you use your own data path. If you only want
to use the DQ and/or DQS pins as inputs, you need to set the
output enable of the DQ and/or DQS pins to ground.
Stratix II or Stratix II GX side I/O banks (I/O banks 1, 2, 5, and 6) support
all the memory interfaces supported in the top and bottom I/O banks. For
optimal performance, use the Altera memory controller IP Tool Bench to
pick the data and strobe pins for these interfaces. Since these I/O banks
do not have any dedicated circuitry for memory interfacing, they can
support DDR SDRAM at speeds up to 150 MHz and other DDR memories
at speeds up to 200 MHz. You need to use the SSTL-18 Class I I/O
standard when interfacing with DDR2 SDRAM devices using pins in I/O
bank 1, 2, 5, or 6. These I/O banks do not support the SSTL-18 Class II and
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
1.8-V HSTL Class II I/O standards on output and bidirectional pins, but
you can use SSTL-18 Class I or 1.8-V HSTL Class I I/O standards for
memory interfaces.
1
The Altera memory controller IP Tool Bench generates the
optimal pin constraints that allow you to interface these
memories at high frequency.
Table 3–8 shows the maximum clock rate supported for the DDR SDRAM
interface in the Stratix II or Stratix II GX device side I/O banks.
Table 3–8. Maximum Clock Rate for DDR and DDR2 SDRAM in Stratix II or Stratix II GX Side I/O Banks
Stratix II or Stratix II GX
Device Speed Grade
DDR SDRAM
(MHz)
DDR2 SDRAM
(MHz)
QDRII SRAM
(MHz)
RLDRAM II
(MHz)
-3
150
200
200
200
-4
133
167
167
175
-5
133
167
167
175
Clock Pins
You can use any of the DDR I/O registers to generate clocks to the
memory device. For better performance, use the same I/O bank as the
data and address/command pins.
Command and Address Pins
You can use any of the user I/O pins in the top or bottom bank of the
device for commands and addresses. For better performance, use the
same I/O bank as the data pins.
Other Pins (Parity, DM, ECC and QVLD Pins)
You can use any of the DQ pins for the parity pins in Stratix II and
Stratix II GX devices. The Stratix II or Stratix II GX device family has
support for parity in the ×8/×9, ×16/×18, and ×32/×36 mode. There is
one parity bit available per 8 bits of data pins.
The data mask, DM, pins are only required when writing to DDR
SDRAM, DDR2 SDRAM, and RLDRAM II devices. A low signal on the
DM pins indicates that the write is valid. If the DM signal is high, the
memory will mask the DQ signals. You can use any of the I/O pins in the
same bank as the DQ pins (or the RLDRAM II SIO’s and QDRII SRAM’s
D pins) for the DM signals. Each group of DQS and DQ signals in DDR
3–20
Stratix II Device Handbook, Volume 2
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
and DDR2 SDRAM devices requires a DM pin. There is one DM pin per
RLDRAM II device. The DDR I/O output registers, clocked by the –90°
shifted clock, creates the DM signals, similar to DQ output signals.
1
Perform timing analysis to calculate your write-clock phase
shift.
Some DDR SDRAM and DDR2 SDRAM devices support error correction
coding (ECC), which is a method of detecting and automatically
correcting errors in data transmission. In a 72-bit DDR SDRAM interface,
there are eight ECC pins in addition to the 64 data pins. Connect the DDR
and DDR2 SDRAM ECC pins to a Stratix II or Stratix II GX device
DQS/DQ group. The memory controller needs extra logic to encode and
decode the ECC data.
QVLD pins are used in RLDRAM II interfacing to indicate the read data
availability. There is one QVLD pin per RLDRAM II device. A high on
QVLD indicates that the memory is outputting the data requested.
Similar to DQ inputs, this signal is edge-aligned with QK/QK# signals
and is sent half a clock cycle before data starts coming out of the memory.
You need to connect QVLD pins to the DQVLD pin on the Stratix II or
Stratix II GX device. The DQVLD pin can be used as a regular user I/O
pin if not used for QVLD. Because the Quartus II software does not
differentiate DQVLD pins from DQ pins, you must ensure that your
design uses the pin table’s recommended DQVLD pin.
DQS Phase-Shift Circuitry
The Stratix II or Stratix II GX phase-shift circuitry and the DQS logic
block control the DQS and DQSn pins. Each Stratix II or Stratix II GX
device contains two phase-shifting circuits. There is one circuit for I/O
banks 3 and 4, and another circuit for I/O banks 7 and 8. The phaseshifting circuit on the top of the device can control all the DQS and DQSn
pins in the top I/O banks and the phase-shifting circuit on the bottom of
the device can control all the DQS and DQSn pins in the bottom I/O
banks. Figure 3–8 shows the DQS and DQSn pin connections to the DQS
logic block and the DQS phase-shift circuitry.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–8. DQS and DQSn Pins and the DQS Phase-Shift Circuitry
Note (1)
From PLL 5 (3)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
CLK[15..12]p (2)
DQS
Phase-Shift
Circuitry
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS Logic
Blocks
Notes to Figure 3–8:
(1)
(2)
(3)
There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II or Stratix II GX
device, up to 8 on the left side of the DQS phase-shift circuitry (I/O banks 3 and 8), and up to 10 on the right side
(I/O bank 4 and 7).
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase-shift circuitry on the bottom of the device. You can also use a phase-locked loop (PLL) clock output as a
reference clock to the phase-shift circuitry. The reference clock can also be used in the logic array.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Figure 3–9 shows the connections between the DQS phase-shift circuitry
and the DQS logic block.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Note (1)
CLRN
(6)
PRN
Q SCLR
DQS bus
EnableN
DQS'
NOT
A
EN
DQS Logic Block (2)
EN
DQS or DQSn
DQS Delay
Settings to and from the
Logic Array (5)
6
Delay Chains
clock enable
upndn
Phase
Comparator
Input reference
clock (4)
DLL
DQS Phase-Shift Circuitry (3)
Up/Down
Counter
6
6
Phase
Offset
Control
DQS Delay
Settings from the
DQS Phase-Shift
Circuitry
6
6
Phase offset
settings from the
logic array
addnsub
DQS or DQSn
Phase Offset
Settings
D
DQS Logic Block (2)
DQS or DQSn
DQS Logic Block (2)
Q
6
6
6
Bypass
D
Q
6
6
DQS Delay Chain
Update
Enable
Circuitry
B
Postamble Circuitry
gated_dqs control
reset
DFF
VCC
Figure 3–9. DQS Phase-Shift Circuitry and DQS Logic Block Connections
Notes to Figure 3–9:
(1)
(2)
(3)
(4)
(5)
(6)
All features of the DQS phase-shift circuitry and the DQS logic block are accessible from the altdqs megafunction
in the Quartus II software. You should, however, use Altera’s memory controller IP Tool Bench to generate the data
path for your memory interface.
DQS logic block is available on every DQS and DQSn pin.
There is one DQS phase-shift circuit on the top and bottom side of the device.
The input reference clock can come from CLK[15..12]p or PLL 5 for the DQS phase-shift circuitry on the top side
of the device or from CLK[7..4]p or PLL 6 for the DQS phase-shift circuitry on the bottom side of the device.
Each individual DQS and DQSn pair can have individual DQS delay settings to and from the logic array.
This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
The phase-shift circuitry is only used during read transactions where the
DQS and DQSn pins are acting as input clocks or strobes. The phase-shift
circuitry can shift the incoming DQS signal by 0°, 22.5°, 30°, 36°, 45°, 60°,
67.5°, 72°, 90°, 108°, 120°, or 144°. The shifted DQS signal is then used as
clocks at the DQ IOE input registers.
Figure 3–3 shows an example where the DQS signal is shifted by 90°. The
DQS signals goes through the 90° shift delay set by the DQS phase-shift
circuitry and the DQS logic block and some routing delay from the DQS
pin to the DQ IOE registers. The DQ signals only goes through routing
delay from the DQ pin to the DQ IOE registers and maintains the 90°
relationship between the DQS and DQ signals at the DQ IOE registers
since the software will automatically set delay chains to match the routing
delay between the pins and the IOE registers for the DQ and DQS input
paths.
All 18 DQS and DQSn pins on either the top or bottom of the device can
have their input signal phase shifted by a different degree amount but all
must be referenced at one particular frequency. For example you can have
a 90° phase shift on DQS0T and have a 60° phase shift on DQS1T both
referenced from a 200-MHz clock. Not all phase-shift combinations are
supported, however. The phase shifts on the same side of the device must
all be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), or a
multiple of 36° (up to 144°).
In order to generate the correct phase shift with the DLL used, you must
provide a clock signal of the same frequency as the DQS signal to the DQS
phase-shift circuitry. Any of the CLK[15..12]p clock pins can feed the
phase circuitry on the top of the device (I/O banks 3 and 4) or any of the
CLK[7..4]p clock pins can feed the phase circuitry on the bottom of the
device (I/O banks 7 and 8). Stratix II and Stratix II GX devices can also
use PLLs 5 or 6 as the reference clock to the DQS phase-shift circuitry on
the top or bottom of the device, respectively. PLL 5 is connected to the
DQS phase-shift circuitry on the top side of the device and PLL 6 is
connected to the DQS phase-shift circuitry on the bottom side of the
device. Both the top and bottom phase-shift circuits need unique clock
pins or PLL clock outputs for the reference clock.
1
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Stratix II Device Handbook, Volume 2
When you have a PLL dedicated only to generate the DLL input
reference clock, you must set the PLL mode to “No
Compensation” or the Quartus® II software will change it
automatically. Because there are no other PLL outputs used, the
PLL doesn’t need to compensate for any clock paths.
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
DLL
The DQS phase-shift circuitry uses a delay-locked loop (DLL) to
dynamically measure the clock period needed by the DQS/DQSn pin (see
Figure 3–10). The DQS phase-shift circuitry then uses the clock period to
generate the correct phase shift. The DLL in the Stratix II or Stratix II GX
DQS phase-shift circuitry can operate between 100 and 400 MHz. The
phase-shift circuitry needs a maximum of 256 clock cycles to calculate the
correct input clock period. Data sent during these clock cycles may not be
properly captured.
1
Although the DLL can run up to 400 MHz, other factors may
prevent you from interfacing with a 400-MHz external memory
device.
1
You can still use the DQS phase-shift circuitry for any memory
interfaces that are less than 100 MHz. The DQS signal will be
shifted by 2.5 ns and you can add more shift by using the phase
offset module. Even if the DQS signal is not shifted exactly to the
middle of the DQ valid window, the IOE should still be able to
capture the data in this low frequency application.
There are four different frequency modes for the Stratix II or Stratix II GX
DLL. Each frequency mode provides different phase shift, as shown in
Table 3–9.
Table 3–9. Stratix II and Stratix II GS DLL Frequency Modes
Available
Number of
Phase Shift Delay Chains
Frequency
Mode
Frequency Range (MHz)
0
100–175
30, 60, 90,
120
12
1
150–230
22.5, 45,
67.5, 90
16
2
200–310
30, 60, 90,
120
12
3
240–400 (C3 speed grade)
240–350 (C4 and C5 speed grades)
36, 72, 108,
144
10
In frequency mode 0, Stratix II devices use a 6-bit setting to implement the
phase-shift delay. In frequency modes 1, 2, and 3, Stratix II devices only
use a 5-bit setting to implement the phase-shift delay.
The DLL can be reset from either the logic array or a user I/O pin. This
signal is not shown in Figure 3–10. Each time the DLL is reset, you must
wait for 256 clock cycles before you can capture the data properly.
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January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Table 3–10 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 3–10. DQS Delay Buffer Maximum Delay in Fast Timing Model
Frequency
Mode
Maximum Delay Per Delay Buffer
(Fast Timing Model)
Unit
0
0.833
ns
1, 2, 3
0.416
ns
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–10. Simplified Diagram of the DQS Phase-Shift Circuitry
Note (1)
addnsub
Phase offset settings
from the logic array
DLL
6
Input reference
clock (2)
Phase
Offset
Control
upndn
Phase
Comparator
clock enable
Up/Down
Counter
6
Phase offset
settings (3)
6
Delay Chains
6
DQS delay
settings (4)
6
Notes to Figure 3–10:
(1)
(2)
(3)
(4)
All features of the DQS phase-shift circuitry are accessible from the altdqs megafunction in the Quartus II software.
You should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory
interface.
The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the bottom side of the
device can come from CLK[7..4]p or PLL 6.
Phase offset settings can only go to the DQS logic blocks.
DQS delay settings can go to the logic array and/or to the DQS logic block.
The input reference clock goes into the DLL to a chain of up to 16 delay
elements. The phase comparator compares the signal coming out of the
end of the delay element chain to the input reference clock. The phase
comparator then issues the upndn signal to the up/down counter. This
signal increments or decrements a six-bit delay setting (DQS delay
settings) that will increase or decrease the delay through the delay
element chain to bring the input reference clock and the signals coming
out of the delay element chain in phase.
The DQS delay settings contain the control bits to shift the signal on the
input DQS pin by the amount set in the altdqs megafunction. For the 0°
shift, both the DLL and the DQS logic block are bypassed. Since Stratix II
and Stratix II GX DQS and DQ pins are designed such that the pin to IOE
delays are matched, the skew between the DQ and DQS pin at the DQ IOE
registers is negligible when the 0° shift is implemented. You can feed the
DQS delay settings to the DQS logic block and the logic array.
Altera Corporation
January 2008
3–27
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Phase Offset Control
The DQS phase-shift circuitry also contains a phase offset control module
that can add or subtract a phase offset amount from the DQS delay setting
(phase offset settings from the logic array in Figure 3–10). You should use
the phase offset control module for making small shifts to the input signal
and use the DQS phase-shift circuitry for larger signal shifts. For example,
if you need the input signal to be shifted by 75°, you can set the altdqs
megafunction to generate a 72° phase shift with a phase offset of +3°.
You can either use a static phase offset or a dynamic phase offset to
implement the additional phase shift. The available additional phase shift
is implemented in 2s-complement between settings –64 to +63 for
frequency mode 0, and between settings –32 to +31 for frequency modes
1, 2, and 3. However, the DQS delay settings are at the maximum at
setting 64 for frequency mode 0, and at the maximum at setting 32 for
frequency modes 1, 2, and 3. Therefore, the actual physical offset setting
range will be 64 or 32 subtracted by the DQS delay settings from the DLL.
For example, if the DLL determines that to achieve 30° you will need a
DQS delay setting of 28, you can subtract up to 28 phase offset settings
and you can add up to 36 phase offset settings to achieve the optimal
delay.
1
Each phase offset setting translates to a certain delay, as
specified in the DC & Switching Characteristics of Stratix III
Devices chapter in volume 2 of the Stratix III Device Handbook.
When using the static phase offset, you can specify the phase offset
amount in the altdqs megafunction as a positive number for addition or
a negative number for subtraction. You can also have a dynamic phase
offset that is always added to, subtracted from, or both added to and
subtracted from the DLL phase shift. When you always add or subtract,
you can dynamically input the phase offset amount into the
dll_offset[5..0] port. When you want to both add and subtract
dynamically, you control the addnsub signal in addition to the
dll_offset[5..0] signals.
DQS Logic Block
Each DQS and DQSn pin is connected to a separate DQS logic block (see
Figure 3–11). The logic block contains DQS delay chains and postamble
circuitry.
3–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Note (1)
CLRN
(3)
PRN
Q SCLR
DQS bus
EnableN
DQS'
NOT
A
EN
Input Reference
Clock (2)
EN
D
6
DQS Delay
Settings from the
DQS PhaseShift Circuitry
Phase Offset
Settings
6
6
DQS or
DQSn Pin
Bypass
Q
6
6
6
D
Q
6
6
DQS Delay Chain
Update
Enable
Circuitry
B
Postamble Circuitry
gated_dqs control
reset
DFF
VCC
Figure 3–11. Simplified Diagram of the DQS Logic Block
Notes to Figure 3–11:
(1)
(2)
(3)
All features of the DQS logic block are accessible from the altdqs megafunction in the Quartus II software. You
should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory interface.
The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the top side of the device
can come from CLK[7..4]p or PLL 6.
This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
3–29
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
DQS Delay Chains
The DQS delay chains consist of a set of variable delay elements to allow
the input DQS and DQSn signals to be shifted by the amount given by the
DQS phase-shift circuitry or the logic array. There are four delay elements
in the DQS delay chain; the first delay chain closest to the DQS pin can
either be shifted by the DQS delay settings or by the sum of the DQS delay
setting and the phase-offset setting. The number of delay chains used is
transparent to the users because the altdqs megafunction automatically
sets it. The DQS delay settings can come from the DQS phase-shift
circuitry on the same side of the device as the target DQS logic block or
from the logic array. When you apply a 0° shift in the altdqs
megafunction, the DQS delay chains are bypassed.
The delay elements in the DQS logic block mimic the delay elements in
the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own 6- or 5-bit settings using the
dqs_delayctrlin[5..0] signals available in the altdqs
megafunction. These settings control 1, 2, 3, or all 4 delay elements in the
DQS delay chains. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps
and the value of the delay steps.
Both the DQS delay settings and the phase-offset settings pass through a
latch before going into the DQS delay chains. The latches are controlled
by the update enable circuitry to allow enough time for any changes in
the DQS delay setting bits to arrive to all the delay elements. This allows
them to be adjusted at the same time. The update enable circuitry enables
the latch to allow enough time for the DQS delay settings to travel from
the DQS phase-shift circuitry to all the DQS logic blocks before the next
change. It uses the input reference clock to generate the update enable
output. The altdqs megafunction uses this circuit by default. See
Figure 3–12 for an example waveform of the update enable circuitry
output.
The shifted DQS signal then goes to the DQS bus to clock the IOE input
registers of the DQ pins. It can also go into the logic array for
resynchronization purposes. The shifted DQSn signal can only go to the
active-low input register in the DQ IOE and is only used for QDRII SRAM
interfaces.
3–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–12. DQS Update Enable Waveform
DLL Counter Update
(Every Eight Cycles)
DLL Counter Update
(Every Eight Cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe like
DDR and DDR2 SDRAM, the DQS signal is low before going to or coming
from a high-impedance state. See Figure 3–3. The state where DQS is low,
just after a high-impedance state, is called the preamble and the state
where DQS is low, just before it returns to a high-impedance state, is
called the postamble. There are preamble and postamble specifications
for both read and write operations in DDR and DDR2 SDRAM. The DQS
postamble circuitry ensures data is not lost when there is noise on the
DQS line at the end of a read postamble time. It is to be used with one of
the DQS IOE input registers such that the DQS postamble control signal
can ground the shifted DQS signal used to clock the DQ input registers at
the end of a read operation. This ensures that any glitches on the DQS
input signals at the end of the read postamble time do not affect the DQ
IOE registers.
f
See AN 327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices for more details.
DDR Registers
Each IOE in a Stratix II or Stratix II GX device contains six registers and
one latch. Two registers and a latch are used for input, two registers are
used for output, and two registers are used for output enable control. The
second output enable register provides the write preamble for the DQS
strobe in the DDR external memory interfaces. This active low output
enable register extends the high-impedance state of the pin by a half clock
cycle to provide the external memory’s DQS write preamble time
specification. Figure 3–13 shows the six registers and the latch in the
Stratix II or Stratix II GX IOE and Figure 3–14 shows how the second OE
register extends the DQS high-impedance state by half a clock cycle
during a write operation.
Altera Corporation
January 2008
3–31
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–13. Bidirectional DDR I/O Path in Stratix II and Stratix II GX Devices
Note (1)
DFF
OE
(2)
D
Q
OR2
OE Register AOE (3)
1
0
(4)
DFF
D
Q
OE Register BOE (5)
DFF
datain_l
D
Q
0
1
TRI (6)
I/O Pin (7)
Output Register AO
DFF
Logic Array
datain_h
D
Q
Output Register BO
outclock
combout
DFF
dataout_h
Q
D
Input Register AI
LatchTCHLA
dataout_l
Q
D
DFF
neg_reg_out
Q
D
ENA
Latch C I
Input Register BI (8)
inclock
Notes to Figure 3–13:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All control signals can be inverted at the IOE. The signal names used here match with Quartus II software naming
convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the AOE register during compilation.
The AOE register generates the enable signal for general-purpose DDR I/O applications.
This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
The BOE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.
The tristate enable is by default active low. You can, however, design it to be active high. The combinational control
path for the tristate is not shown in this diagram.
You can also have combinational output to the I/O pin; this path is not shown in the diagram.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–14. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note (1)
System clock
(outclock for DQS)
OE for DQS
(from logic array)
DQS
90˚
Delay
by Half
a Clock
Cycle
Preamble
Postamble
Write Clock
(outclock for DQ,
−90° phase shifted
from System Clock)
datain_h
(from logic array)
D0
D2
datain_l
(from logic array)
D1
D3
OE for DQ
(from logic array)
DQ
D0
D1
D2
D3
Note to Figure 3–14:
(1)
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the AOE
register D input.
Figures 3–15 and 3–16 summarize the IOE registers used for the DQ and
DQS signals.
Altera Corporation
January 2008
3–33
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–15. DQ Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
(2)
D
OE
Q
OE Register AOE
DFF
D
datain_l
Q
0
TRI
1
Output Register AO
DQ Pin
DFF
Logic Array
D
datain_h
Q
Output Register BO
outclock (3)
DFF
Q
D
dataout_h
Input Register AI
Latch
TCH
LA
Q
dataout_l
D
ENA
Latch C I
DFF
neg_reg_out
Q
D
(4)
Input Register BI (6)
inclock (from DQS bus)
(5)
Notes to Figure 3–15:
(1)
(2)
(3)
(4)
(5)
(6)
You can use the altdq megafunction to generate the DQ signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register AOE during compilation.
The outclock signal for DDR, DDR2 SDRAM, and QDRII SRAM interfaces has a 90° phase-shift relationship with
the system clock. For 300-MHz RLDRAM II interfaces with EP2S60F1020C3, Altera recommends a 75° phase-shift
relationship.
The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SRAM interfaces.
The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the
altdq megafunction to generate the DQ signals. Connect this port to the combout port in the altdqs
megafunction.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–16. DQS Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
OE
(2)
D
Q
OE Register AOE
OR2
1
0
(3)
DFF
D
Q
OE Register BOE
DFF
Logic Array
datain_h (4)
D
Q
TRI
Output Register AO
DQS Pin (5)
1
0
DFF
datain_l (4)
system clock
D
Q
Output Register BO
combout (7)
Notes to Figure 3–16:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
You can use the altdqs megafunction to generate the DQS signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OE register AOE during compilation. In RLDRAM II and QDRII SRAM, the OE signal is always
disabled.
The select line can be chosen in the altdqs megafunction.
The datain_l and datain_h pins are usually connected to ground and VCC, respectively.
DQS postamble circuitry and handling is not shown in this diagram. For more information, see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.
DQS logic blocks are only available with DQS and DQSn pins.
You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.
Altera Corporation
January 2008
3–35
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
For interfaces to DDR SDRAM, DDR2 SDRAM, and RLDRAM II, the
Stratix II or Stratix II GX DDR IOE structure requires you to invert the
incoming DQS signal to ensure proper data transfer. This is not required
for QDRII SRAM interfaces if the CQ signal is wired to the DQS pin and
the CQ# signal is wired to the DQSn pin. The altdq megafunction, by
default, adds the inverter to the inclock port when it generates DQ
blocks. The megafunction also includes an option to remove the inverter
for QDRII SRAM interfaces. As shown in Figure 3–13, the inclock
signal’s rising edge clocks the AI register, inclock signal’s falling edge
clocks the BI register, and latch CI is opened when inclock is 1. In a DDR
memory read operation, the last data coincides with DQS being low. If
you do not invert the DQS pin, you will not get this last data as the latch
does not open until the next rising edge of the DQS signal.
Figure 3–17 shows waveforms of the circuit shown in Figure 3–15.
The first set of waveforms in Figure 3–17 shows the edge-aligned
relationship between the DQ and DQS signals at the Stratix II or
Stratix II GX device pins. The second set of waveforms in Figure 3–17
shows what happens if the shifted DQS signal is not inverted; the last
data, Dn, does not get latched into the logic array as DQS goes to tristate
after the read postamble time. The third set of waveforms in Figure 3–17
shows a proper read operation with the DQS signal inverted after the 90°
shift; the last data, Dn, does get latched. In this case the outputs of register
AI and latch CI, which correspond to dataout_h and dataout_l ports,
are now switched because of the DQS inversion. Register AI, register BI,
and latch CI refer to the nomenclature in Figure 3–15.
3–36
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–17. DQ Captures with Non-Inverted and Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
Dn − 1
Dn
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted
by 90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Dn − 1
Dn − 2
Dn
Dn − 2
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Altera Corporation
January 2008
Dn − 2
Dn
Dn − 1
Dn − 3
Dn − 1
3–37
Stratix II Device Handbook, Volume 2
Enhancements In Stratix II and Stratix II GX Devices
PLL
When using the Stratix II and Stratix II GX top and bottom I/O banks
(I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL
with two outputs is needed to generate the system clock and the write
clock. The system clock generates the DQS write signals, commands, and
addresses. The write clock is either shifted by –90° or 90° from the system
clock and is used to generate the DQ signals during writes.
For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera also
recommends a second read PLL to help ease resynchronization.
When using the Stratix II and Stratix II GX side I/O banks 1, 2, 5, or 6 to
interface with DDR SDRAM devices, two PLLs may be needed per I/O
bank for best performance. Since the side I/O banks do not have
dedicated circuitry, one PLL captures data from the DDR SDRAM and
another PLL generates the write signals, commands, and addresses to the
DDR SDRAM device. Stratix II and Stratix II GX side I/O banks can
support DDR SDRAM up to 150 MHz.
Enhancements
In Stratix II and
Stratix II GX
Devices
Stratix II and Stratix II GX external memory interfaces support differs
from Stratix external memory interfaces support in the following ways:
■
■
■
■
■
■
■
■
Conclusion
A PLL output can now be used as the input reference clock to the
DLL.
The shifted DQS signal can now go into the logic array.
The DLL in Stratix II and Stratix II GX devices has more phase-shift
options than in Stratix devices. It also has the option to add phase
offset settings.
Stratix II and Stratix II GX devices have DQS logic blocks with each
DQS pin that helps with fine tuning the phase shift.
The DQS delay settings can be routed from the DLL into the logic
array. You can also bypass the DLL and send the DQS delay settings
from the logic array to the DQS logic block.
Stratix II and Stratix II GX devices support DQSn pins.
The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.
The DQS pins have been enhanced with the DQS postamble circuitry.
Stratix II and Stratix II GX devices support SDR SDRAM, DDR SDRAM,
DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories.
Stratix II and Stratix II GX devices feature high-speed interfaces that
transfer data between external memory devices at up to 300 MHz/600
Mbps. DQS phase-shift circuitry and DQS logic blocks within the
Stratix II and Stratix II GX devices allow you to fine-tune the phase shifts
for the input clocks or strobes to properly align clock edges as needed to
capture data.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
Document
Revision History
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &
Stratix GX Devices
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
DC & Switching Characteristics of Stratix III Devices chapter in
volume 2 of the Stratix III Device Handbook
Table 3–11 shows the revision history for this chapter.
Table 3–11. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
January 2008,
v4.5
Added the “Referenced Documents” section.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 8. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter. No content change.
—
May 2007,
v4.4
Updated the “Phase Offset Control” section.
—
Updated Figure 3–2.
—
Updated Table 3–1.
—
Minor text edits.
Added Table 3–4 and Table 3–6.
—
Updated Note (1) to Figure 3–10.
—
February 2007
v4.3
Added the “Document Revision History” section to
this chapter.
—
April 2006, v4.2
Chapter updated as part of the Stratix II Device
Handbook update.
—
No change
Formerly chapter 7. Chapter number change only
due to chapter addition to Section I in
February 2006; no content change.
—
December 2005
v4.1
Chapter updated as part of the Stratix II Device
Handbook update.
—
October 2005
v4.0
Added chapter to the Stratix II GX Device
Handbook.
—
Altera Corporation
January 2008
3–39
Stratix II Device Handbook, Volume 2
Document Revision History
3–40
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
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