datasheet for VL43B1G63A

datasheet for VL43B1G63A

Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

General Information

8GB 1Gx72 DDR3 SDRAM ECC REGISTERED SO-RDIMM 204-PIN

Description

The VL43B1G63A is a 1Gx72 DDR3 SDRAM high density RDIMM. This dual rank memory module consists of eighteen CMOS 512Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages, a 28-bit registered buffer/PLL clock in BGA package, and a 2K EEPROM with thermal sensor in an 8-pin MLF package. This module is a

204-pin registered dual in-line memory module and is intended for mounting into an edge connector socket.

Decoupling capacitors are mounted on the printed circuit board for each DDR3 SDRAM.

204-pin, registered small-outline dual in-line memory module (SO-RDIMM)

Supports ECC error detection and correction

Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, PC3-6400

VDD = VDDQ = 1.5V +/-0.075V

JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible)

VDDSPD = 3.0V to 3.6V

Eight internal component banks for concurrent operation

8-bit architecture

Bi-directional differential data-strobe

Nominal and dynamic on-die termination (ODT)

ZQ calibration support

Programmable CAS# latency:

11 (DDR3-1600), 9 (DDR3-1333), 7 (DDR3-1066), 6 (DDR3-800)

Programmable burst; length (8)

Average refresh period 7.8 us

Asynchronous

Fly-by

On board terminated command, address, and control bus

Serial presence detect (SPD) EEPROM with thermal sensor o

C to +125 o

C (Max +/-3 o

C accuracy)

Thermal sensor range: -40

 pinout

Gold edge contacts

Lead-free, RoHS compliant

PCB:

Operating temperature (T

OPER

): - Commercial (0 o

- Industrial (-40 o

C <= Tc <= 95

C <= Tc <= 95 o o

C)

C)

Notes: Double refresh rate is required when 85 o

C < T

OPER

<= 95 o

C.

T

OPER

is DRAM case temperature (Tc).

Order Information:

VL43B1G63A K0 M X X

OPERATING TEMPERATURE

None: Commercial

S1: Industrial screening

DRAM DIE (Option)

DRAM MANUFACTURER

M - MICRON

MODULE SPEED

K0: PC3-12800 @ CL11

K9: PC3-10600 @ CL9

F8: PC3-8500 @ CL7

E7: PC3-6400 @ CL6

VL: Lead-free/RoHS

Pin Name

A10/AP

A12/BC#

BA0~BA2

DQS0#~DQS8#

CB0~CB7

CK0, CK0#

ODT0, ODT1

CKE0, CKE1

CS0#, CS1#

RAS#

RESET#

VSS Ground

SDA

SCL

EVENT#

VREFCA

VREFDQ

VDDSPD

Function

Address Input/ Autoprecharge

Address Input/ Burst Chop

Bank Address Inputs

Data Strobes Complement

Data Check Bits I/O

Clock Input

On-die Termination Control

Clock Enables

Chip Selects

Row Address Strobes

Register and SDRAM Control

SPD Data Input/Output

SPD Clock Input

Temperature Event Output

Reference Voltage for CA

Reference Voltage for DQ

SPD Voltage Supply

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Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

Pin Configuration

204-PIN DDR3 SO-RDIMM FRONT 204-PIN DDR3 SO-RDIMM BACK

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin

DM5

5 DQ0 57 DQ25 109 VDD 161

7 DQ1 59 DM3 111 CK0 163

9 VSS 61 VSS 113 CK0# 165

11 DM0 63 DQ26 115 VDD 167

13 DQ2 65 DQ27 117 A10/AP 169

DQ42 4 DQ4 56 DQ29

6 DQ5 58 VSS 110 VDD 162 DQ43

VSS

DQ48 10 DQS0# 62 DQS3 114 166

DQ49 12 DQS0 64 VSS 116 VDD 168

VSS

Name

VSS

DQ46

DQ47

VSS

DQ52

DQ53

VSS

15 DQ3 67 VSS 119 BA0 171 DQS6# 16 DQ6 68 DQ31 CS2# 172

17 VSS 69 CB0 121 WE# 173

19 DQ8 71 CB1 123 VDD 175

21 DQ9 73 VSS 125 CAS# 177

DQS6 18 DQ7 70 VSS 122 RAS# 174

VSS

DQ50

20 VSS 72 CB4 124 VDD 176

22 DQ12 74 CB5 126 ODT0 178

DQ51 24 DQ13 76 DM8 128 ODT1 180

DM6

DQ54

DQ55

VSS

DQ60

27 DQS1 79 VSS 131 VDD 183

29 VSS 81 CB2 133 DQ32 185

31 DQ10 83 CB3 135 DQ33 187

33 DQ11 85 VDD 137 VSS 189

VSS 26 VSS 78 VSS 130 A13 182

DQ56 28 DM1 80 CB6 132 VDD 184

DQ57

VSS

37 DQ16 89 CKE1 141 DQS4 193

39 DQ17 91 BA2 143 VSS 195

41 VSS 93 VDD 145 DQ34 197

VSS

SA0

43 DQS2# 95 A12/BC# VDDSPD

30 82 CB7 134 DQ36 186

DM7 34 DQ14 86 VDD 138 VSS 190

DQ58 36 DQ15 88 A15 140 DM4 192

DQ59 38 VSS 90 A14 142 DQ38 194

40 DQ20 92 A9 144 DQ39 196

44 DM2 96 A11 148 DQ44 200

DQ61

VSS

DQS7#

DQS7

VSS

DQ62

DQ63

VSS

42 DQ21 94 VDD 146 VSS 198 EVENT#

SDA

45 DQS2 97 A8 149 VSS 201

47 VSS 99 A5 151 DQ40 203

49 DQ18 101 VDD 153 DQ41

51 DQ19 103 A3 155 VSS

SA1

VTT

46 VSS 98 A7 150 DQ45 202

48 DQ22 100 A6 152 VSS 204

SCL

VTT

*: These pins are not used in this module.

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PART NO.:

Function Block Diagram

Product Specifications

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

RCS1#

RCS0#

DQS0

DQS0#

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Vss

DQS1

DQS1#

DM1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D0

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D9

ZQ

Vss

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Vss

DQS2

DQS2#

DM2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D1

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D10

ZQ

Vss

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

Vss

DQS3

DQS3#

DM3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D2

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D11

ZQ

Vss

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Vss

DQS8

DQS8#

DM8

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D3

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D12

ZQ

Vss

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D8

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D17

ZQ

Vss

CS1#

CS0#

A0-A15

BA0-BA2

RAS#

CAS#

WE#

CKE0

ODT0

CKE1

ODT1

CK0

CK0#

22 ohm +/-5%

120 ohm

+/-1%

1:2

R

E

G

I

S

T

E

R

/

P

L

L

RCS1# -> CS1#: SDRAMs D9-D17

RCS0# -> CS0#: SDRAMs D0-D8

RA0-RA15 -> A0-A15: SDRAMs D0-D17

RBA0-RBA2 -> BA0-BA2: SDRAMs D0-D17

RRAS# -> RAS#: SDRAMs D0-D17

RCAS# -> CAS#: SDRAMs D0-D17

RWE# -> WE#: SDRAMs D0-D17

RCKE0 -> CKE0: SDRAMs D0-D8

RODT0 -> ODT0: SDRAMs D0-D8

RCKE1 -> CKE1: SDRAMs D9-D17

RODT1 -> ODT1: SDRAMs D9-D17

PCK0

PCK0#

PAR_IN

RESET#

22 ohm +/-5%

QERR#

RST #

Err_Out#

RESET#: SDRAMs D0-D17

DQS4

DQS4#

DM4

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

Vss

DQS7

DQS7#

DM7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

Vss

DQS6

DQS6#

DM6

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Vss

DQS5

DQS5#

DM5

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D4

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D13

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D5

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D14

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D6

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D15

ZQ

Vss

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

ZQ

CS# DQS DQS#

D7

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

D16

ZQ

Vss

Command, address, control, and clock line terminations

RA0-RA15, RBA0-RBA2

RRAS#, RCAS#, RWE#,

RCS0#, RCKE0, RODT0

RCS1#, RCKE1, RODT1

PCK0

PCK0#

Serial PD w ith Thermal sensor

SCL

EVENT#

EVENT#

A0 A1 A2

SA0 SA1

Vss

SDA

VDDSPD

VDD

VTT

VREFCA

VREFDQ

VSS

DDR3

SDRAM

DDR3

SDRAM

36 ohm +/-5%

VTT

30 ohm +/-5%

0.1uF

VDD

Serial PD

D0-D17

D0-D17

D0-D17

D0-D17

D0-D17

Notes:

1. Unless otherw ise noted, resistor values are 15 ohms +/-5%

2. ZQ resistors are 240 ohms +/-1%

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Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

Absolute Maximum Ratings

Symbol Parameter

VDD

VDDQ

Voltage on VDD pin relative to VSS

Voltage on VDDQ pin relative to VSS

VIN, VOUT Voltage on any pin relative to VSS

-0.4

-0.4

-0.4

-55

Address, RAS#,

CAS#, WE#, BA,

CS#, CKE, ODT

IL

Input leakage current; Any input 0V<VIN<VDD;

VREF input 0V<VIN<0.95V;

Other pins not under test = 0V

CK, CK# -5

1.975

1.975

1.975

150

150 uA

V

V

V

0

C

IOZ

IVREF

Output leakage current;

0V<VOUT<VDDQ; DQs and ODT are disabled

DQ, DQS, DQS#

VREF supply leakage current; VREF = Valid VREF level

-10

-18

10

18 uA uA

DC Operating Conditions

Symbol Parameter Min Max

1.425 1.5 1.575 V 1,2

VDDQ I/O Supply Voltage

VREFDQ (DC) I/O reference voltage DQ bus

VREFCA (DC) Input reference voltage CMD/ADD bus

1.425

0.49 x VDD

0.49 x VDD

1.5

0.5 x VDD

0.5 x VDD

1.575

0.51 x VDD

0.51 x VDD

V

V

V

1,2

3,4

3,4

VTT Termination Reference Voltage -0.483 x VDDQ 0.5 x VDDQ +0.517 x VDDQ V

Notes:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD

4. For reference: approximate VDD/2 +/-15mV.

5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins.

5

Operating Temperature Condition

Symbol Parameter

T

OPER

Operating

Commercial

Industrial

Rating Units Notes

0 to 95

-40 to +95

0

C 1,2

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51-2.

2. At -40 to +85

85 o o

C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when

C < TOPER <= 95 o

C.

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Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

Input DC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

VIHCA(DC)

VILCA(DC)

Input High (Logic 1) Voltage ( DDR3-1066/1333/1600/800)

Input Low (Logic 0) Voltage ( DDR3-1066/1333/1600/800)

DQ and DM

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

VIHDQ(DC)

VILDQ(DC)

Input High (Logic 1) Voltage (

DDR3-1066/1333/1600/800)

Input Low (Logic 0) Voltage ( DDR3-1066/1333/1600/800)

VREF + 0.100

VSS

VDD

VREF - 0.100

V

V

Input AC Logic Level

All voltages referenced to VSS

Symbol Parameter Min Unit

Command and Address

Input High (Logic 1) Voltage (

DDR3-1066/1333/1600/800)

Input Low (Logic 0) Voltage ( DDR3-1066/1333/1600/800)

VREF + 0.175

-

-

VREF - 0.175

V

V

VIHCA(AC)

VILCA(AC)

DQ and DM

VIHDQ(AC)

VILDQ(AC)

VIHDQ(AC)

VILDQ(AC)

Input High (Logic 1) Voltage (

DDR3-1066/800)

Input Low (Logic 0) Voltage

(DDR3-1066/800)

Input High (Logic 1) Voltage ( DDR3-1333/1600)

Input Low (Logic 0) Voltage (

DDR3-1333/1600)

VREF + 0.175

-

VREF + 0.150

-

-

VREF - 0.175

-

VREF - 0.150

V

V

V

V

Input/Output Capacitance

TA=25

0

C, f=100MHz

Input capacitance (A0~A15, BA0~BA2, RAS#, CAS#, WE#)

Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)

Input capacitance (CK0, CK0#)

Input/Output capacitance

(DQ, DQS, DQS#, DM, CB)

K0 (DDR3-1600)

K9 (DDR3-1333)

F8 (DDR3-1066)

E7 (DDR3-800)

CIN1

CIN2

CIN3

CIO

5.5

5.5

5.5

7

7

7

6.5

6.5

6.5

9.0

9.4

10 pF pF pF

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5 pF pF pF

Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

IDD Specification

(DDR3-1600) (DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

Operating one bank active-precharge current;

tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.

Precharge power-down current;

All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING.

Precharge quiet standby current;

All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is

HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Active power-down current;

All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING.

Active standby current;

All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD)); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING.

Operating burst read current;

All device banks open; Continuous burst reads; IOUT = 0mA;

BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS

MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W.

Operating burst write current;

All device banks open; Continuous burst writes; BL = 8; CL =

CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Burst refresh current;

tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval;

CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.

Self refresh current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING.

Operating bank interleave read current;

All bank interleaving reads; IOUT = 0mA; BL = 8; CL =

CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is

HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.

IDD0* 739

IDD1* 838

IDD2P-F** 676

IDD2P-S** 388

IDD2N** 604

IDD2Q** 586

IDD3P** 784

IDD3N** 784

IDD4R* 1657

IDD4W* 1369

IDD5** 2890

IDD6** 360

667

802

604

388

550

550

730

730

1504

1234

2764

360

Note: IDD specification is based on Micron E-die components.

*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.

**: Value calculated reflects all module ranks in this operating condition.

640

775

568

388

532

496

676

676

1351

1099

2692

360

640

775

568 mA

388 mA

532 mA

496 mA

676 mA

676 mA

1351

1099 mA

2692

360

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Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - 8 - 8 - ns

Average Clock Period

Clock Period

Average high pulse width tCK(avg) tCK(abs) tCH(avg)

1.25 <1.50 1.5 <1.875 1.875 <2.5 2.5 3.3 ns tCK(avg)min

+

tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tJIT(per)max tCK(avg)min

+ tJIT(per)min tCK(avg)max

+ tCK(avg)min

+

tJIT(per)max tJIT(per)min tCK(avg)max

+

tJIT(per)max

0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 ns tCK(avg)

0.47

-70

-60

0.53

70

60

0.47

-100

-90

0.53

100

90

Average low pulse width

Clock Period Jitter tCL(avg) tJIT(per)

Clock Period Jitter during DLL locking period tJIT(per, lck)

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles tJIT(cc) tJIT(cc, lck) tERR(2per)

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

Cumulative error across n = 13, 14 ... 49, 50 cycles

Absolute clock HIGH pulse width tERR(nper) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) tCH(abs) tCL(abs) Absolute clock Low pulse width

Data Timing

DQS,DQS# to DQ skew, per group, per access

DQ output hold time from DQS, DQS#

DQ low-impedance time from CK, CK#

DQ high-impedance time from CK, CK#

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac) levels

Data hold time to DQS, DQS# referenced to

Vih(ac)Vil(ac) levels

DQ and DM Input pulse width for each input tQH tLZ(DQ) tHZ(DQ) tDS(base)

(AC170) tDS(base)

(AC150) tDIPW

-103

-122

-136

-147

-155

-163

-169

-175

-180

-184

-188

0.43

0.43

0.38

-450

-

360

140

120

103

122

136

147

155

163

169

175

180

184

188

-

-

-

225

225

-

0.47

-80

-70

0.53

80

70

0.47

-90

-80

0.53

90

80

160

140

180

160

-118

-140

-155

-168

-177

-186

-193

118

140

155

168

177

186

193

-132

-157

-175

-188

-200

-209

-217

-200

-205

200

205

-224

-231

224

231

-210 210 -237 237

-215 215 -242 242 tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min

tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max

0.43 - 0.43 -

0.43 - 0.43 -

132

157

175

188

200

209

217

0.38

-500

-

400

-

250

250

-

0.38

-600

-

490

-

300

300

-

-147

-175

-194

-209

-222

-232

-241

-249

-257

-263

-269

0.43

0.43

0.38

-800

-

600

200

180

147

175

194

209

222

232

241

249

257

263

269

-

-

-

400

400

- ps ps ps ps ps ps ps ps tCK(avg) ps ps ps ps ps ps ps ps tCK(avg) tCK(avg) tCK(avg) ps ps ps

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7

Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

Data Strobe Timing

DQS, DQS# READ Preamble

DQS, DQS# differential READ Postamble

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

tRPRE tRPST

0.9

0.3

-

-

0.9

0.3

-

-

0.9

0.3

-

-

0.9

0.3

-

- tCK tCK

DQS, DQS# output high time

DQS, DQS# output low time tQSH tQSL

0.4

0.4

-

-

0.4

0.4

-

-

0.38

0.38

-

-

0.38

0.38

-

- tCK(avg) tCK(avg)

DQS, DQS# rising edge output access time from rising CK, CK#

DQS, DQS# low-impedance time

(Referenced from RL-1)

DQS, DQS# high-impedance time

(Referenced from RL+BL/ 2)

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# rising edge to CK, CK# rising edge

DQS,DQS# failing edge setup time to CK,

CK# rising edge

DQS,DQS# failing edge hold time to CK,

CK# rising edge

Command and Address Timing

tDQSCK -225 225 -255 255 -300 300 -400 400 ps tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Internal READ Command to PRECHARGE

Command delay

Delay from start of internal write transaction to internal read command tRTP tWTR max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

- max

(4tCK,7.5ns) max

(4tCK,7.5ns)

-

-

Mode Register Set command cycle time

Mode Register Set command update delay

CAS# to CAS# command delay

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

ACTIVE to internal read or write delay time

PRECHARGE command period

ACTIVE to ACTIVE or REF command period

ACTIVE to ACTIVE command period for

1KB page size

ACTIVE to ACTIVE command period for

2KB page size

Four activate window for 1KB page size

Four activate window for 2KB page size

Command and Address setup time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Command and Address setup time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Command and Address hold time from CK,

CK# referenced to Vih(ac) / Vil(ac) levels

Control & Address Input pulse width for each input tMRD tMOD tCCD tDAL(min) tMPRR tRAS tRCD tRP tRC tRRD tRRD tFAW tFAW tIS(base)

(AC175) tIS(base)

(AC150)

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

-

-

-

4 max

(12tCK,15ns)

4

WR + roundup (tRP / tCK(AVG))

-

-

-

4 max

(12tCK,15ns)

4

- nCK

-

- nCK nCK

1

35

13.75

13.75

48.75 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

40

-

9*tREFI 36 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns

-

-

-

-

-

-

-

1

13.5

13.5

49.5 max

(4tCK,6ns) max

(4tCK,7.5ns)

30

45

-

-

-

-

-

-

-

-

1

13.13

13.13

50.63 max

(4tCK,7.5ns) max

(4tCK,10ns)

37.5

50

-

-

-

-

-

-

-

-

1

15

15

52.5 max

(4tCK,10ns) max

(4tCK,10ns)

40

50

-

-

-

-

- nCK ns ns

-

-

- ns ns ns

45 - 65 - 125 - 200 - ps

45 + 125 - 65 + 125 - 125 + 150 - 200 + 150 - ps tIPW 560 - 620 - 780 - 900 - ps

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8

Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

Refresh Timing

4Gb REFRESH to REFRESH or REFRESH to ACTIVE command interval

Average periodic refresh interval

(0°C<= TCASE <= 85 °C)

Average periodic refresh interval

(85°C<= TCASE <= 95 °C)

Calibration Timing

tRFC 300 - 300 - 300 - 300 - ns

Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - tCK

Normal operation Full calibration time

Normal operation Short calibration time

Reset Timing

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE)

Valid Clock Requirement before Self

Refresh Exit (SRX)

Power Down Timing

Exit Power Down with DLL to any valid command; Exit Precharge Power Down with

DLL frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL

CKE minimum pulse width

Command pass disable delay

Power Down Entry to Exit Timing

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WRA command to Power Down entry BL8 (OTF, MRS), BL4OTF

Timing of WR command to Power Down entry (BL4MRS)

Timing of WRA command to Power Down entry (BL4MRS)

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry tZQoper tZQCS tXPR tXS tCKESR tCKSRE tCKSRX

256

64 max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tC,

10ns) max(5tC,

10ns) tXP tXPDLL tCKE tCPDED tPD max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,6ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

5.625ns)

1 tCKE(min)

-

-

-

-

9*tREFI max

(3tCK,7.5ns) max

(10tCK,24ns) max (3tCK,

7.5ns)

1 tCKE(min)

-

-

-

-

9*tREFI tRDPDEN tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN

RL + 4 +1

WL + 4

+ (tWR/ tCK(avg))

WL+4

+WR+1

WL + 2

+ (tWR/ tCK(avg))

WL+2

+WR+1

-

-

-

-

-

-

-

-

-

-

-

-

256

64 max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC+10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

RL + 4 +1

WL + 4

+ (tWR/ tCK(avg))

WL+4

+WR+1

WL + 2

+ (tWR/ tCK(avg))

WL+2

+WR+1

-

-

-

-

-

-

-

-

-

-

-

-

256

64 max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC

+10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

RL + 4 +1

WL + 4

+ (tWR/ tCK(avg))

WL+4

+WR+1

WL + 2

+ (tWR/ tCK(avg))

WL+2

+WR+1

-

-

-

-

-

-

-

-

-

-

-

-

256

64 max

(5tCK, tRFC

+ 10ns) max(5tC, tRFC

+10ns) tCKE(min) +

1tCK max(5tCK,

10ns) max(5tCK,

10ns)

RL + 4 +1

WL + 4

+ (tWR/ tCK(avg))

WL+4

+WR+1

WL + 2

+ (tWR/ tCK(avg))

WL+2

+WR+1

-

-

-

-

-

-

-

- tCK tCK nCK tCK

- nCK

- nCK

- nCK

- nCK

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9

Product Specifications

PART NO.:

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

AC TIMING PARAMETERS & SPECIFICATIONS

K0 K9

(DDR3-1333)

F8

(DDR3-1066)

E7

(DDR3-800)

Unit

MIN MAX MIN MAX MIN MAX MIN MAX

ODT Timing

ODT high time without write command or with write command and BC4

ODTH8 6 - 6 - 6 - 6 - nCK ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

ODT turn-on

RTT_NOM and RTT_WR turn-off time from

ODTL off reference

RTT dynamic change skew tAON tADC

-225

0.3

225

0.7

-250

0.3

250

0.7

-300

0.3

300

0.7

-400

0.3

400

0.7 ps tCK(avg)

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is programmed

DQS/DQS delay after tDQS margining mode is programmed

Setup time for tDQSS latch tWLS 165 - 195 - 245 - 325 - ps

Hold time for tDQSS latch

Write leveling output delay

Write leveling output error tWLH tWLO tWLOE

165

0

0

-

7.5

2

195

0

0

-

9

2

245

0

0

-

9

2

325

0

0

-

9

2 ps ns ns

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Package Dimensions

PART NO.:

Product Specifications

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

FRONT VIEW

67.60

3.40

MAX

4.0 +/- 0.10 (2X)

30.00 TYP

20.00 TYP

1.80 (2X)

TYP

6.00 TYP

2.15 TYP

PIN 1

1.0 +/- 0.10

0.5 R

0.60 TYP

63.60 TYP

BACK VIEW

0.45 TYP

PIN 203

1.0 +/- 0.10

2.55 TYP

PIN 204

39.00 TYP

3.00 TYP

21.00 TYP

24.80 TYP

4.00 TYP

PIN 2

Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.

2. The dimensional diagram is for reference only.

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Revision History:

PART NO.:

Product Specifications

VL43B1G63A-K0/K9/F8/E7M REV: 1.0

Date Rev.

Page Changes

02/28/2012 1.0 All Spec

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