datasheet for VL393T2863E

datasheet for VL393T2863E
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
General Information
1GB 128M x 72 DDR2 SDRAM VLP ECC REGISTERED DIMM 240-PIN
Description
The VL393T2863E is a 128Mx72 DDR2 SDRAM high density DIMM. This memory module is single rank, consists of
nine CMOS 128Mx8 bit with 8 banks DDR2 synchronous DRAMs in BGA packages, a 25-bit registered buffer in BGA
package, a zero delay PLL clock in BGA package, and a 2K EEPROM in an 8-pin MLF package. This module is a
240-pin dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling
capacitors are mounted on the printed circuit board for each DDR2 SDRAM.
Features
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Pin Description
240-pin, registered dual in-line memory module (RDIMM)
JEDEC pin out
Supports ECC error detection and correction
Fast data transfer rates: PC2-5300, PC2-4200, PC2-3200
VDD = VDDQ = 1.8V
JEDEC standard 1.8V (SSTL_18 compatible)
VDDSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS# ) option
Differential clock inputs (CK, CK#)
Four-bit pre-fetch architecture
DLL aligns DQ and DQS transition with CK
Nominal and dynamic on-die termination (ODT)
Programmable CAS# latency: 5 (DDR2-667), 4 (DDR2-533)
3 (DDR2-400)
Write latency = Read latency – 1 tCK
Eight internal component banks for concurrent operation
Programmable burst; length (4, 8)
Adjustable data-output drive strength
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 18.29mm (0.720”), double sided components
Order Information:
VL393T2863E - E6 S X
Pin Name
Function
A0~A13
Address Inputs
A10/AP
Address Input/ Autoprecharge
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
ODT0
On-die Termination Control
CK, CK#
Clock Input
CKE0
Clock Enables
CS0#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
RESET#
Reset Input
CB0~CB7
Check Bits
DM0~DM8
Data Masks
VDD
Voltage Supply 1.8V +/- 0.1V
VSS
Ground
SA0~SA1
SPD Address
SDA
SPD Data Input/Output
DRAM DIE (Option)
SCL
SPD Clock Input
DRAM MANUFACTURER
S - SAMSUNG
VDDSPD
SPD Voltage Supply 1.7V to 3.6V
VREF
SSTL_18 Reference Voltage
NC
No Connect
MODULE SPEED
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
VL: Lead-free/RoHS
DRAM component: MT47H128M8HQ-25/-3/-37E:H (Lead-free/ RoHS)
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1
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Pin Configuration
240-PIN DDR2 DIMM FRONT
240-PIN DDR2 DIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
31
DQ19
61
A4
91
VSS
121
VSS
151
VSS
181
VDDQ
211
DM5/
DQS14
2
VSS
32
VSS
62
VDDQ
92
DQS5#
122
DQ4
152
DQ28
182
A3
212
NC/
DQS14#
3
DQ0
33
DQ24
63
A2
93
DQS5
123
DQ5
153
DQ29
183
A1
213
VSS
4
DQ1
34
DQ25
64
VDD
94
VSS
124
VSS
154
VSS
184
VDD
214
DQ46
5
VSS
35
VSSD
65
VSS
95
DQ42
125
DM0/
DQS9
155
DM3/
DQS12
185
CK0
215
DQ47
6
DQS0#
36
DQS3#
66
VSS
96
DQ43
126
NC/
DQS9#
156
NC/
DQS12#
186
CK0#
216
VSS
7
DQS0
37
DQS3
67
VDD
97
VSS
127
VSS
157
VSS
187
VDD
217
DQ52
8
VSS
38
VSS
68
NC
98
DQ48
128
DQ6
158
DQ30
188
A0
218
DQ53
9
DQ2
39
DQ26
69
VDD
99
DQ49
129
DQ7
159
DQ31
189
VDD
219
VSS
10
DQ3
40
DQ27
70
A10/AP
100
VSS
130
VSS
160
VSS
190
BA1
220
NC
11
VSS
41
VSS
71
BA0
101
SA2
131
DQ12
161
CB4
191
VDDQ
221
NC
12
DQ8
42
CB0
72
VDDQ
102
NC
132
DQ13
162
CB5
192
RAS#
222
VSS
13
DQ9
43
CB1
73
WE#
103
VSS
133
VSS
163
VSS
193
CS0#
223
DM6/
DQS15
14
VSS
44
VSS
74
CAS#
104
DQS6#
134
DM1/
DQS10
164
DM8/
DQS17
194
VDDQ
224
NC/
DQS15#
15
DQS1#
45
DQS8#
75
VDDQ
105
DQS6
135
NC/
DQS10#
165
NC/
DQS17#
195
ODT0
225
VSS
16
DQS1
46
DQS8
76
CS1#*
106
VSS
136
VSS
166
VSS
196
A13
226
DQ54
17
VSS
47
VSS
77
ODT1*
107
DQ50
137
NC
167
CB6
197
VDD
227
DQ55
18
RESET#
48
CB2
78
VDDQ
108
DQ51
138
NC
168
CB7
198
VSS
228
VSS
19
NC
49
CB3
79
VSS
109
VSS
139
VSS
169
VSS
199
DQ36
229
DQ60
20
VSS
50
VSS
80
DQ32
110
DQ56
140
DQ14
170
VDDQ
200
DQ37
230
DQ61
21
DQ10
51
VDDQ
81
DQ33
111
DQ57
141
DQ15
171
CKE1*
201
VSS
231
VSS
22
DQ11
52
CKE0
82
VSS
112
VSS
142
VSS
172
VDD
202
DM4/
DQS13
232
DM7/
DQS16
23
VSS
53
VDD
83
DQS4#
113
DQS7#
143
DQ20
173
NC
203
NC/
DQS13#
233
NC/
DQS16#
24
DQ16
54
BA2
84
DQS4
114
DQS7
144
DQ21
174
NC
204
VSS
234
VSS
25
DQ17
55
NC
85
VSS
115
VSS
145
VSS
175
VDDQ
205
DQ38
235
DQ62
26
VSS
56
VDDQ
86
DQ34
116
DQ58
146
DM2/
DQS11
176
A12
206
DQ39
236
DQ63
177
A9
207
VSS
237
VSS
27
DQS2#
57
A11
87
DQ35
117
DQ59
147
NC/
DQS11#
28
DQS2
58
A7
88
VSS
118
VSS
148
VSS
178
VDD
208
DQ44
238
VDDSPD
29
VSS
59
VDD
89
DQ40
119
SDA
149
DQ22
179
A8
209
DQ45
239
SA0
30
DQ18
60
A5
90
DQ41
120
SCL
150
DQ23
180
A6
210
VSS
240
SA1
Note:
1. * These pins are not used in this module.
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2
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Function Block Diagram
RCS0#
DQS4#
DQS4
DM4
DQS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
CS# DQS DQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
D5
DQS6#
DQS6
DM6
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3#
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D4
DM5
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2#
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS# DQS DQS#
DQS5#
DQS5
DQS1#
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
D6
DQS7#
DQS7
DM7
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DM
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
D7
DQS8#
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0#
A0-A13
BA0-BA2
RAS#
CAS#
WE#
CKE0
ODT 0
RESET #
PCK9
PCK9#
DM/
RDQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
1:1
R
E
G
I
S
T
E
R
CS# DQS DQS#
VDDSPD
Serial PD
SCL
VDD/VDDQ
WP
D8
A0
A1
Serial PD
D0-D8
SDA
A2
VREF
D0-D8
VSS
D0-D8
SA0 SA1
VSS
RCS0# -> CS#: DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13: DDR2 SDRAMs D0-D8
RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D8
RRAS# -> RAS#: DDR2 SDRAMs D0-D8
RCAS# -> CAS#: DDR2 SDRAMs D0-D8
RWE# -> WE#: DDR2 SDRAMs D0-D8
RCKE0 -> CKE0: DDR2 SDRAMs D0-D8
RODT 0 -> ODT 0: DDR2 SDRAMs D0-D8
VSS
CK0
CK0#
RESET #
P
L
L
OE
PCK0 ~ PCK8
-> CK : DDR2 SDRAMs D0-D8
PCK0# ~ PCK8# -> CK# : DDR2 SDRAMs D0-D8
PCK9 -> CK : Register
PCK9# -> CK# : Register
RST #
Notes:
1. Unless otherwise noted, resistor value are 22 ohm +/-5%
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3
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Absolute Maximum Ratings
Symbol
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
VDD
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, BA,
RAS#, CAS#, WE#
-5
5
uA
CS#, CKE, ODT
-5
5
uA
CK, CK#
-250
250
uA
DM
-5
5
uA
-5
5
uA
-18
18
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
1.7
1.8
1.9
V
1
VDDQ
I/O supply voltage
1.7
1.8
1.9
V
4
VDDL
VDDL supply voltage
1.7
1.8
1.9
V
4
VREF
I/O reference voltage
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
VREF-0.04
VREF
VREF+0.04
V
3
VDD
VTT
Parameter
I/O termination voltage
Note:
1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This
measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and
must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
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4
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Operating Temperature Condition
Symbol
TOPER
Parameter
Rating
Operating temperature
Units
0
0 - 95
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At 0 – 85 C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
o
o
85 C < TOPER <= 95 C.
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
VIH(DC)
Input High (Logic 1) Voltage
VREF + 0.125
VDDQ + 0.300
V
VIL(DC)
Input Low (Logic 0) Voltage
-0.300
VREF - 0.125
V
Min
Max
Unit
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
VIH(AC)
Input High (Logic 1) Voltage DDR2-400/DDR2-533
VREF + 0.250
-
V
VIL(AC)
Input Low (Logic 0) Voltage DDR2-400/DDR2-533
-
VREF - 0.250
V
VIH(AC)
Input High (Logic 1) Voltage DDR2-667
VREF + 0.200
-
V
VIL(AC)
Input Low (Logic 0) Voltage DDR2-667
-
VREF - 0.200
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
Symbol
E6
(DDR2-667)
D5
(DDR2-553)
CC
(DDR2-400)
Min
Max
Min
Max
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#)
CIN1
6.5
7.5
6.5
7.5
6.5
7.5
pF
Input capacitance (CKE0, ODT0, CS0#)
CIN2
6.5
7.5
6.5
7.5
6.5
7.5
pF
Input capacitance (CK0, CK0#)
CIN3
6
7
6
7
6
7
pF
Input/Output capacitance (DQ, DQS, DQS#, DM, CB)
CIO
6.5
7.5
6.5
8
6.5
8
pF
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5
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
IDD Specification
Condition
Symbol
E6
(DDR2-667)
D5
(DDR2-553)
CC
(DDR2-400)
Unit
Operating one bank active-pre-charge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD0
1065
1020
675
mA
Operating one bank active-read-pre-charge;
IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD);
tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same
as IDD4W.
IDD1
1155
1110
1065
mA
Pre-charge power-down current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
IDD2P
435
435
435
mA
Pre-charge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
IDD2Q
660
660
615
mA
Pre-charge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are SWITCHING.
IDD2N
705
705
660
mA
Active power-down current;
All banks open; tCK= tCK(IDD); CKE is LOW;
Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING.
660
615
615
mA
IDD3P
462
462
462
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3N
840
840
795
mA
Operating burst write current;
All banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD4W
1470
1380
1245
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL =
CL(IDD);
AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as IDD4W.
IDD4R
1560
1470
1335
mA
IDD5
1650
1650
1650
mA
135
135
135
IDD7
2460
2460
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS#
is HIGH between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING.
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD);
AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD =
1*tCK(IDD) ;
CKE is HIGH; CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
mA
2325
mA
Notes: IDD specification is based on Samsung D-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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6
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
E6
(DDR2-667)
D5
(DDR2-553)
CC
(DDR2-400)
Max
Min
Max
Min
Max
Min
Unit
Clock Timing
CL5
tCK(5)
3,000
8,000
-
-
-
-
ps
CL4
tCK(4)
3,750
8,000
3,750
8,000
-
-
ps
CL3
tCK(3)
5000
8000
5000
8000
5000
8000
ps
CK high-level width
tCH(avg)
0.48
0.52
0.48
0.52
0.45
0.55
tCK
CK low-level width
tCL(avg)
0.48
0.52
0.48
0.52
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH, tCL)
-
MIN
(tCH, tCL)
-
MIN
(tCH, tCL)
-
ps
Clock jitter
tJIT
-125
125
-125
125
-100
100
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
500
-600
600
ps
Data-out high impedance window from CK/CK#
tHZ
-
tAC(MAX)
-
tAC(MAX)
-
tAC(MAX)
ps
Data-out low impedance window from CK/CK#
tLZ
tAC(MiN)
tAC(MAX)
tAC(MiN)
tAC(MAX)
tAC(MiN)
tAC(MAX)
ps
DQ and DM input setup time relative to DQS
tDS
100
-
100
-
150
-
ps
DQ and DM input hold time relative to DQS
tDH
175
-
225
-
275
-
ps
DQ and DM input pulse width ( for each input)
tDIPW
0.35
-
0.35
-
0.35
-
tCK
Data hold skew factor
tQHS
-
340
-
400
-
450
ps
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP - tQHS
-
tHP - tQHS
-
tHP - tQHS
-
ps
Data valid output window (DVW)
tDVW
tQH-tDQSQ
-
tQH-tDQSQ
-
tQH-tDQSQ
-
ns
DQS input high pulse width
tDQSH
0.35
-
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
0.35
-
tCK
DQS output access time from CK/CK#
tDQSCK
-400
+400
-450
+450
-500
+500
ps
DQS failing edge to CK rising-setup time
tDSS
0.2
-
0.2
-
0.2
-
tCK
DQS failing edge from CK rising-hold time
tDSH
0.2
-
0.2
-
0.2
-
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
-
240
-
300
-
350
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read preamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read preamble setup time
tWPRES
0
-
0
-
0
-
ps
DQS read preamble
tWPRE
0.35
-
0.35
-
0.35
-
tCK
DQS read preamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock Cycle Time
Data Timing
Data Strobe Timing
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7
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
E6
(DDR2-667)
D5
(DDR2-553)
CC
(DDR2-400)
Unit
Min
Max
Min
Max
Min
Max
tIPW
0.6
-
0.6
-
0.6
-
tCK
Address and control input setup time
tIS
200
-
250
-
350
-
ps
Address and control input hold time
tIH
275
-
375
-
475
-
ps
CAS# to CAS# command delay
tCCD
2
-
2
-
2
-
ps
ACTIVE to ACTIVE (same bank) command
tRC
55
-
55
-
55
-
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
-
7.5
-
7.5
-
ns
Command and Address Timing
Address and control input pulse width for each input
ACTIVE to READ or WRITE delay
tRCD
15
-
15
-
15
-
ns
Four Bank Activate period
tFAW
37.5
-
37.5
-
37.5
-
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
40
70,000
45
70,000
ns
Internal READ to precharge Command delay
tRTP
7.5
-
7.5
-
7.5
-
ns
Write recovery time
tWR
15
-
15
-
15
-
ns
Auto precharge write recovery + precharge time
tDAL
t WR+t RP
-
t WR+t RP
-
t WR+tnRP
-
ns
Internal WRITE to READ Command delay
tWTR
7.5
-
7.5
-
10
-
ns
tRP
15
-
15
-
15
-
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
-
tRP+tCK
-
tRP+tCK
-
ns
LOAD MODE command cycle time
tMRD
2
-
2
-
2
-
tCK
tDELAY
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
Refresh to Active or Refresh to Refresh command
interval
tRFC
127.5
-
127.5
-
127.5
-
ns
Average periodic Refresh interval
tREFI
-
7.8
-
7.8
-
7.8
us
Exit Self Refresh to non-READ command
tXSNR
t RFC(MIN)
+10
-
t RFC(MIN)
+10
-
t RFC(MIN)
+10
-
ns
Exit Self Refresh to READ
tXSRD
200
-
200
-
200
-
tCK
Exit Self Refresh timing reference
tISXR
tIS
-
tIS
-
tIS
-
ps
PRECHARGE command period
CKE low to CK, CK# uncertainty
Self Refresh
ODT
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
t AC(MIN)
t AC(MAX)+
700
t AC(MIN)
t AC(MAX)+
1,000
t AC(MIN)
t AC(MAX)+
1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAOF
t AC(MIN)
t AC(MAX)+
600
t AC(MIN)
t AC(MAX)+
600
t AC(MIN)
ODT turn-on(power-down mode)
tAONPD
t AC(MIN)+
2,000
2 x tCK +
t AC(MAX)+
1,000
t AC(MIN)+
2,000
2 x tCK +
t AC(MAX)+
1,000
t AC(MIN)+
2000
ODT turn-off (power-down mode)
tAOFPD
t AC(MIN)+
2,000
2.5 xtCK+
t AC(MAX)+
1,000
t AC(MIN)+
2,000
2.5 xtCK+
t AC(MAX)+
1,000
t AC(MIN)+
2000
ODT to power-down entry latency
tANPD
3
-
3
-
3
-
tCK
ODT power-down exit latency
tAXPD
8
-
8
-
8
-
tCK
Exit active power-down to READ command, MR[bit12=0]
tXARD
2
-
2
-
2
-
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARD
7-AL
-
6-AL
-
6-AL
-
tCK
Exit precharge power-down to any non-READ command
tXP
2
-
2
-
2
-
tCK
CKE minimum high/low time
tCKE
3
-
3
-
3
-
tCK
ODT turn-off
t AC(MAX)+
600
2tCK +
t
AC(MAX)+1
000
2.5xtCK +
tAC(MAX)+
1000
ps
ps
ps
Power Down
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8
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Package Dimensions
FRONT VIEW
133.35
3.00 (4X)
TYP
3.85
MAX
2.00 (4X)
TYP
18.29
10.00
1.27+/_0.10
PIN 1
5.175 (2X)
1.50 +/- 0.10
0.80 TYP
1.00 TYP
PIN 120
123.00 TYP
BACK VIEW
3.00 TYP (4X)
3.80TYP
PIN 240
55.0 TYP
63.0TYP
PIN 121
5.00 TYP
Note: 1. All dimension are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
9
Product Specifications
PART NO.:
VL393T2863E-E6S-D5S-CCS
REV: 1.2
Revision History:VN-281009
Date
Rev.
Page
Changes
09/21/2007
1.0
All
Spec release
05/23/2008
1.1
9
Update package dimension
11/30/2010
1.2
All
Update datasheet
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
10
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