datasheet for PL613-01 by PhaseLink Corporation
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
DESCRIPTION
FEATURES
Designed for PCB space savings with 3 low-power
Programmable PLLs and up to 8 clock outputs.
Low-Power Consumption
o 10µ A typical when PDB is activated
Output Frequency:
o <110MHz @ 1.8V operation
o <166MHz @ 2.5V operation
o <200MHz @ 3.3V operation
Input Frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
Programmable I/O pins can be configured as Output
Enable (OE), Configuration Switching (CSEL),
Frequency Switching (FSELX), Power Down (PDB)
inputs, or Clock outputs.
Disabled outputs programmable as HiZ or Active Low
Four distinct configurations selectable with CSEL[0:1]
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Temperature range: 0 C to 70 C, -40 C to +85 C
Available in GREEN/RoHS compliant 3x3 QFN or
(T)SSOP packages.
The PL613-01 is an advanced triple PLL design
based on PhaseLink’s PicoPLL TM , world’s smallest
programmable clock, technology. This advanced
technology allows the 8 output PL613-01 to fit in to a
small 3mmx3mm QFN package or (T)SSOP for high
performance, low-power, low-cost applications.
Besides its small form factor and 8 outputs that can
reduce overall system costs, the PL613-01 offers
superior phase noise, jitter and power consumption
performance.
The power down feature of PL613-01, when
activated, allows the IC to consume less than 10µ A of
power, while its CSEL[0:1] allows switching between
up to 4 pre-programmed configurations. The FSELX,
on the other hand, allows frequency switching of two
outputs (CLK1 & CLK2) on a single clock pin (CLK2).
BLOCK DIAGRAM
Programming
Interface
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 1
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
XOUT
VDD
GND
CLK5, OE6^, CSEL0
12
13
XIN, FIN
PIN CONFIGURATION
11
10
9
8
CLK4
XIN, FIN
1
16
XOUT
GND
2
15
VDD
CLK6, OEM^, PDB^
14
7
CLK3, OE4^
CLK5, OE6^, CSEL0
3
14
CLK4
VDD
15
6
GND
CLK6, OEM^, PDB^
4
13
CLK3, OE4^
16
1
5
CLK2
VDD
5
12
GND
CLK7, OE0^, CSEL1
6
11
CLK2
CLK0, FSELX
7
10
CLK1, OE2^
VDD
8
9
GND
GND
3
4
CLK1, OE2^
VDD
2
CLK0, FSELX^
CLK7, OE0^, CSEL1
^ Denotes internal pull up
QFN Package
(T)SSOP Package
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
Type
Description
QFN-16L
(T)SSOP-16L
1
7
B*
- Programmable Clock (CLK0) output or
- CLK2 Frequency Switching (FSELX) input.
GND
3, 6, 12
2, 9, 12
P
GND connection.
VDD
2, 9, 15
5, 8, 15
P
VDD connection.
CLK1, OE2
4
10
B*
- Programmable Clock (CLK1) output or
- Output Enable (OE) input for CLK2.
CLK2
5
11
O
Programmable Clock (CLK2) output.
CLK3, OE4
7
13
B*
- Programmable Clock (CLK3) output or
- Output Enable (OE) input for CLK4.
CLK4
8
14
O
Programmable Clock (CLK4) output.
XOUT
10
16
O
Crystal output pin. Do Not Connect when using FIN.
XIN, FIN
11
1
I
Crystal or Reference Clock input.
B*
- Programmable Clock (CLK5) output or
- Output Enable (OE) input for CLK6 or
- Configuration Switching input.
B*
- Programmable Clock (CLK6) output, or
- Output Enable Master (OEM) for all clock outputs, or
- Power Down mode (PDB) input.
B*
- Programmable Clock (CLK7) output or
- Output Enable (OE) input for CLK0 or
- Configuration Switching input.
CLK0, FSELX
CLK5, OE6,
CSEL0
CLK6, OEM,
PDB
CLK7, OE0,
CSEL1
13
14
16
3
4
6
* Note: All bidirectional buffers (I/Os) incorporate an internal 60KΩ pull up resistor when used as an input except when
PDB mode is used. In configurations that use PDB, the PDB pin will have a 10M Ω pull up resistor.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 2
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
KEY PROGRAMMING PARAMETERS
CLK[ 0:7 ]
Output Frequency
CLK[0,3,6]
F VCOx / (P*(1,2,4,8)), F REF or
F REF / (P*(1,2,4,8))
Output Drive Strength
Programmable Input/Output
Each output has three
optional drive strengths to
choose from. They are:
Most pins are multi-function I/Os. In addition
to CLK, they can be configured to perform
as:
CLK[1,4,7]
F VCOx / P
CLK[2,5]
F VCOx / P, F REF or F REF / P
Low: 4mA
Std: 8mA (default)
High:16mA
OE [0,2,4,6] – (Output Enable for
individual I/Os)
OEM – (Master OE controlling all outputs)
CSEL[0:1] – (Device Configuration
Switching)
FSELX – (CLK2 Frequency Switching)
PDB – (Power Down)
CLK[0:8] – (Output)
HiZ or Active Low disabled state
Where F VCOx = F REF * M / R
M = 11 bit
R = 8 bit
P = 5 bit (Odd/Even Divider)
FUNCTIONAL DESCRIPTION
The PL613-01 is a highly featured, very flexible, advanced triple PLL design for high performance, low-power
applications. The device accepts a low-cost fundamental crystal input of 10MHz to 40MHz or a reference clock
input of 10MHz to 200MHz and is capable of producing 8 distinct output frequencies up to 200MHz. All 3-PLLs are
fully programmable, with a total of five, 5-bit Post VCO, Odd/Even ‘P-counter’ dividers with additional 1, 2, 4 or 8
‘Post P-counter’ dividers to allow generating most demanding frequencies, easily. The outputs can be
programmed to deliver the generated frequencies from the PLLs, or the reference input. Each bidirectional feature
pin (I/O) on the PL613-01 incorporates a 60KΩ pull up resistor and can be configured to perform various functions.
Usage of various design features of these products is mentioned in the following paragraphs.
PLL Programming
The three PLLs in PL613-01 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The three PLL
outputs are transferred to five 5-bit post VCO,
Odd/Even dividers (P-Counter), as shown in the above
diagrams. In addition, there are three optional (÷ 1,
÷ 2, ÷ 4 or ÷ 8) post P-Counter dividers, that can further
divide the VCO frequency. In general, the PLL
output frequency is determined by the following
formula:
F OUT = (F REF *M)/(R*P)
For output calculations, please note that ‘P’ includes
the ‘P’ counter bits plus the additional optional (÷ 1,
÷ 2, ÷ 4 or ÷ 8) dividers, if used.
CLKx (Clock Outputs)
There are a maximum of 8 outputs available on the
PL613-01. Clock output frequencies can be
configured as follows:
CLK[0,3,6]
F VCOx / (P*(1, 2, 4, 8))
F REF (Crystal or Reference Clock frequency)
F REF / (P*(1,2,4,8))
CLK[1, 7]
F VCOx / P
CLK[2, 4, 5]
F VCOx / P, F REF or F REF / P
Each output can be programmed with a 4mA, 8mA, or
16mA drive strength. The maximum output frequency
is 200MHz @ 3.3V, 166MHz @ 2.5V or 110MHz @
1.8V.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 3
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
OE (Output Enable)
Four pins can be configured as OE inputs for
controlling individual clock outputs, as shown in the
table below:
Controls Output
OEx
On CLK#
OE0
CLK0
OE2
CLK2
OE4
CLK4
OE6
CLK6
0
0 (Default)
On
On
Hi Z
1
On
On
Active ‘0’
Off
Hi Z
1
Off
Off
Active ‘0’
Normal Operation (Default)
On-The-Fly Configuration Switching (CSEL)
The PL613-01 can be programmed to allow switching
between 4 different configurations, allowing for
changes in the output frequencies. Many applications
(i.e. video/audio) can use the same design footprint,
but allow for configuration switching, adhering to
various standards. CSEL0 and CSEL1 are used in
the switching selection. These pins incorporate a
60kΩ pull up resistor for normal operating condition.
The logic for configuration switching of the
programmed parts is shown below:
Normal Operation (Default)
OEM (Master Output Enable)
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of the
PL613-01. In addition the state of the disabled
outputs can be programmed to float (Hi Z) or to
operate in the ‘Active low’ mode. The OEM Function
operates on the following logic:
OEM
OE Type
Osc PLL
Output
Pin
(Programmable)
0
Off
1
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The programming control for individual OEs is
shown below:
OE
OE Type
Osc PLL
Output
Pin
(Programmable)
1
0 (Default)
Note: Typical enable time from power down is <2ms.
Note: Typical enable time is < 500 ns plus one clock period.
0
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode. The logic for PDB is shown below:
PDB PDB Type
Osc PLL
Output
Pin
Program
0 (Default)
On
On
Hi Z
1
On
On
Active ‘0’
1
Normal Operation (Default)
Note: Typical enable time is < 500 ns plus one clock period.
Power-Down Control (PDB)
When activated, PDB ‘Disables all the PLLs, the
oscillator circuitry, counters, and all other active
circuitry. PDB activation disables all outputs and the
IC consumes <10µ A of power. The PDB input
incorporates a 10MΩ pull up resistor for normal
operating condition.
CSEL1
CSEL0
0
0
1
1
0
1
0
1
Programmed
Configuration
0
1
2
3 (Default)
Note: Typical enable time is <500µ s .
On-The-Fly Output Frequency Switching
Between Two Output Frequencies (FSELX)
The PL613-01 is equipped with the FSELX feature to
allow frequency switching of two frequencies on one
of the output pins. Frequencies assigned to CLK1
and CLK2 can be switched, when FSELX is
activated, on CLK2 output. The logic for FSELX is
shown below:
FSELX
CLK2 Output
0
Frequency 2
1 (default)
Frequency 1
Note: Typical enable time is <10ns plus one clock period.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 4
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the V DD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
- Multiple V DD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V DD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1 F for
designs using frequencies < 50MHz and 0.01 F for
designs using frequencies > 50MHz.
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
XOUT
XIN
1
8
Cpt
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 5
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
260
C
Supply Voltage Range
Soldering Temperature (Green package)
10
Data Retention @ 85 C
Storage Temperature
TS
Ambient Operating Temperature*
Year
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
Crystal Input Frequency (XIN) Fundamental crystal
TYP.
10
@ V DD = 3.3V, ± 10%
Input (FIN) Frequency
10
@ V DD = 2.5V, ± 10%
Output Enable Time
MHz
MHz
110
Internally AC coupled
0.8
V DD
Vpp
200
1
@ V DD = 2.5V, ± 10% (High Drive)
166
@ V DD = 1.8V, ± 10% (High Drive)
Settling Time
40
166
@ V DD = 3.3V, ± 10% (High Drive)
Output Frequency
UNITS
200
@ V DD = 1.8V, ± 10%
Input (FIN) Signal Amplitude
MAX.
MHz
110
At power-up (V DD > 90% of operating V DD )
OE Function; Ta=25º C, 15pF Load. Add one
clock period to this measurement for a usable
clock output.
PDB Function; Ta=25º C, 15pF Load
ms
500
ns
2
ms
2
ppm
V DD Sensitivity
Frequency vs. V DD, ± 10%
Output Rise Time
15pF Load, 10/90% V DD , High Drive, 3.3V
1.2
1.7
ns
Output Fall Time
15pF Load, 90/10% V DD , High Drive, 3.3V
PLL driven output, @ V DD /2, 15pF load,
High Drive, over entire frequency range
Configuration dependant, with capacitive
decoupling between V DD and GND.
1.2
1.7
ns
50
55
%
Duty Cycle
Period Jitter*
(10,000 samples)
-2
2
45
300
ps
* Note: Jitter performance depends on the programming parameters.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 6
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
DC SPECIFICATIONS
PARAMETERS
SYMBOL
Supply Current, V DD = 3.3V
I DD
Supply Current, V DD = 2.5V
I DD
Supply Current, V DD = 1.8V
I DD
Supply Current
I DD
Operating Voltage
V DD
CONDITIONS
MIN.
All 8 outputs @ 20MHz
No Load, V DD = 3.3V
All 8 outputs @ 20MHz
No Load, V DD = 2.5V
All 8 outputs @ 20MHz
No Load, V DD = 1.8V
When PDB=0
TYP.
MAX.
UNITS
17
23
mA
13.5
18
mA
9.5
13
mA
10
µA
Configured for 3.3V Operation
2.97
3.3
3.63
Configured for 2.5V Operation
2.25
2.5
2.75
Configured for 1.8V Operation
1.62
1.8
1.98
Output Low Voltage
V OL
I OL = +4mA Std Drive, 3.3V
Output High Voltage
V OH
I OH = -4mA Std Drive, 3.3V
Output Current, Low Drive
I OSD
Output Current, Std Drive
Output Current, High Drive
V
0.4
V
2.4
V
V OL = 0.4V, V OH = 2.4V, 3.3V
4
mA
I OSD
V OL = 0.4V, V OH = 2.4V, 3.3V
8
mA
I OHD
V OL = 0.4V, V OH = 2.4V, 3.3V
16
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
SYMBOL
MIN
F XIN
10
C L (xtal)
Operating Drive Level
Metal Can Crystal
Small SMD Crystal
TYP
ESR Max
Shunt Capacitance
ESR Max
UNITS
40
MHz
15
0.1
Shunt Capacitance
MAX
pF
2
mW
C0
5.5
pF
ESR
40
Ω
C0
2.5
pF
ESR
60
Ω
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 7
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
QFN-16L
A
e
L
D
D1
E1
Pin1 Dot
A3
b
SEATING PLANE
A1
A
A1
A3
b
D
E
D1
E1
L
e
Dimension in MM
Min.
Max.
0.7
0.8
0.05
0.05
0.20
0.18
0.30
3.00 BSC
3.00 BSC
-1.70
-1.70
0.30
0.50
0.50 BSC
E
Symbol
TSSOP-16L
Symbol
A
A1
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.20
6.60
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
e
L
B
SSOP-16L
Symbol
A
A1
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.05
0.15
0.20
0.30
0.18
0.25
4.80
5.00
3.80
3.98
5.80
6.20
0.40
1.27
0.635 BSC
E
H
D
A
A1
C
e
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
B
www.phaselink.com
L
Rev 02/08/11
Page 8
PL613-01
1.8V to 3.3V, PicoPLL, 3-PLL, 200MHz, 8 Output Clock IC
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA 95134 USA
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL613-01-XXX X X X
PART NUMBER
3 DIGIT ID Code *
(will be assigned at
programming time)
PACKAGE TYPE
O=TSSOP-16L
Q=QFN-16L
X=SSOP-16L
NONE= TUBE
R=TAPE and REEL
TEMPERATURE
C=COMMERCIAL (0 C to 70 C)
I= INDUSTRIAL (-40 C to +85 C)
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part Number/Order Number
PL613-01-XXXOC
PL613-01-XXXOC-R
PL613-01-XXXQC-R
PL613-01-XXXXC
PL613-01-XXXXC-R
†
Marking†
P613-01
XXX(I)
LLLLL
P613-01
XXX(I)
LLLLL
P61301
XXX(I)
LLL
P613-01
XXX(I)
LLLLL
P613-01
XXX(I)
LLLLL
Package Option
16-Pin TSSOP (Tube)
16-Pin TSSOP (Tape and Reel)
16-Pin QFN (Tape and Reel)
16-Pin SSOP (Tube)
16-Pin SSOP (Tape and Reel)
Marking Notes :
1) The “I” after the three digit programming code will be marked for Industrial Temperature grade products only. Commercial
grade products will not have a character in this position.
2) LLL represents the production lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warra nty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critica l components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 02/08/11
Page 9
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