D-Link | DSH-8 - 10/100Mbps Dual Speed SOHO Hub | User manual | ADM7001/X
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Data Sheet, Rev. 1.07, Nov. 2005 ADM7001/X Single Ethernet 10/100M PHY Communications N e v e r s t o p t h i n k i n g . Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2005. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Single Ethernet 10/100M PHY Revision History: 2005-11-25, Rev. 1.07 Previous Version: Page/Date Subjects (major changes since last revision) 2003-03-05 Rev. 1.0: First release of ADM7001 2003-04-08 Rev. 1.01: Register Modifications and Pin updates 2003-07-24 Rev. 1.02: The following sections were updated: 1.2, 1.3, 2.1, 2.2.1, 2.2.5, 2.2.7, 2.2.8, 2.2.8, 4.1, 4.2.3-4, 4.2.11-12, 4.3.4, 4.3.9, 4.3.11, 4.3.12, & 4.3.16 2003-07-30 Rev. 1.03: Updated section 6.2 2003-09-15 Rev. 1.04: Updated Section 2.2.5, 2.2.8, & 4.2.11 2004-02-19 Rev. 1.05: Updated table 5.3 2004-04-16 Rev. 1.06: Removed TQFP packaging 2005-09-12 Rev. 1.07 when changed to the new Infineon format 2005-11-25 Minor change. Included Green package information Trademarks ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®, 10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems Incorporated. Template: template_A4_3.0.fm / 3 / 2005-01-17 ADM7001/X Data sheet Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 1.1 1.1.1 1.2 1.3 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twisted Pair Interface, 5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Ground/Power, 7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground and Power, 5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input, 2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII/RMII/GPSI Interface, 16 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals, 6 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Interface, 4 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 13 14 15 16 16 22 22 24 25 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.1.10 3.1.11 3.1.12 3.1.13 3.1.14 3.1.15 3.1.16 3.1.17 3.1.18 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100M PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-X Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-TX Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-TX Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-FX Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-FX Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Base-T Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manchester Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Driver and Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Link Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Negotiation and Speed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reduced Media Independent Interface (RMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path for 100M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path for 10M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path for 100M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path for 10M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 30 30 31 31 31 31 31 31 32 32 33 33 33 33 33 34 34 34 35 36 36 38 38 Data Sheet 4 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Table of Contents 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.3 3.4 3.4.1 3.4.2 3.5 3.6 Receive Path for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Path for GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Path for GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 5.1 5.1.1 5.1.2 5.1.2.1 5.2 5.2.1 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.5 5.5.1 5.5.2 5.6 5.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics for 2.5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XI/OSCI (Crystal/Oscillator) Timing (In MII Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFCLK Input Timing (XI in RMII Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFCLK Output Timing (CLKO50 in RMII Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXCLK Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TXCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Management Interface (MDC/MDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data Sheet 5 39 41 41 42 42 43 44 44 44 45 46 74 74 74 74 74 75 75 76 76 77 77 78 79 79 81 82 82 83 83 84 85 86 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Data Sheet ADM7001/X Block Diagram 10 Pin Diagram 11 100Base-X Block Diagram and Data Path 27 10Base-T Block Diagram and Data Path 32 RMII Signal Diagram 35 RMII Reception Without Error 35 RMII Reception with False Carrier (100M Only) 36 RMII Reception with Symbol Error 36 10M RMII Receive Diagram 36 100M RMII Transmit Diagram 37 10M RMII Transmit Diagram 38 MII Signal Diagram 39 MII Receive Without Error 39 MII Receive With False Carrier 40 MII Receive With Symbol Error(100M Only) 40 MII Transmission 41 MII Transmit with Collision (Half Duplex Only) 41 GPSI Signal Diagram 42 GPSI Receive Diagram 42 GPSI Transmit Diagram 43 SMII Read Operation 44 SMII Write Operation 45 Medium Detect Power Management Flow Chart 46 Power and Ground Filtering 47 Crystal/Oscillator Timing 75 REFCLK Input Timing 76 REFCLK Output Timing 77 RMII Transmit Timing 78 RMII Receive Timing 78 RXCLK Output Timing 79 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 83 GPSI Receive Timing 84 GPSI Transmit Timing 84 Serial Management Interface (MDC/MDIO) Timing 85 Power On Configuration Timing 86 ADM7001/X,Low Profile Quad Flat Package (LQFP) 87 6 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Data Sheet Abbreviations for Pin Type 12 Abbreviations for Buffer Type 12 Twisted Pair Interface, 5 Pins 13 Digital Ground/Power, 7 Pins 14 Ground and Power, 5 Pins 15 Clock Input, 2 Pins 16 MII/RMII/GPSI Interface, 16 pins 16 Reset Pin 22 Clock Signals, 6 pins 22 LED Interface, 4 Pins 24 Regulator Control 25 Look-up Table for Translating 5B Symbols into 4B Nibbles 28 Channel Configuration 38 Speed LED Display 43 Duplex LED Display 43 Activity/Link LED Display 43 Cable Distance LED Display 44 Registers Address Space 48 Registers Overview 48 Registers Access Types 48 Registers Clock Domains 49 Reserved Registers 59 Absolute Maximum Rating 74 Recommended Operating Conditions 74 DC Characteristics for 2.5 V Operation 74 Crystal/Oscillator Timing 75 REFCLK Input Timing 76 REFCLK Output Timing 77 RMII Transmit Timing 78 RMII Receive Timing 79 REFCLK Input Timing 80 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 83 GPSI Receive Timing 84 GPSI Transmit Timing 85 Serial Management Interface (MDC/MDIO) Timing 85 Power On Configuration Timing 86 Dimensions for 100 Pin LQFP Package 88 7 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Product Overview 1 Product Overview Features and Block Diagram. 1.1 Overview The ADM7001/X is a single chip one port 10/100M PHY, which is designed for today’s low cost and low power dual speed application. The ADM7001X is the environmentally friendly “green” package version. It supports auto sensing 10/100 Mbps ports with on-chip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation, and also supports Manchester Code Converter with on chip clock recovery circuitry for 10 Mbps functionality. Meanwhile, it provides Medium Independent Interface (MII), Reduced Medium Independent Interface (RMII) and General Purpose Serial Interface (GPSI), three different interfaces in different applications. For today's IA (Information Application), ADM7001/X supports "Auto Cross Over Detection" function to eliminate the technical barrier between networking and end user. With the aid of this auto cross over detection function, Plug-n-Play feature can be easily applied to IA relative products. The major design target for ADM7001/X is to reduce the power consumption and system radiation for the whole system. With the aid of this low power consumption and low radiation chip, the fan and on-system power supply can be removed to save the total manufacture cost and make SOHO application achievable. 1.1.1 Package Information Product Name Product Type Package Ordering Number ADM7001/X ADM7001/X LQFP-48-1 Q67801H 2A1) 1) contact Infineon for the updated ordering information 1.2 Features Main features: • • • • • • • • • • • • • • • • • • IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver. Single chip, integrated physical layer and transceivers for 10Base-T and 100BASE-TX function. Medium Independent Interface (MII), Reduced MII (RMII) and General Purpose Serial Interface (GPSI) for high port count switch. Built-in 10 Mbit transmit filter. 10 Mbit PLL, exceeding tolerances for both preamble and data jitter. 100 Mbit PLL, combined with the digital adaptive equalizer and performance up to 120 meters for UTP 5. 125 MHz Clock Generator and Timing Recovery. Integrated Base Line Wander Correction. Carrier Integrity Monitor function supported. Supports FEFI when Auto Negotiation disabled. Supports Auto MDIX function for Plug-and-Play IEEE 802.3u Clause 28 compliant auto negotiation for full 10 Mbit/s and 100 Mbit/s control. Supports programmable LED for different Switch Application and Power On LED Self Test. Supports Cable Length Indication both in MII Register and LED (Programmable) Supports PECL interface for fiber connection. Supports TP vs. FX Medium Converter function. Supports Fault Propagation function for medium converter. Supports 10K Bytes Jumbo Packet with Clock Skew 150 ppm. Data Sheet 8 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Product Overview • • • • Built-in Clock Generator and Power On Reset Signal to save system cost. 48 LQFP without regulator. Supports Power saving function. Supports Parallel LED output. Data Sheet 9 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Product Overview 1.3 Block Diagram Figure 1 ADM7001/X Block Diagram Data Sheet 10 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Interface Description 2.1 Pin Diagram PHYAD4/RXD0 PYYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3 MDC MDIO RESET_N VCC33IN XI XO TEST1 GNDIK 2 VCCO_25 GNDIK RXDV/CRSDV/DIS_AMDIX RMII_EN/RX_CLK ISOLATE/RXER GNDO VCCIK_25 TXER TXCLK TXEN TXD0 TXD1 ADM7001L/T 48 Pin VCC25OUT(CORE) TXP TXN GNDPLL VCCPLL_25 RTX TEST0 GNDTR SD/FXEN RXP RXN VCCA_25 PWRDOWN_N ANEN/COLLED DUPFUL/DUPLED SPD100/SPDLED LNKACT PHYAD0/INTR VCCO_2.5 GNDO CRS COL/GPSI TXD3 TXD2 Figure 2 Pin Diagram 2.2 Pin Description Note: For those pins, which have multiple functions, pin name is separated by slash ("/"). If not specified, all signals are default to digital signals. Please refer to Table 1Pin Type Descriptions' for an explanation of pin abbreviations. Data Sheet 11 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. AO Output. Analog levels. AI/O Input or Output. Analog levels. PWR Power GND Ground MCL Must be connected to Low (JEDEC Standard) MCH Must be connected to High (JEDEC Standard) NU Not Usable (JEDEC Standard) NC Not Connected (JEDEC Standard) Table 2 Abbreviations for Buffer Type Abbreviations Description Z High impedance PU1 Pull up, 10 kΩ PD1 Pull down, 10 kΩ PD2 Pull down, 20 kΩ TS Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance. OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. OC Open Collector PP Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high (identical to output with no type attribute). OD/PP Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with the OD attribute or as an output with the PP attribute. ST Schmitt-Trigger characteristics TTL TTL characteristics Data Sheet 12 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.1 Twisted Pair Interface, 5 Pins Table 3 Twisted Pair Interface, 5 Pins Pin or Ball No. Name Pin Type 35 TXP AI/O Twisted Pair Transmit Output Positive 34 TXN AI/O Twisted Pair Transmit Output Negative 27 RXP AI/O Twisted Pair Receive Input Positive 26 RXN AI/O Twisted Pair Receive Input Negative 28 Power On Setting FXEN AI Fiber Enable Value on this pin will be latched by ADM7001/X/X during power on reset as fiber select signal. 0B , Twisted Pair Mode 1B , Fiber Optic Mode Fiber Mode SDP Data Sheet Buffer Type Function 100BASE-FX Signal Detect. After power on reset stage, this pin acts as signal detect signal from external fiber optic transceiver in case FXEN is detected as high during power on reset. 0B , No signal detected 1B , Signal 13 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.2 Digital Ground/Power, 7 Pins Table 4 Digital Ground/Power, 7 Pins Pin or Ball No. Name Pin Type 6, 17 GNDO D,GND Ground used by 3.3 V I/O. 2, 37 GNDIK D,GND Ground used by Core. 1, 18 VCCO_25 D,PWR 2.5V Power used by Digital I/O Pad. 7 VCCIK_25 D,PWR 2.5 V Power used by Core Data Sheet Buffer Type Function 14 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.3 Ground and Power, 5 Pins Table 5 Ground and Power, 5 Pins Pin or Ball No. Name Pin Type 41 VCC3IN A,PWR 3.3V Power input to ADM7001/X and used by built-in 3.3 V to 2.5 V regulator. 36 VCC25OUT A,PWR 2.5V Power output by ADM7001/X. Maximum Supply current from this pin is 200 mA 29 GNDTR A,GND Analog Ground Pad 25 VCCA_25 A,PWR Analog 2.5 V Power 32 VCCPLL_25 A,PWR Analog 2.5 V Power used by Clock Generator module. Data Sheet Buffer Type Function 15 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.4 Clock Input, 2 Pins Table 6 Clock Input, 2 Pins Pin or Ball No. Name Pin Type Buffer Type Function 40 XI/OSCI I CTL Crystal/Oscillator input. 25M Crystal/Oscillator Input in MII mode and 50M Clock input in RMII mode (Also called REFCLK in RMII Mode). Note: CTL: Crystal 39 XO O CTL Crystal output. When 25M Oscillator is used, this pin should left unconnected. Capable of driving one XI input for multiple port application. Note: CTL: Crystal 2.2.5 MII/RMII/GPSI Interface, 16 pins Table 7 MII/RMII/GPSI Interface, 16 pins Pin or Ball No. Name Pin Type Buffer Type Function 9 MII Mode TXCLK O 16mA MII Transmit Clock. 25M Clock output in 100BASE-X mode and 2.5M Clock output for 10BASE-T mode. This clock is continuously driven output and generated from XI. Before Speed is recognized, this pin drives out continuous 25M clock Data Sheet RMII Mode TXCLK N/A GPSI Mode TXCLK GPSI Transmit Clock. 10M Clock output in 10BASE-T mode. 16 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball No. Name Pin Type Buffer Type Function 14, 13, 12, 11 MII Mode TXD[3:0] I TTL PD Transmit Data. Nibble-wide transmit data stream in MII mode. These four bits are synchronous to the rising edge of TXCLK and TXD[3] is the most significant bit 10 8 RMII Mode TXD[3:0] Di-bits Transmit Data. TXD0 and TXD1 for the di-bits that are transmitted and are driven synchronously to REFCLK. TXD[1] is the MSB. Note that in 100Mb/s mode, TXD can change once per REFCLK cycle, whereas in 10Mb/s mode, TXD must be held steady for 10 consecutive REFCLK cycles. TXD[3] and TXD[2] are not used in RMII Mode, left unconnected or pull down externally for normal operation. GPSI Mode TXD[3:0] Serial Transmit Data. TXD0 for the designated port inputs the data that is transmitted and is driven synchronously to TXCLK in 10Mb/s mode. When ADM7001/X is programmed into GPSI mode, TXD[3:1] should be left unconnected or pull down externally for normal operation. MII Mode TXEN TTL PD Transmit Enable. Transmit Enable to indicate that the data on TXD[3:0] is valid. RMII Mode TXEN Transmit Enable. TXEN indicates that the di-bit on TXD is valid and it is driven synchronously to REFCLK. GPSI Mode TXEN Transmit Enable. Transmit Enable to indicate that the data on TXD0 is valid. MII Mode TXER RMII Mode TXER GPSI Mode LOW Data Sheet I I TTL PD Transmit Error. Active high signal to indicate that there is error condition requested by MAC. Transmit Error. Active high signal to indicate that there is error condition requested by MAC. Keep Low in GPSI Mode. 17 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball No. Name Pin Type Buffer Type Function 4 Power On Setting RMII_EN I LVTTL PD RMII Enable. Used to select MII or RMII operation. The default value during power on reset is 0 (Before RMII_EN and GPSI value is determined) Note: LVTTL: Low Voltage TTL Level 0B 1B MII Mode RX_CLK O 16mA , MII Mode , RMII Mode MII Receive Clock. 25M Clock output in 100BASE-X mode, 2.5M Clock output for 10BASE-T MII mode. This clock is recovered from the received data on the cable input. Due to recovered from incoming receive data, it is possible that RXCLK starts running yet RXDV keeps low for a while. During power on reset, there is no receiving clock driven by ADM7001/X RMII Mode CLKO50 RMII 50M Clock Output. This pin outputs continuous 50M clock in RMII mode. To reduce the BOM cost for system application, user can connect this pin directly to REFCLK to proper RMII operation. GPSI Mode RX_CLK GPSI Receive Clock. 10M clock for 10BASE-T GPSI mode. This clock is recovered from the received data on the cable input. Due to recovered from incoming receive data, it is possible that RXCLK starts running yet CRS keeps low for a while. During power on reset, there is no receiving clock driven by ADM7001/X. Note: That clock on this pin will not be active during power on reset due to power on setting. Data Sheet 18 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball No. Name Pin Type 3 Power On I Setting DIS_AMDIX_EN Buffer Type Function LVTTL PD Disable Auto Crossover Function Value on this pin will be latched by ADM7001/X to select Auto Cross-Over Function. Note: LVTTL: Low Voltage TTL Level 0B 1B MII Mode RXDV 45, 46, 47, 48 Data Sheet O 8mA , Enable Auto Crossover , Disable Auto Crossover MII Receive Data Valid. Active high signal to indicate that the data on RXD[3:0] is valid. Synchronous to the rising edge of RXCLK in MII mode. RMII Mode CRSDV RMII Carrier Sense/Receive Data Valid. Represents Receive Carrier Sense and Data Valid in RMII mode. CRSDV asserts when the receive medium is nonidle. The assertion of CRSDV is asynchronous to REFCLK. At the de-assertion of carrier, CRSDV de-asserts synchronously to REFCLK only on the first di-bit of RXD. If there is still data in the FIFO not yet presented onto RXD, then on the second di-bit of RXD, CRSDV is asserted synchronously to REFCLK. The toggling of CRSDV_P on the first and second di-bit continues until all the data in the FIFO is presented onto RXD. CRSDV is asserted for the duration of carrier activity for a false carrier event. GPSI Mode LOW Keep Low in GPSI Mode. Power On Setting PHYAD[1:4] I TTL PD PHY Address Select Value on these 4 pins combined with PHYAD0 will be stored into ADM7001/X as PHY physical address during power on reset. After power on reset, these 4 pins are output. MII Mode RXD[3:0] O 8mA MII Receive Data. Nibble-wide receive data stream in MII mode. These four bits are synchronous to the rising edge of RX_CLK and RXD[3] is the most significant bit. RMII Mode RXD[1:0] RMII Receive Data. RXD0 and RXD1 for the di-bits that are received and are driven synchronously to REFCLK. RXD[1] is the MSB. Note that in 100Mb/s mode, RXD can change once per REFCLK cycle, whereas in 10Mb/s mode, RXD must be held steady for 10 consecutive REFCLK cycles. RXD[3:2] have not used in this mode. GPSI Mode RXD GPSI Receive Data. RXD0 for the designated port inputs the data that is transmitted and is driven synchronously to RX_CLK in 10Mb/s mode. RXD[3:1] have not used in this mode. 19 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball No. Name Pin Type Buffer Type Function 5 Power On Setting ISOLATE I TTL PD ISOLATE Value on this pin will be latched by ADM7001/X during power on reset. 0B , Normal Operation 1B , All MII outputs are tri-stated. All MII Inputs(TXD, TXEN, TXER) are ignored MII Mode RXER O 4mA MII Receive Error. Active high signal to indicate that there is error condition detected by ADM7001/X. When error is detected, RXER will be high and maintains high until RXDV is de-asserted. 15 RMII Mode RXER RMII Receive Error. Active high signal to indicate that there is error condition detected by ADM7001/X. When error is detected, RXER will be high and maintains high until CRSDV is de-asserted. GPSI Mode N/A No Operation in GPSI Mode. Power On Setting GPSI I PD GPSI Mode Select Value on this pin will be sampled by ADM7001/X during power on reset to form GPSI internal control signal. Together with RMII_EN, these two pins form three possible internal supported by ADM7001/X. RMII_EN GPSI Interface 0B , 0B MII 0B , 1B GPSI(1M8) 1B , x RMII GPSI/MII Mode COL O 8mA GPSI/MII Collision In half duplex mode, active high to indicate that there is collision on the medium. In full duplex mode, this pin will keep low all the time. RMII Mode N/A Data Sheet Not Available 20 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball No. Name Pin Type Buffer Type Function 16 Power On Setting REPEATER I LVTTL PD Repeater Mode. Value on this pin will be latched by ADM7001/X during power on reset as repeater mode Note: LVTTL: Low Voltage TTL Level 0B 1B MII Mode CRS O 8mA , SW/NIC mode, CRS will be asserted according to RX/TX in half duplex mode. , REPEATER mode. CRS will be asserted only in RX mode in half duplex operation. MII Carrier Sense. This bit indicates that there is carrier sense presented on the medium. Note that in half duplex mode, this pin will also be asserted high by ADM7001/X under transmit condition. This pin is asynchronous to RX_CLK. RMII Mode N/A Not Available. GPSI Mode CRS GPSI Carrier Sense. This bit indicates that there is carrier sense presented on the medium. Note that in half duplex mode, this pin will also be asserted high by ADM7001/X under transmit condition. This pin is asynchronous to RX_CLK. Note: LVTTL: Low Voltage TTL Level Data Sheet 21 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.6 Reset Pin Table 8 Reset Pin Pin or Ball No. Name Pin Type Buffer Type Function 42 RESET# I ST Reset Signal Active low to bring ADM7001/X into reset condition. Recommend keeping low for at least 200 ms to ensure the stability of the system after power on reset. 2.2.7 Clock Signals, 6 Pins Table 9 Clock Signals, 6 pins Pin or Ball Name No. Pin Type Buffer Type Function 43 MDIO I/O LVTTL PU Management Data. MDIO transfers management data in and out of the device synchronous to MDC. 44 MDC I LVTTL Note: LVTTL: Low Voltage TTL Level Management Data Reference Clock. A non-continuous clock input for management usage. ADM7001/X will use this clock to sample data input on MDIO and drive data onto MDIO according to rising edge of this clock. Note: LVTTL: Low Voltage TTL Level 19 Power On Setting PHYAD0 MII/RMII/GPSI Mode INTR# I LVTTL PU PHY Address bit 0. See RXD[3:0] description. Note: LVTTL: Low Voltage TTL Level Interrupt Default active low signal to indicate that there is interrupt event in SMI register. Active value of interrupt signal can be configured by register 18.1. Only available when interrupt mode is selected. Note: LVTTL: Low Voltage TTL Level Data Sheet 22 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 9 Clock Signals, 6 pins (cont’d) Pin or Ball Name No. Pin Type Buffer Type Function 24 I LVTTL PU Low Power Operation. PWRDOWN# Note: When RESET# is reset to 0 and PWRDOWN# is set to 0, whole ADM7001/X blocks will be disabled. 0B 1B 38, 30 TEST[1:0] I LVTTL PD , ADM7001/X in low power mode operation. All blocks except the energy detection and crystal oscillator are deactivated. , ADM7001/X in normal mode operation. Note: LVTTL: Low Voltage TTL Level Industrial Test Pin. Keeps low for normal operation. Note: LVTTL: Low Voltage TTL Level Data Sheet 23 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description 2.2.8 LED Interface, 4 Pins Table 10 LED Interface, 4 Pins Pin or Ball Name No. Pin Buffer Type Type Function 20 Reserved I TTL PU Reserved. LNKACT O 8mA Link/Activity LED. Active low (Note) 100ms (blink 100ms) to indicate that there is transmit or receive activity after Link Up. Keeps high all the time when link is failed. Power On Setting SPD100 I TTL PU Recommend 100M Operation. This bit is only available in TP mode. Together with ANEN to form speed mode select for ADM7001/X: ANEN SPD100 Mode 0B , 0B Force 10BASE-T Mode 0B , 1B Force 100BASE-TX Mode 1B , 0B 10M Capability 1B , 1B 10/100M Capability Normal Mode SPDLED O 8mA Speed LED.(Note) 0B , 100M 1B , 10M Cable Length LED. When FXEN is low and MII register 18.2 DIS_CABLEN_LED is set to 0, this pin together with COLLED and LNKACTLED form cable length information on twisted pair Note: That the following indication assume recommend value on SPDLED, COLLED and LNKACTLED is high, when corresponding bit's power on setting bit is 0, polarity of corresponding bit will be inverted. SPDLED COLLED LNKACTLED Cable Length 21 Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. 110B 110B 100B 000B xxxB Data Sheet 24 , , , , , Flashed >140 meters or Link Failed 0 - 40 meters 40 - 80 meters 80 - 120 meters Reserved Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Interface Description Table 10 LED Interface, 4 Pins (cont’d) Pin or Ball Name No. Pin Buffer Type Type Function 22 Power On Setting DUPFUL I TTL PU Duplex Control This pin is only available when auto negotiation is disabled. ANEN DUPFUL Mode 0B , 0B Force to Half Duplex Mode 0B , 1B Force to Full Duplex Mode 1B , 0B Half Duplex Capability 1B , 1B Full/Half Duplex Capability Normal Mode DUPLED O 8 mA Duplex LED.(Note) Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. This rule also applies to Cable Length indication 0B 1B 23 , Full Duplex , Half Duplex Power On Setting ANEN I TTL PU Auto Negotiation Enable. This bit is only available in TP mode. 0B , Disable Auto Negotiation 1B , Enable Auto Negotiation Normal Mode COLLED O 8mA Collision LED. Keep high (Note) when ADM7001/X is in full duplex mode and will blink 100 ms when collision condition is detected in half duplex mode. Note: When recommend value during power on is high, then this signal is active low; if the recommend value is low, then this signal is active high. 2.2.9 Regulator Control Table 11 Regulator Control Pin or Ball No. Name Pin Type 31 RTX AI Data Sheet Buffer Type Function Constant Voltage Reference. External 1.1kΩ +/- 1% resistor connection to ground. 25 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description 3 Function Description ADM7001/X integrates 100Base-X physical sub layer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, and complete 10Base-T modules into a single chip for both 10 Mbps and 100 Mbps Ethernet operations. It also supports 100Base-FX operation through external fiber-optic transceivers. The device is capable of operating in either full-duplex mode or half-duplex mode in either 10 Mbps or 100 Mbps operation. Operational modes can be selected by hardware configuration pins, software settings of management registers, or determined by the on-chip auto negotiation logic. The 10Base-T section of the device consists of the 10 Mbps transceiver module with filters and a Manchester ENDEC module. ADM7001/X consists of seven kinds of major blocks: • • • • • • • 10/100M PHY Block MAC Interface LED Display SMI Power Management Clock Generator Voltage Regulator Each 10/100M PHY block contains: • • • • 10M PHY block 100M PHY block Auto-negotiation Other Digital Control Blocks 3.1 10/100M PHY Block The 100Base-X section of the device implements the following functional blocks: • • • 100Base-X physical coding sub-layer (PCS) 100Base-X physical medium attachment (PMA) Twisted-pair PMD (TP-PMD) transceiver The 100Base-X and 10Base-T sections share the following functional blocks: • • • Clock synthesizer module MII Registers IEEE 802.3u auto negotiation The interface used for communication between PHY block and switch core is MII interface. 3.1.1 100Base-X Module ADM7001/X implements 100Base-X compliant PCS and PMA, and 100Base-TX compliant TP-PMD as illustrated in Figure 3. Bypass options for each of the major functional blocks within the 100Base-X PCS provide flexibility for various applications. 100 Mbit/s PHY loop back is included for diagnostic purpose. 3.1.2 100Base-TX Receiver For 100Base-TX operation, the on-chip twisted pair receiver that consists of a differential line receiver, an adaptive equalizer and a base-line wander compensation circuits detects the incoming signal. ADM7001/X uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable. Data Sheet 26 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7001/X implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application. Alternatively, the receive data stream may be generated by an external optical receiver as in a 100Base-FX application. The receiver block consists of the following functional sub-blocks: • • • • • • • • • A/D Converter Adaptive Equalizer and Timing Recovery Module NRZI/NRZ and Serial/Parallel Decoder De-scrambler Symbol Alignment Block Symbol Decoder Collision Detect Block Carrier Sense Block Stream Decoder Block A/D Converter 5;67$7 ( 0$&+,1( )LEHU2SWLF 5HFHLYHU $'$37,9((48$/,=(5 &/2&.'$7$5(&29(5< 6(5,$/723$5$//(/ %% '(&2'(5 15=,WR% '(6&5$0%/(5 0,,7260,,&219(57(5 $'%ORFN High performance A/D converter with 125M sampling rate converts signals received on RXP/RXN pins to 6-bits data streams; besides it possess auto-gain-control capability that will further improve receive performance especially under long cable or harsh detrimental signal integrity. Due to high pass characteristic on transformer, built in base-line-wander correcting circuit will cancel it out and restore its DC level. 0/7 67$ 7( 0$&+,1( 15=WR15=, 3$5$//$/726(5,$/ 6&5$0%/(5 7;67$7( 0$&+,1 ( %%'(&2'(5 60,,720,,&219(57(5 7; '5,9(5 ),%(5 237 ,& '5,9(5 Figure 3 100Base-X Block Diagram and Data Path Adaptive Equalizer and Timing Recovery Module All digital design is especially immune from noise environments, and achieves better correlations between production and system testing. Baud rate Adaptive Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed Data Sheet 27 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description forward and Decision Feedback techniques meets the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 140 meters. NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary. Data Descrambling The descrambler acquires synchronization with the data stream by recognizing idle bursts of 40 or more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to the state of the scrambling LFSR. Upon achieving synchronization, the incoming data is XORed by the deciphering LFSR and descrambled. In order to maintain synchronization, the descrambler continuously monitors the validity of the unscrambled data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 µs countdown. Upon detection of at least 6 idle symbols (30 consecutive 1) within the 722 µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely to give a properly operating network connection with good signal integrity. If the link state monitor does not recognize at least 6 unscrambled idle symbols within 722 µs period, the descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. Symbol Alignment The symbol alignment circuit in the ADM7001/X determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. Symbol Decoding The symbol decoder functions as a look-up table that translates incoming 5B symbols into 4B nibbles as shown in Table 12. The symbol decoder first detects the /J/K symbol pair preceded by idle symbols and replaces the symbol with MAC preamble. All subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD). The translated data is presented on the internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the translated nibble. Table 12 Look-up Table for Translating 5B Symbols into 4B Nibbles PCS Code-Group[4:0] Name MII (TXD/RXD)<3:0> Interpretation 11110 0 0000 Data 0 01001 1 0001 Data 1 10100 2 0010 Data 2 10101 3 0011 Data 3 01010 4 0100 Data 4 01011 5 0101 Data 5 01110 6 0110 Data 6 01111 7 0111 Data 7 10010 8 1000 Data 8 10011 9 1001 Data 9 10110 A 1010 Data A 10111 B 1011 Data B Data Sheet 28 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Table 12 Look-up Table for Translating 5B Symbols into 4B Nibbles (cont’d) PCS Code-Group[4:0] Name MII (TXD/RXD)<3:0> Interpretation 11010 C 1100 Data C 11011 D 1101 Data D 11100 E 1110 Data E 11101 F 1111 Data F 11111 I Undefined IDLEused as inter-stream fill code 11000 J 0101 Start-of-Stream Delimiter, Part 1 of 2; always used in pairs with K 10001 K 0101 Start-of-Stream Delimiter, Part 2 of 2; always used in pairs with J 01101 T Undefined Start-of-Stream Delimiter, Part 1 of 2; always used in pairs with R 0111 R Undefined Start-of-Stream Delimiter, Part 2 of 2; always used in pairs with T 00100 H Undefined Transmit Error; used to force signaling errors 00000 V Undefined Invalid code 00001 V Undefined Invalid code 00010 V Undefined Invalid code 00011 V Undefined Invalid code 00101 V Undefined Invalid code 00110 V Undefined Invalid code 01000 V Undefined Invalid code 01100 V Undefined Invalid code 10000 V Undefined Invalid code 11001 V Undefined Invalid code Valid Data Signal The valid data signal (RXDV) indicates that recovered and decoded nibbles are presented on the internal RXD[3:0] synchronous to receive clock, RXCLK. RXDV is asserted when the first nibble of translated /J/K is ready for transfer over the internal MII. It remains active until either the /T/R delimiter is recognized, link test indicates failure, or no signal is detected. On any of these conditions, RXDV is deasserted. Receive Errors The RXER signal is used to communicate with receiver error conditions. While the receiver is in a state of holding RXDV asserted, the RXER will be asserted for each code word which does not map to a valid code-group. 100Base-X Link Monitor The 100Base-X link monitor function allows the receiver to ensure that reliable data is received. Without reliable data reception, the link monitor will halt both transmit and receive operations until a valid link is detected. The ADM7001/X performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10 Mbits/s link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin. When persistent signal energy is detected on the network, the logic moves into a Link-Ready state after approximately 500 µs, and waits for an enable from the auto negotiation module. When receiving, the link-up state Data Sheet 29 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description is entered, and the transmission and reception logic blocks become active. Should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. Carrier Sense Carrier sense (CRS) for 100 Mbits/s operation is asserted upon the detection of two non contiguous zeros occurring within any 10-bit boundary of the received data stream. The carrier sense function is independent of symbol alignment. In switch mode, CRS is asserted during either packet transmission or reception. For repeater mode, CRS is asserted only during packet reception. When the idle symbol pair is detected in the received data stream, CRS is deasserted. In repeater mode, CRS is only asserted due to receive activity. CRS is intended to encapsulate RXDV. Bad SSD Detection A bad start of stream delimiter (Bad SSD) is an error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-group (SSD) is not received. If this condition is detected, the ADM7001/X will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to receive 5B code-groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become deasserted. Far-End Fault Auto negotiation provides a mechanism for transferring information from the Local Station to the link Partner that a remote fault has occurred for 100Base-TX. As auto negotiation is not currently specified for operation over fiber, the far end fault indication function (FEFI) provides this capability for 100Base-FX applications. A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected wire at a station’s transmitter. This station will receive valid data and detect that the link is good via the link integrity monitor, but will not be able to detect that its transmission is not propagating to the other station. A 100Base-FX station that detects such a remote fault may modify its transmitted idle stream from all ones to a group of 84 ones followed by a single 0. This is referred to as the FEFI idle pattern. The FEFI function is controlled by bit 3 of register 11H. It is initialized to 1 (encoded) if the SELFX pin is at logic high level during power on reset. If the FEFI function is enabled the ADM7001/X will halt all current operations and transmit the FEFI idle pattern when FOSD signal is de-asserted following a good link indication from the link integrity monitor. FOSD signal is generated internally from the internal signal detect circuit. Transmission of the FEFI idle pattern will continue until link up signal is asserted. If three or more FEFI idle patterns are detected by the ADM7001/X, bit 4 of the Basic mode status register (address 1h) is set to one until read by management. Additionally, upon detection of far end fault, all receive and transmit MII activities are disabled/ignored. 3.1.3 100Base-TX Transmitter ADM7001/X implements a TP-PMD compliant transceiver for 100Base-TX operation. The differential transmit driver is shared by the 10Base-T and 100Base-TX subsystems. This arrangement results in one device that uses the same external magnetics for both the 10Base-T and the 100Base-TX transmission with simple RC component connections. The individually wave-shaped 10Base-T and 100Base-TX transmit signals are multiplexed in the transmission output driver selection. ADM7001/X 100Base-TX transmission driver implements MLT-3 translation and wave-shaping functions. The rise/fall time of the output signal is closely controlled to conform to the target range specified in the ANSI TP-PMD standard. 3.1.4 100Base-FX Receiver Signal is received through PECL receiver inputs from fiber transceiver, and directly passed to clock recovery circuit for data/clock recovery. Scrambler/de-scrambler is bypassed in 100Base-FX. Data Sheet 30 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Automatic “Signal_Detect“ Function Block When DIS_ANASDEN_N in register 18 is set to 0, ADM7001/X doesn't support SDP detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001/X uses the data on RXP/RXN to detect consecutive 65 “1” on the receive data (Recovered from RXP/RXN) to determine whether “Signal” is detected or not. When the detect condition is true (Consecutive 65 bits “1”), internal signal detect signal will be asserted to inform receive relative blocks to be ready for coming receive activities. 3.1.5 100Base-FX Transmitter In 100Base FX transmit, the serial data stream is driven out as NRZI PECL signals, which enter fiber transceiver in differential-pairs form. Fiber transceiver should be available working at 3.3 V environment. 3.1.6 10Base-T Module The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard. Figure 4 provides an overview for the 10Base-T module. The ADM7001/X 10Base-T module is comprised of the following functional blocks: • • • • • • • Manchester encoder and decoder Collision detector Link test function Transmit driver and receiver Serial and parallel interface Jabber and SQE test functions Polarity detection and correction 3.1.7 Operation Modes The ADM7001/X 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In halfduplex mode, the ADM7001/X functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmitting and receiving. In full duplex mode the ADM7001/X can simultaneously transmit and receive data. 3.1.8 Manchester Encoder/Decoder Data encoding and transmission begin when the transmission enable input (TXEN) goes high and continues as long as the transceiver is in good link state. Transmission ends when the transmission enable input goes low. The last transition occurs at the center of the bit cell if the last bit is 1, or at the boundary of the bit cell if the last bit is 0. A differential input receiver circuit accomplishes decoding and a phase-locked loop that separates the Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when no more mid bit transitions are detected. Within one and half bit times after the last bit, carrier sense is deasserted. 3.1.9 Transmit Driver and Receiver The ADM7001/X integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmission signal are attenuated properly. 3.1.10 Smart Squelch The smart squelch circuit is responsible for determining when valid data is present on the differential receives. The ADM7001/X implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that impulse Data Sheet 31 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description noise on the receive inputs will not be mistaken for a valid signal. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs. The "analog squelch circuit" checks the signal at the start of the packet and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150ns. Finally, the signal must exceed the original squelch level within an additional 150ns to ensure that the input waveform will not be rejected. Figure 4 ),/7(5 15=WR15=, 0$1&+(67(5 &2'('(&2'(5 0720,, 60$57648(/7+ 0$1&+(67(5&2'( (1&2'(5 0,,720 60,,720,,&219(57(5 0,,7260,,&219(57(5 Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. 5(&(,9( ),/7(5 :$9( 6+$3(5 7; '5,9(5 10Base-T Block Diagram and Data Path Valid data is considered to be present until the squelch level has not been generated for a time longer than 200 ns, indicating end of packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise, causing premature end-of-packet detection. The receive squelch threshold level can be lowered for use in longer cable applications. This is achieved by setting bit 7 of register address 10H. 3.1.11 Carrier Sense Carrier Sense (CRS) is asserted due to receive activity once valid data is detected via the smart squelch function. For 10 Mbit/s half duplex operation, CRS is asserted during either packet transmission or reception. For 10 Mbit/s full duplex and repeater mode operations, the CRS is asserted only due to receive activity. 3.1.12 Collision Detection Collision is detected internal to the MAC, which is generated by an AND function of TXEN and RXDV derived from internal timing recovery circuitry. Note should be taken that due to TXEN and RXDV are asynchronous to each other, COL signal outputted by ADM7001/X is irrelevant to either TXCLK or RXCLK. Data Sheet 32 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description 3.1.13 Jabber Function The jabber function monitors the ADM7001/X output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disable for the entire time that the TXEN signal is asserted. This signal has to be de-asserted for approximately 408 ms (The un-jab time) before the jabber function re-enables the transmit outputs. The jabber function can be disabled by programming bit 0 of register address 10H to high. 3.1.14 Link Test Function A link pulse is used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10Base-T twisted-pair transmitter, receiver, and collision detection functions. The link pulse generator produces pulses as defined in IEEE 802.3 10Base-T standard. Each link pulse is nominally 100 ns in duration and is transmitted every 16 ms, in the absence of transmit data. Setting bit 10 of register 10H to high can disable link pulse check function. 3.1.15 Automatic Link Polarity Detection ADM7001/X's 10Base-T transceiver module incorporates an “automatic link polarity detection circuit”. The inverted polarity is determined when seven consecutive link pulses of inverted polarity or three consecutive packets are received with inverted end-of-packet pulses. If the input polarity is reversed, the error condition will be automatically corrected and reported in bit 13 of register 11H. 3.1.16 Clock Synthesizer The ADM7001/X implements a clock synthesizer that generates all the reference clocks needed from a single external frequency source. The clock source must be a TTL level signal at 25 MHz ± 50ppm. 3.1.17 Auto Negotiation The Auto Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provides the signaling used to communicate auto negotiation abilities between two devices at each end of a link segment. For further detail regarding auto negotiation, refer to Clause 28 of the IEEE 802.3u specification. The ADM7001/X supports four different Ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. The auto negotiation function within the ADM7001/X can be controlled either by internal register access or by the use of configuration pins are sampled. If disabled, auto negotiation will not occur until software enables bit 12 in register 0. If auto negotiation is enabled, the negotiation process will commence immediately. When auto negotiation is enabled, the ADM7001/X transmits the abilities programmed into the auto negotiation advertisement register at address 04H via FLP bursts. Any combination of 10 Mbps, 100 Mbps, half duplex and full duplex modes may be selected. Auto negotiation controls the exchange of configuration information. Upon successfully auto negotiation, the abilities reported by the link partner are stored in the auto negotiation link partner ability register at address 05H. The contents of the “auto negotiation link partner ability register” are used to automatically configure to the highest performance protocol between the local and far-end nodes. Software can determine which mode has been configured by auto negotiation by comparing the contents of register 04H and 05H and then selecting the technology whose bit is set in both registers of highest priority relative to the following list. • • • 100Base-TX full duplex (highest priority) 100Base-TX half duplex 10Base-T full duplex Data Sheet 33 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description • 10Base-T half duplex (lowest priority) The basic mode control register at address 0H provides control of enabling, disabling, and restarting of the auto negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between 10 Mbps or 100 Mbps operation, while the duplex mode bit (bit 8) controls switching between full duplex operation and half duplex operation. The speed selection and duplex mode bits have no effect on the mode of operation when the auto negotiation enable bit (bit 12) is set. The basic mode status register (BMSR) at address 1H indicates the set of available abilities for technology types (bit 15 to bit 11), auto negotiation ability (bit 3), and extended register capability (bit 0). These bits are hardwired to indicate the full functionality of the ADM7001/X. The BMSR also provides status on: • • • Whether auto negotiation is complete (bit 5) Whether the Link Partner is advertising that a remote fault has occurred (bit 4) Whether a valid link has been established (bit 2) The auto negotiation advertisement register at address 4H indicates the auto negotiation abilities to be advertised by the ADM7001/X. All available abilities are transmitted by default, but writing to this register or configuring external pins can suppress any ability. The auto negotiation link partner ability register at address 05H indicates the abilities of the Link Partner as indicated by auto negotiation communication. The contents of this register are considered valid when the auto negotiation complete bits (bit 5, register address 1H and bit 4, register 17H) are set. 3.1.18 Auto Negotiation and Speed Configuration The twelve sets of four pins listed in Table 13 configure the speed capability of each channel of ADM7001/X. The logic state of these pins is latched into the advertisement register (register address 4H) for auto negotiation purpose. These pins are also used for evaluating the default value in the base mode control register (register 0H) according to Table 13 Channel Configuration. 3.2 MAC Interface The ADM7001/X interfaces to 10/100 Media Access Controllers (MAC) via the RMII, MII, or GPSI Interface. 3.2.1 Reduced Media Independent Interface (RMII) The reduced media Independent interface (RMII) is compliant to the RMII consortium’s RMII Rev. 1.2 specification. The REFCLK pin that supplies the 50 MHz reference clock to the ADM7001/X is used as the RMII REFCLK signal. All RMII signals with the exception of the assertion of CRSDV_P are synchronous to REFCLK. See Figure 5 Data Sheet 34 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 5 RMII Signal Diagram 3.2.2 Receive Path for 100M Figure 6 shows the relationship among REFCLK, CRSDV, RXD and RXER while receiving a valid packet. Carrier sense is detected, which causes CRSDV to assert asynchronously to REFCLK. The received data is then placed into the FIFO for resynchronization. After a minimum of 12 bits are placed into the FIFO, the received data is presented onto RXD[1:0] synchronously to REFCLK. Note that while the FIFO is filling up RXD[1:0] is set to 00 until the first received di-bit of preamble (01) is presented onto RXD[1:0]. When carrier sense is de-asserted at the end of a packet, CRSDV is de-asserted when the first di-bit of a nibble is presented onto RXD[1:0] synchronously to REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1:0], then on the second dibit of a nibble, CRSDV reasserts. This pattern of assertion and de-assertion continues until all received data in the FIFO has been presented onto RXD[1:0]. RXER is inactive for the duration of the received valid packet. Figure 7 shows the relationship among REFCLK, CRSDV and RXD[1:0] during a received false carrier event. CRSDV is asserted asynchronously to REFCLK as in the valid receive case shown in . However, once false carrier is detected, RXD[1:0] is changed to (10) (11) (Value 1110 in MII) and RXER is asserted. Both RXD[1:0] and RXER transition synchronously to REFCLK. After carrier sense is de-asserted, CRSDV is de-asserted synchronously to REFCLK. REFCLK CRSDV RXD 00 00 00 00 00 00 01 01 01 01 01 11 Data Data Data Data Data Data Data Data Data 00 00 00 RXER Carrier Sense Detected Preamble Carrier Deasserted SFD Data Figure 6 Data Sheet RMII Reception Without Error 35 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 7 RMII Reception with False Carrier (100M Only) A receive symbol error event is shown in Figure 8. The packet with the symbol error is treated as if it were a valid packet with the exception that all di-bits are substituted with the (01) pattern. Figure 8 RMII Reception with Symbol Error 3.2.3 Receive Path for 10M Figure 9 10M RMII Receive Diagram In 10M Mode, RXER will maintain low all the time due to False Carrier and symbol error is not supported by 10M Mode. Different from 100M mode, RXD and CRSDV can transit once per 10 REFCLK cycles. After carrier sense is de-asserted yet the FIFO data is not fully presented onto RXD, the CRSDV de-assertion and re-assertion also follow this rule. 3.2.4 Transmit Path for 100M Figure 10 shows the relationship among REFCLK, TXEN and TXD[1:0] during a transmit event. TXEN and TXD[1:0] are synchronous to REFCLK. When TXEN is asserted, it indicates that TXD[1:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored. If an odd number of di-bits are presented onto TXD[1:0] and TXEN, the final di-bit will be discarded by ADM7001/X. Data Sheet 36 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description !" Figure 10 Data Sheet 100M RMII Transmit Diagram 37 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description 3.2.5 Transmit Path for 10M In 10MBSE-T mode, each di-bit must be repeated 10 times by the MAC, TXEN and TXD[1:0] should be synchronous to REFCLK. When TXEN is asserted, it indicates that data on TXD[1:0] is valid for transmission. In 10Base-T mode, it is possible that the number of preamble bits and the number of frame bits received are not integer nibbles. The preamble is always padded up such that the SFD appears on the RMII aligned to the nibble boundary. Extra bits at the end of the frame that do not complete a nibble are truncated by AD7001. Figure 11 shows the timing diagram for 10M Transmission. Figure 11 10M RMII Transmit Diagram Table 13 Channel Configuration Recommend Value Auto Negotiation ANENDIS REC_10M TP_FULL DUPLEX Enable 1 1 1 √ 1 1 0 √ 1 0 1 √ 1 0 0 √ 0 1 1 √ 0 1 0 √ 0 0 1 √ 0 0 0 √ 3.2.6 Disable Capability 100 Full 100 Half 10 Full 10 Half √ √ √ √ √ √ √ √ √ √ √ √ √ Media Independent Interface (MII) Signal Diagram for MII interface is shown in Figure 12. Data Sheet 38 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 12 MII Signal Diagram 3.2.7 Receive Path for MII Figure 13 shows the relationship among RXCLK, RXDV, RXD and CRS during a reception of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001/X. When ADM7001/X detects there is valid data, RXDV and the received data are presented onto RXD[3:0] synchronously to RX_CLK. Whenever received data is not valid anymore, RXDV will be de-asserted by ADM7001/X and "0" will be put on RXD[3:0]. Figure 13 MII Receive Without Error Figure 14 shows the relationship among RXCLK, RXDV and RXD[3:0] during a received false carrier event. CRS is asserted asynchronously to RXCLK as in the valid receive case shown in Figure 15. However, once false carrier is detected, RXD[3:0] is changed to (1110) and RXER is asserted. Both RXD[3:0] and RXER transit synchronously to RXCLK. Data Sheet 39 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 14 MII Receive With False Carrier A receive symbol error event is shown in Figure 15. The packet with the symbol error is treated as if it were a valid packet with the exception that all bits are substituted with the (0101) pattern. RXER will keep low in 10M Operation. Figure 15 Data Sheet MII Receive With Symbol Error(100M Only) 40 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description 3.2.8 Transmit Path for MII Figure 16 shows the relationship among TXCLK, TXEN and TXD[3:0] during a transmit event. TXEN and TXD[3:0] are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 25M in 100M mode and 2.5M in 10M mode. When TXEN is asserted, it indicates that TXD[3:0] contains valid data to be transmitted. When TXEN is de-asserted, value on TXD[1:0] should be ignored. Figure 16 MII Transmission When ADM7001/X operates in half duplex mode, either 10M or 100M, it will assert COL signal whenever it detects there is collision on the medium. Figure 17 shows the timing diagram for MII Collision. Figure 17 MII Transmit with Collision (Half Duplex Only) 3.2.9 General Purpose Serial Interface (GPSI) Signal Diagram for MII interface is shown in Figure 18. Data Sheet 41 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 18 GPSI Signal Diagram 3.2.10 Receive Path for GPSI Figure 19 shows the relationship among RXCLK, RXD and CRS during a receive of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001/X. When ADM7001/X detects there is valid data, received data is presented onto RXD synchronously to RXCLK. Whenever received data is not valid anymore, CRS will be de-asserted by ADM7001/X and "0" will be put on RXD. Figure 19 GPSI Receive Diagram 3.2.11 Transmit Path for GPSI Figure 20 shows the relationship among TXCLK, TXEN and TXD during a transmit event. TXEN and TXD are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 10M in 10M mode. When TXEN is asserted, it indicates that TXD contains valid data to be transmitted. When TXEN is de-asserted, value on TXD should be ignored. Data Sheet 42 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 20 GPSI Transmit Diagram 3.3 LED Display Register 19 is used for different mode led display. ADM7001/X provides power on LED self test to minimize and ease the system test cost. All LEDs will be Off during power on reset (Output value same as recommend value on LED pins). After power on reset, all internal parallel LEDs will be On for 2 seconds to ease manufacture overhead There are three types of LED supported by ADM7001/X internally. The first is LNKACT, which represents the status of Link and Transmit/Receive Activity, the second is LDSPD, which indicates the speed status, and the last is DUPCOL, which shows pure duplex status in full duplex and duplex/collision combined status in half duplex. All these three LED can be controlled by Register 19 to change display contents. After LED self test, Table 14, Table 15,Table 16 show the On/Off polarity according to different recommended value setting for LDSPD, DUPCOL and LNKACT. When the recommend value is high, ADM7001/X will drive LED LOW; ADM7001/X will drive the LED HIGH when the recommend value is low, instead. Table 14 Speed LED Display SPEED SPDLED 10M 0 100M 1 LINK FAIL 1 Table 15 DUPLEX Duplex LED Display DUPCOL HALF FULL LINK UP Blink (HIGH) When Collision LOW All the Time LINK FAIL HIGH All the Time HIGH All the Time Table 16 SPEED Activity/Link LED Display Link/Activity Link Activity LINK UP LOW Blink (HIGH) When RX/TX LINK FAIL HIGH All the Time HIGH All the Time Besides duplex, speed, link and activity status, ADM7001/X also provides cable information that can be shown on LEDs when register 19 is programmed to distance LED display (see Table 17) Data Sheet 43 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Table 17 Cable Distance LED Display LNKACT DUPCOL LEDSPD Cable Distance 1 1 0 0 to 40 meters 1 0 0 40 to 80 meters 0 0 0 80 to 120 meters 1 1 1 Reserved 3.4 Management Register Access The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The ADM7001/X is designed to support an MDC frequency specified in the IEEE specification of up to 2.5 MHz. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO pin requires a 1.5 KΩ pull-up which, during idle and turnaround periods, will pull MDIO to a logic one state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous logic one bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-of-frame field indicated by a <01> pattern. The next field signals the operation code (OP): <10> indicates read from MII management register operation, and <01> indicates write to MII management register operation. The next two fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most significant bit is transferred first. During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is provided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written into the MII management registers of the ADM7001/X 3.4.1 Preamble Suppression The ADM7001/X supports a preamble suppression mode as indicated by an 1 in bit 6 of the basic mode status register (Register 1h). If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management entity needs not to generate preamble for each management transaction. The ADM7001/X requires a single initialization sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by pullingup the resistor of MDIO. While the ADM7001/X will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. When ADM7001/X detects that there is physical address match, then it will enable Read/Write capability for external access. When neither physical address nor register address is matched, then ADM7001/X will tristate the MDIO pin. Figure 21 SMII Read Operation 3.4.2 Reset Operation The ADM7001/X can be reset either by hardware or software. A hardware reset is accomplished by applying a negative pulse, with duration of at least 200 ms to the RC pin of the ADM7001/X during normal operation to Data Sheet 44 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description guarantee internal Power On Reset Circuit is reset well. Setting the reset bit in the Basic Mode Control activates software reset Register (bit 15, register 0H). This bit is self-clearing and, when set, will return a value of 1 until the software reset operation has completed, please note that internal SRAM will not be reset during software reset. Figure 22 SMII Write Operation Hardware reset operation samples the pins and initializes all registers to their default values. This process includes re-evaluation of all hardware configurable registers. A software reset will reset an individual PHY and it does not latch the external pins nor reset the registers to their respective default value. Logic levels on several I/O pins are detected during a hardware reset to determine the initial functionality of ADM7001/X. Some of these pins are used as output ports after reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to VCC or Ground directly. Configuration pins multiplexed with logic level output functions should be either weakly pulled up or weakly pulled down through resistors. 3.5 Power Management An analog block is designed for carrier sense detecting. When there is no carrier sense presented on medium (cable not attached), then "SIGNAL DETECT" will not be ON. Whenever cable is attached to ADM7001/X and the voltage threshold is above +/- 50mV, then SD will be asserted HIGH to indicate that there is cable attached to ADM7001/X. All internal blocks except Management block will be disabled (reset) before SD is asserted. When SD is asserted, internal Auto Negotiation block will be turned on and the 10M transmit driver will also be turned on for auto negotiation process. Auto negotiation will issue control signals to control 10M receive and 100M A/D block according to different state in arbitration block diagram. During auto negotiation, all digital blocks except management and link monitor blocks will be disabled to reduce power consumption. Whenever operating speed is determined (Either auto negotiation is On or Off), the non-active speed relative circuit will be disabled all the time to save more power. For example, when corresponding port is operating on 10M, then 100M relative blocks will be disabled and 10M relative blocks will be disabled whenever corresponding port is in 100M mode. Auto negotiation block will be reset when SD signal goes from high to low. See Figure 23 for the state diagram for this algorithm. Data Sheet 45 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description Figure 23 Medium Detect Power Management Flow Chart Another way to reduce instant power is to separate the LED display period. All 4 LEDs will be divided into 4 time frame and each time frame occupies 1 us. One and only one LED will be driven at each time frame to reduce instant current consumed from LED. 3.6 Voltage Regulator ADM7001/X requires two different levels, 3.3 V and 2.5 V, of voltage supply to provide the power to different parts of circuitry inside the chip. ADM7001/X has a build-in voltage regulator circuitry to generate the 2.5 V voltage (VCC25OUT) from 3.3 V power source (VCC3IN). External Application Circuitry is shown in Figure 24. Data Sheet 46 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Function Description ˆˁˆ˩ ˖˄ ˄˃̈˙ ˖˅ ˃ˁ˄̈˙ ˖ˆ ˅ˁˈ˩ ˃ˁ˃˄̈˙ ˆˊ ˆˋ ˆˌ ˇ˃ ˇ˄ ˇ˅ ˇˆ ˇˇ ˇˈ ˇˉ ˇˊ ˇˋ ˖ˈ ˖ˉ ˃ˁ˄̈˙ ˅˅̈˙ GNDIK TEST1 XO XI VCC33IN RESET_N MDIO MDC PHYAD1/RXD3 PHYAD2/RXD2 PYYAD3/RXD1 PHYAD4/RXD0 ˖ˇ ˄̈˙ ˅ˁˈ˩ ˖ˊ ˄ ˃ˁ˄̈˙ ˅ ˆ ˖ˋ ˃ˁ˃˄̈˙ ˇ ˈ ˉ ˖ˌ ˃ˁ˄̈˙ ˊ ˋ ˌ ˖˄˅ ˃ˁ˃˄̈˙ ˄˃ ˄˄ ˄˅ VCCO_25 VCC25OUT(CORE) GNDIK RXDV/CRSDV/DIS_AMDIX TXP TXN RMII_EN/RX_CLK GNDPLL ISOLATE/RXER GNDO VCCPLL_25 RTX ADM7001 VCCIK_25 TXER TXCLK TEST0 GNDTR SD/FXEN QFP 48 TXEN TXD0 TXD1 RXP RXN VCCA_25 ˆˉ ˅ˁˈ˩ ˆˈ ˆˇ ˆˆ ˆ˅ ˩˖˖ˣ˟˟ ˖˄˃ ˆ˄ ˖˄˄ ˆ˃ ˅ˌ ˅ˋ ˄́˙ ˅ˊ ˅ˉ ˅˅̈˙ ˅ˈ ˅ˁˈ˩ PWRDOWN_N ANEN/COLLED DUPFUL/DUPLED SPD100/SPDLED FEFI_EN/LNKACT VCCO_2.5 PHYAD0/INTR GNDO TXD3 TXD2 CONV/REPEATER/CRS COL/GPSI ˅ˇ ˅ˆ ˅˅ ˅˄ ˅˃ ˄ˌ ˄ˋ ˄ˊ ˄ˉ ˄ˈ ˄ˇ ˄ˆ ˖˄ˆ ˖˄ˇ ˃ˁ˄̈˙ ˃ˁ˃˄̈˙ ˅ˁˈ˩ ˖˄ˈ ˄̈˙ ˖˄ˉ ˃ˁ˃˄̈˙ Figure 24 Data Sheet Power and Ground Filtering 47 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description 4 Registers Description Table 18 Registers Address Space Module Base Address End Address PHY 00H 1FH Table 19 Note Registers Overview Register Short Name Register Long Name Offset Address Page Number CR Control Register 00H 50 SR Status Register 01H 52 PHY_IR0 PHY Identifier Register 0 02H 55 PHY_IR1 PHY Identifier Register 1 03H 55 Advertisement Auto Negotiation Advertisement Register 04H 56 ANLPA Auto Negotiation Link Partner Ability 05H 57 ANER Auto Negotiation Expansion Register 06H 58 Res0 Reserved 0 07H 59 GPCR Generic PHY Control/Configuration Register 10H 60 P10_MCR PHY 10M Module Configuration Register 11H 62 P100_MCR PHY 100M Module Control Register 12H 64 LCR LED Configuration Register 13H 65 IER Interrupt Enable Register 14H 67 PGSR PHY Generic Status Register 16H 68 PSSR PHY Specific Status Register 17H 69 PRVSR PHY Recommend Value Status Register 18H 70 ISR Interrupt Status Register 19H 71 RECR Receive Error Counter Register 1DH 72 CIR Chip ID Register 1FH 73 The register is addressed wordwise. Table 20 Registers Access Types Mode Symbol Description Hardware (HW) Description Software (SW) read/write rw Register is used as input for the HW Register is read and writable by SW read r Register is written by HW (register Value written by software is ignored by between input and output -> one cycle hardware; that is, software may write any delay) value to this field without affecting hardware behavior (= Target for development.) write w read/write hardware affected rwh Register is writable by SW Register can be modified by HW Register can be modified by HW, but the priority SW versus HW has to be specified rwv Data Sheet 48 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Table 20 Registers Access Types (cont’d) Mode Symbol Description Hardware (HW) Read only ro Register is set by HW (register between SW can only read this register input and output -> one cycle delay) Read virtual rv Physically, there is no new register, the SW can only read this register input of the signal is connected directly to the address multiplexer. Latch high, self clearing lhsc Latch high signal at high level, clear on SW can read the register read Latch low, self clearing llsc Latch high signal at low-level, clear on SW can read the register read Latch high, mask clearing lhmk Latch high signal at high level, register SW can read the register, with write mask cleared with written mask the register can be cleared (1 clears) Latch low, mask clearing llmk Latch high signal at low-level, register cleared on read SW can read the register, with write mask the register can be cleared (1 clears) Interrupt high, self clearing ihsc Differentiate the input signal (low>high) register cleared on read SW can read the register Interrupt low, self clearing ilsc Differentiate the input signal (high>low) register cleared on read SW can read the register Interrupt high, mask clearing ihmk Differentiate the input signal (highSW can read the register, with write mask >low) register cleared with written mask the register can be cleared Interrupt low, mask clearing ilmk Differentiate the input signal (low>high) register cleared with written mask SW can read the register, with write mask the register can be cleared Interrupt enable ien register Enables the interrupt source for interrupt generation SW can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset Register is read and writable by SW Read/write self clearing rwsc Register is used as input for the hw, the Writing to the register generates a strobe register will be cleared due to a HW signal for the HW (1 pdi clock cycle) mechanism. Register is read and writable by SW. Table 21 Registers Clock Domains Clock Short Name 4.1 Data Sheet Description Software (SW) Description Register Description 49 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Control Register CR Control Register Offset 00H 567 /3%. 66/ $1(1 3'1 UZVF UZ UZ UZ UZ ,62 UZ Reset Value 3000H 5$1 '3/; &7 660 5HV UZVF UZ UR UR UZ Field Bits Type Description RST 15 rwsc RESET Setting this bit initiates the software reset function that resets the selected port, except for the phase-locked loop circuit. It will re-latch in all hardware configuration pin values. The software reset process takes 25us to complete. This bit, which is self-clearing, returns a value of 1 until the reset process is complete. 0B RST_0, Normal operation 1B RST_1, PHY Reset LPBK 14 rw Back Enable This bit controls the PHY loop back operation that isolates the network transmitter outputs (TXP and TXN) and routes the MII transmit data to the MII receive data path. This function should only be used when auto negotiation is disabled (bit12 = 0). The specific PHY (10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13. 0B LPBK_0, Disable Loop back mode 1B LPBK_1, Enable loop back mode SSL 13 rw Speed Selection LSB SPEED_LSB 0.60.13 Link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored). 00B 10M, 10 Mbit/s 01B 100M, 100 Mbit/s 10B 1000M, 1000 Mbit/s 11B Res, Reserved ANEN 12 rw Auto Negotiation Enable This bit determines whether the link speed should set up by the auto negotiation process or not. It is set at power up or reset if the PI_RECANEN pin detects a logic 1 input level in Twisted-Pair Mode. 0B ANEN_0, Disable Auto negotiation process 1B ANEN_1, Enable auto negotiation process Data Sheet 50 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description PDN 11 rw Power Down Enable Ored result with PI_PWRDN pin. Setting this bit high or asserting the PI_PWRDN puts the PHY841F into power down mode. During the power down mode, TXP/TXN and all LED outputs are tristated and the MII/RMII interfaces are isolated. 0B PDN_0, Normal Operation 1B PDN_1, Power Down ISO 10 rw Isolate PHY841F from Network Setting this control bit isolates the part from the RMII/MII, with the exception of the serial management interface. When this bit is asserted, the PHY841F does not respond to TXD, TXEN and TXER inputs, and it presents a high impedance on its TXC, RXC, CRSDV, RXER, RXD, COL and CRS outputs. 0B ISO_0, Normal Operation 1B ISO_1, Isolate PHY from MII/RMII RAN 9 rwsc Restart Auto Negotiation ANEN_RST. Setting this bit while auto negotiation is enabled forces a new auto negotiation process to start. This bit is self-clearing and returns to 0 after the auto negotiation process has commenced. 0B RAN_0, Normal Operation 1B RAN_1, Restart Auto Negotiation Process DPLX 8 rw Duplex Mode If auto negotiation is disabled, this bit determines the duplex mode for the link. 0B DPLX_0, Half Duplex mode 1B DPLX_1, Full Duplex mode CT 7 rw Collision Test When set, this bit will cause the COL signal of MII interface to be asserted in response to the assertion of TXEN. 0B CT_0, Disable COL signal test 1B CT_1, Enable COL signal test SSM 6 ro Speed Selection MSB SPEED_MSB. Set to 0 all the time indicate that the PHY841F does not support 1000 Mbit/s function. Res 5:0 ro Reserved Not Applicable Data Sheet 51 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Status Register SR Status Register Offset 01H 7 7;) 7;+ 7) 7+ 7 5HV UR UR UR UR UR UR UR Data Sheet Reset Value 7849H 6835 $1B& 5)' $1(* /,1. -$% ;71' UR 52 UR UR UR UROO UROK UR Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description T4 15 ro 100Base-T4 Capable Set to 0 all the time to indicate that the PHY841F does not support 100Base-T4. TXF 14 100Base-X Full Duplex Capable Set to 1 all the time to indicate that the PHY841F does support Full Duplex mode. TXH 13 100Base-X Half Duplex Capable Set to 1 all the time to indicate that the PHY841F does support Half Duplex mode TF 12 10M Full Duplex Capable TP: Set to 1 all the time to indicate that the PHY841F does support 10M Full Duplex mode. FX: Set to 0 all the time to indicate that the PHY841F does not support 10M Full Duplex mode TH 11 10M Half Duplex Capable TP: Set to 1 all the time to indicate that the PHY841F does support 10M Half Duplex mode. FX: Set to 0 all the time to indicate that the PHY841F does not support 10M Half Duplex mode T2 10 100Base-T2 Capable Set to 0 all the time to indicate that the PHY841F does not support 100Base-T2. Res 9:7 Reserved Not Applicable SUPR 6 MF Preamble Suppression Capable This bit is hardwired to 1 indicating that the PHY841F accepts management frame without preamble. Minimum 32 preamble bits are required following power-on or hardware reset. One idle bit is required between any two management transactions as per IEEE 802.3u specification. AN_C 5 Auto Negotiation Complete If auto negotiation is enabled, this bit indicates whether the auto negotiation process has been completed or not. Set to 0 all the time when Fiber Mode is selected. 0B AN_C_0, Auto Negotiation process not completed 1B AN_C_1, Auto Negotiation process completed Data Sheet 53 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description RFD 4 ro Remote Fault Detect This bit is latched to 1 if the RF bit in the auto negotiation link partner ability register (bit 13, register address 05h) is set or the receive channel meets the far end fault indication function criteria. It is unlatched when this register is read. 0B RFD_0, Remote Fault not detected 1B RFD_1, Remote Fault detected ANEG 3 LINK 2 ro, llsc Link Status This bit reflects the current state of the link -test-fail state machine. Loss of a valid link causes a 0 latched into this bit. It remains 0 until this register is read by the serial management interface. Whenever Linkup, this bit should be read twice to get link up status 0B LINK_0, Link is down 1B LINK_1, Link is up JAB 1 ro, lhsc Jabber Detect 0B JAB_0, Jabber condition not detected 1B JAB_1, Jabber condition detected XTND 0 ro Extended Capability This bit defaults to 1, indicating that the PHY841F implements extended registers. 0B XTND_0, No extended register set 1B XTND_1, Extended register set Data Sheet Auto Negotiation Ability TP: This bit is set to 1 all the time, indicating that PHY841F is capable of auto negotiation. FX: This bit is set to 0 all the time, indicating that PHY841F is not capable of auto negotiation in Fiber Mode. 0B ANEG_0, Not capable of auto negotiation 1B ANEG_1, Capable of auto negotiation 54 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description PHY Identifier PHY_IR0 PHY Identifier Register 0 Offset 02H Reset Value 002EH 3+<,' UR Field Bits Type Description PHYID 15:0 ro PHY-ID IEEE Address PHY Identifier Register 1 PHY_IR1 PHY Identifier Register 1 Offset 03H Reset Value CC62H 3+<,' 02'(/ 5(9,' UR UR UR Field Bits Type Description PHYID 15:10 ro PHY-ID 15:0 IEEE Address/Model No./Rev. No. MODEL 9:4 MODEL 5:0 ADMTEK PHY Revision ID. REVID 3:0 REV-ID 3:0 ADMTEK PHY Revision ID. Data Sheet 55 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Advertisement Advertisement Auto Negotiation Advertisement Register Offset 04H Reset Value 01E1H 13 5HV 5) 5HV $3' 36( 7 7;) 7;' 7) 7' 6HO UZ UR UZ UR UZ UZ UR UZ UZ UZ UZ UR Field Bits Type Description NP 15 rw Next Page This bit is defaults to 1, indicating that PHY841F is next page capable. Res 14 ro Reserved Not Applicable RF 13 rw Remote Fault This bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. 0B NRFD, No remote fault has been detected 1B RFD, Remote Fault has been detected Res 12 ro Reserved Not Applicable APD 11 rw Asymmetric Pause Direction Bit[11:10] Capability 00B NP, No Pause 01B SP, Symmetric PAUSE 10B AP, Asymmetric PAUSE toward Link Partner 11B BSP, Both Symmetric PAUSE and Asymmetric PAUSE toward local device PSE 10 rw Pause Operation for Full Duplex Value on PAUREC will be stored in this bit during power on reset. T4 9 ro Technology Ability for 100Base-T4 Defaults to 0. Data Sheet 56 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description TXF 8 rw 100Base-TX Full Duplex 0B NCFDO, Not capable of 100M Full duplex operation 1B CFDO, Capable of 100M Full duplex operation TXD 7 100Base-TX Half Duplex 0B TXD_0, Not capable of 100M operation 1B TXD_1, Capable of 100M operation TF 6 10Base-T Full Duplex 0B TF_0, Not capable of 10M full duplex operation 1B TF_1, Capable of 10M Full Duplex operation TD 5 10Base-T Half Duplex 0B TD_0, Not capable of 10M operation 1B TD_1, Capable of 10M operation Sel 4:0 ro Selector Field These 5 bits are hardwired to 00001B, indicating that the PHY841F supports IEEE 802.3 CSMA/CD. Auto Negotiation Link Partner Ability ANLPA Auto Negotiation Link Partner Ability 13* $&. UR UR Data Sheet 5) UR Offset 05H 5HV /3$3 /33 /37$ 7;) UR UR UR UR Reset Value 01E1H 7;' 7) 7' 6HO UR UR UR UR UR 57 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description NPG 15 ro Next Page 0B NPG_0, Not capable of next page function 1B NPG_1, Capable of next page function ACK 14 Acknowledge 0B ACK_0, Not acknowledged 1B ACK_1, Link Partner acknowledges reception of the ability data word RF 13 Remote Fault 0B RF_0, No remote fault has been detected 1B RF_1, Remote Fault has been detected Res 12 Reserved Not Applicable LPAP 11 Link Partner Asymmetric Pause Direction LPP 10 Link Partner Pause Capability Value on PAUREC will be stored in this bit during power on reset. LPTA 9 Link Partner Technology Ability for 100Base-T4 Defaults to 0. TXF 8 100Base-TX Full Duplex 0B TXF_0, Not capable of 100M Full duplex operation 1B TXF_1, Capable of 100M Full duplex operation TXD 7 100Base-TX Half Duplex 1B TXD_1, Capable of 100M operation 0B TXD_2, Not capable of 100M operation TF 6 10Base-T Full Duplex 1B TF_1, Capable of 10M Full Duplex operation 0B TF_0, Not capable of 10M full duplex operation TD 5 10Base-T Half Duplex 1B TD_1, Capable of 10M operation 0B TD_0, Not capable of 10M operation Sel 4:0 Encoding Definitions Auto Negotiation Expansion Register ANER Auto Negotiation Expansion Register Offset 06H 5HV 3)/7 /313 1;3* 35&9 /3$1 UR Data Sheet Reset Value 0000H UROK 58 UR UR UROK UR Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description Res 15:5 ro Reserved Not Applicable PFLT 4 ro, lhsc Parallel Detection Fault 0B PFLT_0, No Fault Detect 1B PFLT_1, Fault has been detected LPNP 3 ro Link Partner Next Page Able 0B LPNP_0, Link Partner is not next page capable 1B LPNP_1, Link Partner is next page capable NXPG 2 PRCV 1 ro, lhsc Page Received 0B PRCV_0, No new page has been received 1B PRCV_1, A new page has been received LPAN 0 ro Link Partner Auto Negotiation Able 0B LPAN_0, Link Partner is not auto negotiable 1B LPAN_1, Link Partner is auto negotiable Next Page Able 1B NXPG_1, Next page Enable. 0B NXPG_0, Next page Disable Reserved 0 Res0 Reserved 0 Offset 07H Reset Value ReservedH 5HV UR Field Bits Type Description Res 15:0 ro Reserved Not Applicable Table 22 Reserved Registers Register Short Name Register Long Name Offset Address Res1 Reserved 1 08H Res2 Reserved 2 09H Res3 Reserved 3 0AH Res4 Reserved 4 0BH Res5 Reserved 5 0CH Res6 Reserved 6 0DH Data Sheet 59 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Table 22 Reserved Registers (cont’d) Register Short Name Register Long Name Offset Address Res7 Reserved 7 0EH Res8 Reserved 8 0FH Res9 Reserved 9 15H Res10 Reserved 10 1AH Res11 Reserved 11 1BH Res12 Reserved 12 1CH Res 13 Reserved 13 1EH Generic PHY Control/Configuration Register Note: PHY Control/Configuration Registers start from address 16 to 21. GPCR Generic PHY Control/Configuration Register ,)6(/ /%.0' 5HV UR UZ UR Offset 10H )/7 &RQY UZ UZ Reset Value 1000H 5HV ;29( 1 5HV UR UZ UZ (Q '30* UZ UZ Field Bits Type Description IFSEL 15:14 ro Interface Select. Value on RMII_EN and GPSI will be stored in IFSEL[1] and IFSEL[0], respectively 00B , MII 01B , GPSI 1xB , RMII LBKMD 13:12 rw Loop Back Mode Select. When 0.14 LPBK is set to 1, these two bits are set to 01 by default. Value on these two bits can be modified through MDC/MDIO. When 0.14 LPBK is set to 0, these two bits are reset to 00 and can't be updated by MDC/MDIO. Note: Both 10M and 100M loopback should be covered by AD2106. 00B 01B 10B 11B , Disable Loop back , PCS Layer Loop back mode , PMA Layer Loop back mode , PMD layer loop back mode Res 11:10 ro Reserved Not Applicable FLT 9 rw Enable called output remote fault status 0B FLT_0, Disable. 1B FLT_1, Enable. Data Sheet 60 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description Conv 8 rw Converter mode (only valid in rmii mode) 0B Conv_0, Normal Mode 1B Conv_1, converter mode Res 7:5 ro Reserved Not Applicable XOVEN 4 rw Cross Over Auto Detect Enable 0B XOVEN_0, Disable. 1B XOVEN_1, Enable. Res 3:2 rw ADMtek reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. En8 1 rw Enable Register 8 to Store Next Page Information. 0B En8_0, Store Next Page in Register 5. 1B En8_1, Store Next Page in Register 8 DPMG 0 rw Disable Power Management Feature 0B DPMG_0, Enable. Enable Medium Detect Function. 1B DPMG_1, Disable. Medium_On is high all the time. Data Sheet 61 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description PHY 10M Module Configuration Register P10_MCR PHY 10M Module Configuration Register 5HV 606 5HV UR UZ UZ Offset 11H 5HV ,7&( 5HV 5HV 5HV UZ UZ UZ UZ UZ Field Bits Type Description Res 15 ro Reserved Not Applicable Data Sheet Reset Value 0008H 62 $3' 5-0 UZ UZ 7-' 17+ )5/ UZ UZ UZ Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description SMS 14 rw 10BASE-T Serial Mode Select. Only available when AD2106 works in 10M mode. 0B SMS_0, 10M MII or RMII mode (According to RMII_EN) 1B SMS_1, 10M Serial Mode (Seven Wire Mode) Res 13 ADMtek reserved bits. Writing value other than 1 to this bit may cause abnormal operation. Res 12:11 ADMtek reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. ITCE 10 Polarity Interval Timer Check Enable. 0B ITCE_0, Disable 1B ITCE_1, Enable Res 9 ADMtek reserved bits. Writing value other than 1 to this bit may cause abnormal operation. Res 8:6 ADMtek reserved bits. Writing value other than 5 to these three bits may cause abnormal operation. Res 5 ADMtek reserved bits. Writing value other than 1 to this bit may cause abnormal operation. APD 4 Auto Polarity Disable 0B APD_0, Normal 1B APD_1, Disable RJM 3 Enable Receive Jabber Monitor 0B RJM_0, Disable 1B RJM_1, Enable TJD 2 Disable Transmit Jabber 0B TJD_0, Enable Transmit Jabber Function 1B TJD_1, Disable Transmit Jabber Function NTH 1 Normal Threshold 0B NTH_0, Lower 10BASE-T Receive threshold 1B NTH_1, Normal 10BASE-T Receive threshold FRL 0 Force 10M Receive Good Link. 0B FRL_0, Normal Operation 1B FRL_1, Force Good Link Data Sheet 63 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description PHY 100M Module Control Register P100_MCR PHY 100M Module Control Register Offset 12H Reset Value 0022H 5HV 5HV 5HV )[6H O 5HV UR UZ UZ UZ UZ 6&5 )(), UZ UZ &/( ,$& 5HV UR UZ UZ Field Bits Type Description Res 15:12 ro Reserved Not Applicable Res 11:10 rw ADMtek reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. Res 9:8 ADMtek reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. FxSel 7 Fiber Select. 0B SelFX_0, TP Mode 1B SelFX_1, Fiber Mode Res 6:5 ADMtek reserved bits. Writing value other than 0 to these two bits may cause abnormal operation. SCR 4 Disable Scrambler When set to fiber mode, this bit will be forced to 1 automatically. Write 0 to this bit in Fiber Mode has no effect. 0B SCR_0, Enable 1B SCR_1, Disable FEFI 3 Enable FEFI 0B FEFI_0, Disable 1B FEFI_1, Enable CLE 2 ro Disable cable length led indication When this bit is set to 0, SPDLED, COLLED and LNKACTLED are used to represent twisted pair cable length. See SPDLED description for more detail 0B CLE_0, Enable cable length led 1B CLE_1, Disable cable length led IAC 1 rw Interrupt active value control 0B IAC_0, Active low 1B IAC_1, Active high Res 0 Data Sheet ADMtek reserved bits. Writing value other than 0 to this bit may cause abnormal operation. 64 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description LED Configuration Register LCR LED Configuration Register Offset 13H Reset Value 0A34H 5HV /1.&75/ &2/&75/ 63'&75/ UR UR UR UR Field Bits Type Description Res 15:12 ro Reserved Not Applicable LNKCTRL 11:8 ro Link/Act LED Control 0000B, Collision 0001B, All Errors 0010B, Duplex 0011B, Duplex/Collision 0100B, Speed 0101B, Link 0110B, Transmit Activity 0111B, Receive Activity 1000B, TX/RX Activity 1001B, Link/Receive Activity 1010B, Link and TX/RX Activity 1011B, 100M False Carrier Error/10M Receive Jabber 1100B, 100M Error End of Stream/10M Transmit Jabber 1101B, Reserved 1110B, Distance (See LED Description for more detail) COLCTRL 7:4 ro COLLISION LED Control 0000B, Collision 0001B, All Errors 0010B, Duplex 0011B, Duplex/Collision 0100B, Speed 0101B, Link 0110B, Transmit Activity 0111B, Receive Activity 1000B, TX/RX Activity 1001B, Link/Receive Activity 1010B, Link and TX/RX Activity 1011B, 100M False Carrier Error/10M Receive Jabber 1100B, 100M Error End of Stream/10M Transmit Jabber 1101B, Reserved 1110B, Distance (See LED Description for more detail) Data Sheet 65 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description SPDCTRL 3:0 ro Speed LED Control 0000B, Collision 0001B, All Errors 0010B, Duplex 0011B, Duplex/Collision 0100B, Speed 0101B, Link 0110B, Transmit Activity 0111B, Receive Activity 1000B, TX/RX Activity 1001B, Link/Receive Activity 1010B, Link and TX/RX Activity 1011B, 100M False Carrier Error/10M Receive Jabber 1100B, 100M Error End of Stream/10M Transmit Jabber 1101B, Reserved 1110B, Distance (See LED Description for more detail) Data Sheet 66 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Interrupt Enable Register IER Interrupt Enable Register Offset 14H 5HV Reset Value 03FFH ;&+* 6&,( '&,( 35,( /6&( 6(,( )&$5 7-,( 5-,( ((6( UR UZ UZ UZ UZ UZ UZ UZ Field Bits Type Description Res 15:10 ro Reserved Not Applicable XCHG 9 rw Cross Over mode Changed Interrupt Enable 0B XCHG_0, Interrupt Disable 1B XCHG_1, Interrupt Enable SCIE 8 Speed Changed Interrupt Enable 0B SCIE_0, Interrupt Disable 1B SCIE_1, Interrupt Enable DCIE 7 Duplex Changed Interrupt Enable 0B DCIE_0, Interrupt Disable 1B DCIE_1, Interrupt Enable PRIE 6 Page Received Interrupt Enable 0B PRIE_0, Interrupt Disable 1B PRIE_1, Interrupt Enable LSCE 5 Link Status Changed Interrupt Enable 0B LSCE_0, Interrupt Disable 1B LSCE_1, Interrupt Enable SEIE 4 Symbol Error Interrupt Enable 0B SEIE_0, Interrupt Disable 1B SEIE_1, Interrupt Enable FCAR 3 False Carrier Interrupt Enable 0B FCAR_0, Interrupt Disable 1B FCAR_1, Interrupt Enable TJIE 2 Transmit Jabber Interrupt Enable 0B TJIE_0, Interrupt Disable 1B TJIE_1, Interrupt Enable RJIE 1 Receive Jabber Interrupt Enable 0B RJIE_0, Interrupt Disable 1B RJIE_1, Interrupt Enable EESE 0 Error End of Stream Enable 0B EESE_0, Interrupt Disable 1B EESE_1, Interrupt Enable Data Sheet 67 UZ UZ UZ Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description PHY Generic Status Register Note: PHY Status Registers start from 22 to 28 (29 to 30 reserves for further use) PGSR PHY Generic Status Register 5HV 5HV UR UR Offset 16H 0' );(1 UR UR Reset Value 0000H ;29( 5 &%/(1 UR UR Field Bits Type Description Res 15:14 ro Reserved Not Applicable Res 13:11 Reserved Not Applicable MD 10 Medium Detect Real Time Status for Medium Detect Signal. 0B MD_0, Medium_Detect Fail 1B MD_1, Medium_Detect Pass FXEN 9 Fiber Enable Only Changed when PHY Reset. OR’ed result of PI_SELFX and 17.9 (SELFX) 0B FXEN_0, TX mode 1B FXEN_1, FX mode XOVER 8 Cross Over Status 0B XOVS_0, MDI mode 1B XOVS_1, MDIX mode CBLEN 7:0 Cable Length. Only valid for 100M MSB is IC0 1aH , 40 meters 22H , 60 meters 94H , 80 meters 9aH , 100 meters a2H , 120 meters abH , 140 meters Data Sheet 68 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description PHY Specific Status Register PSSR PHY Specific Status Register Offset 17H 5HV -5; -7; UR UR UR 32/ 3287 3,1 UR Reset Value 0060H UR '83 UR 63' /,1. 53$8 5'83 563' 5$19 UR UR UR UR UR UR UR Field Bits Type Description Res 15:12 ro Reserved Not Applicable JRX 11 Real Time 10M Receive Jabber Status 0B JRX_0, No jabber 1B JRX_1, Jabber JTX 10 Real Time 10M Transmit Jabber Status 0B JTX_0, No Jabber 1B JTX_1, Jabber POL 9 Polarity Only available in 10M. 0B POL_0, Normal Polarity 1B POL_1, Polarity Reversed POUT 8 Pause Out Capability Disabled when Half Duplex. 0B POUT_0, Lack of Pause Out capability 1B POUT_1, Has Pause Out capability PIN 7 Pause In Capability Disabled when Half Duplex. 0B PIN_0, Has Pause In capability 1B PIN_1, Lack of Pause In capability DUP 6 Operating Duplex 0B DUP_0, Half Duplex 1B DUP_1, Full Duplex SPD 5 Operating Speed 0B SPD_0, 10Mb/s 1B SPD_1, 100Mb/s LINK 4 Real Time Link Status 0B LINK_0, Link Down 1B LINK_1, Link Up RPAU 3 Pause Recommend Value Only Changed when PHY Reset. This bit is disabled automatically when RDUP is 0. 0B RPAU_0, Pause Disable 1B RPAU_1, Pause Enable Data Sheet 69 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description RDUP 2 ro Duplex Recommended Value Only Changed when PHY Reset. 0B RDUP_0, Half Duplex 1B RDUP_1, Full Duplex RSPD 1 Speed Recommend Value Only Changed when PHY Reset. 0B RSPD_0, 10M 1B RSPD_1, 100M RANV 0 Recommended Auto Negotiation Value Only Changed when PHY Reset. PHY Recommend Value Status Register PRVSR PHY Recommend Value Status Register Offset 18H Reset Value 0000H 5HV 5$19 )6(/ 563' 5'83 35(& )()' ;295 ;296 56,, UR UR UR UR UR UR UR UR UR UR 3+<$ UR UR Bits Type Description Res 15 ro Reserved Not Applicable RANV 14 Auto Negotiation Recommend Value FSEL 13 Fiber Select Recommend Value RSPD 12 Speed Recommend Value 0B RSPD_1, 10M 1B RSPD_0, 100M RDUP 11 Duplex Recommend Value 0B RDUP_0, Half Duplex 1B RDUP_1, Full Duplex PREC 10 Pause Capability Recommend Value 0B PREC_0, Pause Disable 1B PREC_1, Pause Enable FEFD 9 Far End Fault Disable 0B FEFD_0, Enable 1B FEFD_1, Disable XOVR 8 Cross Over Capability Recommend Value 0B XOVR_0, Disable 1B XOVR_1, Enable XOVS 7 Cross Over Status 0B XOVS_0, Non-Cross Over 1B XOVS_1, Cross Over 70 50 Field Data Sheet Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description RSII 6 ro RMII_SMII Interface 0B RSll_0, Non RMII_SMII Interface 1B RSll_1, RMII or SMII Interface used RM 5 Repeater Mode Recommend Value 0B RM_0, NIC/SW 1B RM_1, Repeater PHYA 4:0 PHY Address Interrupt Status Register ISR Interrupt Status Register 5HV FRU Data Sheet Offset 19H Reset Value 0000H ;29& 63'& '83& 35(& /1.& 6(55 )&$5 7-$% 5-$% 675( FRU FRU FRU 71 FRU FRU FRU FRU FRU FRU FRU Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description Res 15:10 cor Reserved Not Applicable XOVC 9 Cross Over mode Changed 0B XOVC_0, Cross Over mode Not Changed 1B XOVC_1, Cross Over mode Changed SPDC 8 Speed Changed 0B SPDC_0, Speed Not Changed 1B SPDC_1, Speed Changed DUPC 7 Duplex Changed 0B DUPC_0, Duplex not changed 1B DUPC_1, Duplex Changed PREC 6 Page Received 0B PREC_0, Page not received 1B PREC_1, Page Received LNKC 5 Link Status Changed 0B LNKC_0, Link Status not Changed 1B LNKC_1, Link Status Changed SERR 4 Symbol Error 0B SERR_0, No symbol Error 1B SERR_1, Symbol Error FCAR 3 False Carrier Note: High whenever Link is Failed 0B 1B FCAR_0, No false carrier FCAR_1, False Carrier TJAB 2 Transmit Jabber 0B TJAB_0, No Jabber 1B TJAB_1, Jabber RJAB 1 Receive Jabber 0B RJAB_0, No Jabber 1B RJAB_1, Jabber STRE 0 Error End of Stream 0B STRE_0, No ESD Error 1B STRE_1, ESD Error Receive Error Counter Register RECR Receive Error Counter Register Offset 1DH Reset Value 0000H (5% UR Data Sheet 72 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Registers Description Field Bits Type Description ERB 15:0 ro Error Counter Includes. 1H 100MFC, 100M False Carrier 2H 100MSE, 100M Symbol Error 3H 10MTJ, 10M Transmit Jabber 4H 10MRJ, 10M Receive Jabber 5H ESS, Error Start of Stream 6H EES, Error End of Stream Chip ID Register CIR Chip ID Register Offset 1FH Reset Value 8125H &+,3,' UR Field Bits Type Description CHIPID 15:0 ro CHIPID 15:0 Data Sheet 73 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5 Electrical Characteristics 5.1 DC Characterization 5.1.1 Absolute Maximum Rating Table 23 Absolute Maximum Rating Parameter Symbol 3.3 V Power Supply VCC33 VCC25 VIN VOUT TSTG PC VESD 2.5 V Power Supply Input Voltage Output Voltage Storage Temperature Power Consumption ESD Rating Values Typ. Max. 3.0 – 3.6 V – 2.25 – 2.75 V – -0.3 – – -0.25 – VCC33 + 0.3 V VCC25 + 0.25 V -55 – 155 °C – – – 0.5 W – – – 2000 V – Unit Note / Test Condition Recommended Operating Conditions Table 24 Recommended Operating Conditions Symbol Power Supply Input Voltage Junction Operating Temperature 5.1.2.1 Note / Test Condition Min. 5.1.2 Parameter Unit VCC33 VIN Tj Values – Min. Typ. Max. 3.135 3.3 3.465 V – 0 – Vcc33 V – 0 25 115 °C – Unit Note / Test Condition DC Characteristics for 2.5 V Operation Under Vcc = 3.0 V ~3.6 V, Tj = 0°C ~ 115 °C Table 25 DC Characteristics for 2.5 V Operation Parameter Symbol VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input Pull-up/down Resistance RI Input Low Voltage Data Sheet Values Min. Typ. Max. – – 0.3 * Vcc V CMOS 0.7 * Vcc v – V CMOS – – 0.4 V CMOS 2.0 – – V CMOS – 75 – KΩ VIL = 0 V or VIH = Vcc33 74 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5.2 AC Characteristics 5.2.1 XI/OSCI (Crystal/Oscillator) Timing (In MII Mode) Figure 25 Crystal/Oscillator Timing Table 26 Crystal/Oscillator Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. tXI_PER 40.0 - 50 ppm 40.0 40.0 + 50 ppm ns – XI/OSCI Clock High tXI_HI 14 20.0 – ns – XI/OSCI Clock Low TX_ILO 14 20.0 – ns – XI/OSCI Clock Rise Time, VIL (max) to VIH (min.) tXI_RISE – – 4 ns – XI/OSCI Clock Fall Time, VIH (min.) to VIL (max) tXI_FALL – – 4 ns – XI/OSCI Clock Period 1) 1) Clock period less then 40ns - 50ppm or greater than 40ns + 50ppm may introduce peer receive CRC due to insufficient receive FIFO depth. Check peer receive FIFO description to confirm. Data Sheet 75 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5.3 RMII Timing 5.3.1 REFCLK Input Timing (XI in RMII Mode) t_IN50_PER t_IN50_HI t_IN50_LO VIH_RMII VIL_RMII t_IN50_RISE Figure 26 REFCLK Input Timing Table 27 REFCLK Input Timing Parameter t_IN50_FALL Symbol Values Unit Min. Typ. Max. Note / Test Condition REFCLK Clock Period tIN50_PER 20.0 - 50 ppm 20.0 20.0 ns + 50 ppm – REFCLK Clock High tIN50_HI tIN50_LO tIN50_RISE 8 10.0 – ns – 8 10.0 – ns – – – 2 ns – tIN50_FALL – – 2 ns – REFCLK Clock Low REFCLK Clock Rise Time, VIL (max) to VIH (min.) REFCLK Clock Fall Time, VIH (min.) to VIL (max) Data Sheet 76 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5.3.2 REFCLK Output Timing (CLKO50 in RMII Mode) t_OUT50_PER t_OUT50_HI t_OUT50_LO VIH_RMII VIL_RMII t_OUT50_RISE Figure 27 REFCLK Output Timing Table 28 REFCLK Output Timing Parameter t_OUT50_FALL Symbol Values Min. Typ. Max. Unit Note / Test Condition REFCLK Clock Period tOUT50_PER 20.0 - 50 ppm 20.0 20.0 + 50 ppm ns – REFCLK Clock High tOUT50_HI tOUT50_LO tOUT50_RISE 8 10.0 12 ns – 8 10.0 12 ns – – – 2 ns – REFCLK Clock Fall Time, VIH (min.) to VIL (max) tOUT50_FALL – – 2 ns – REFCLK Clock Jittering (p-p) tOUT50_JIT – 0.15 – ns v REFCLK Clock Low REFCLK Clock Rise Time, VIL (max) to VIH (min.) 5.3.3 Data Sheet RMII Transmit Timing 77 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics # $ % & Figure 28 RMII Transmit Timing Table 29 RMII Transmit Timing Parameter Symbol Unit Note / Test Condition Min. Typ. Max. TXD to REFCLK Rising Setup Time tRT_DSETUP 2 – – ns – TXD to REFCLK Rising Hold Time tRT_DHOLD 2 – – ns – TXEN asserts to data transmit to tRT_TXE2MH100 – medium – 235 ns – TXEN asserts to data transmit to tRT_TXE2MH10 medium – – 1550 ns – TXEN de-asserts to finish transmitting tRT_TXE2ML100 – – 260 ns – TXEN de-asserts to finish transmitting tRT_TXE2ML10 – 1250 ns – 5.3.4 Values – RMII Receive Timing !"# Figure 29 Data Sheet # % & ' RMII Receive Timing 78 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics Table 30 RMII Receive Timing Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Signal Detected on Medium to CRSDV High tRR_MH2CSH100 – – 265 ns – Signal Detected on Medium to CRSDV High tRR_MH2CSH10 – – 1000 ns – IDLE Detected on Medium to CRSDV low tRR_ML2CSL100 – – 260 ns – IDLE Detected on Medium to CRSDV low tRR_ML2CSL10 – – 570 ns – CRSDV High to Receive Data on RXD tRR_CSH2DAT100 – – 160 ns – CRSDV High to Receive Data on RXD tRR_CSH2DAT10 – – 1600 ns – CRSDV Toggle to End of Data tRR_CSL2DAT100 Receiving – 160 – ns – CRSDV Toggle to End of Data tRR_CSL2DAT10 Receiving – 1600 – ns – – – 5 ns – REFCLK Rising to RXD/CRSDV Delay Time tRR_DDLY 5.4 MII Timing 5.4.1 RXCLK Clock Timing t_RCK_PER t_RCK_HI t_RCK_LO VIH_MII RXCLK VIL_MII t_RCK_RISE Figure 30 Data Sheet t_RCK_FALL RXCLK Output Timing 79 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics Table 31 REFCLK Input Timing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. RXCLK Clock Period(100M) Note1) tRCK_PER100 40.0 40.0 40.0 ns + 50 ppm – RXCLK Clock Period(10M) Note2) tRCK_PER10 400.0 - 50 ppm 400.0 400.0 ns + 50 ppm – RXCLK Clock High (100M) tRCK_HI100 tRCK_HI10 tRCK_LO100 tRCK_LO10 tRCK_RISE 16 – 24 – – 200 – – 16 – 24 – 200 – – – 2 ns – RXCLK Clock Fall Time, VIH (min.) to VIL (max) tRCK_FALL – – 2 ns – REFCLK Clock Jittering (p-p) tRCK_JIT – 0.15 – ns – RXCLK Clock High (10M) RXCLK Clock Low (100M) RXCLK Clock Low (10M) RXCLK Clock Rise Time, VIL (max) to VIH (min.) - 50 ppm ns – – 1) Clock period ppm value is highly depended upon peer transmitter clock source skew. 2) Clock period ppm value is highly depended upon peer transmitter clock source skew. Data Sheet 80 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5.4.2 MII Receive Timing ˥˫˖˟˞ ˖˴̅̅˼˸̅ʳ˗˸̇˸˶̇ʳ ̂́ʳˠ˸˷˼̈̀ ̇˲ˠ˥˲ˠ˛˅˖˦˛ ̇˲ˠ˥˲ˠ˟˅˖˦˟ ˖˥˦ ̇˲ˠ˥˲ˠ˟˅˗˔˧ ̇˲ˠ˥˲ˠ˛˅˗˔˧ ˥˫˗˩ ˥˫˗ ̇˲ˠ˥˲˗˗˟ˬ ˃˃˃˃ ˃˃˃˃ Figure 31 MII Receive Timing Table 32 MII Receive Timing Parameter ˃˃˃˃ ˣ˥˘˔ˠ ˣ˥˘˔ˠ ˦˙˗ Symbol ˥˫˗ ˥˫˗ Values ˥˫˗ ˥˫˗ ˃˃˃˃ Unit Note / Test Condition 140 ns – – 1450 ns – Signal Detected on Medium to tMR_MH2DAT100 – RXDV High – 150 ns – Signal Detected on Medium to tMR_MH2DAT10 RXDV High – – 2300 ns – Min. Typ. Max. Signal Detected on Medium to tMR_MH2CSH100 – CRS High – Signal Detected on Medium to tMR_MH2CSH10 CRS High – RXCLK rising to Data Valid Delay Time tMR_DDLY100 10 – 25 ns – RXCLK rising to Data Valid Delay Time tMR_DDLY10 10 – 25 ns – IDLE Detected on Medium to CRS Low tMR_ML2CSL100 – – 120 ns – DLE Detected on Medium to CRS Low tMR_ML2CSL10 – – 235 ns – DLE Detected on Medium to RXDV Low tMR_ML2DAT100 – – 150 ns – DLE Detected on Medium to RXDV Low tMR_ML2DAT10 – 1450 ns – Data Sheet – 81 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics 5.4.3 TXCLK Output Timing t_TCK_PER t_TCK_HI t_TCK_LO VIH_MII TXCLK VIL_MII t_TCK_RISE Figure 32 TXCLK Output Timing Table 33 TXCLK Output Timing Parameter t_TCK_FALL Symbol Values Unit Min. Typ. Max. Note / Test Condition TXCLK Clock Period (100M) tTCK_PER100 40.0 - 50 ppm 40.0 40.0 ns + 50 ppm – TXCLK Clock Period (10M) tTCK_PER10 40.0 - 50 ppm 40.0 40.0 ns + 50 ppm – TXCLK Clock High (100M) tTCK_HI100 tTCK_HI10 tTCK_LO100 tTCK_LO10 tTCK_RISE 16 – 24 ns – 160 – 240 ns – 16 – 24 ns – 160 – 240 ns – – – 2 ns – TXCLK Clock Fall Time, VIH (min) to VIL (max) tTCK_FALL – – 2 ns – TXCLK Clock Jittering (p-p) tTCK_JIT – 0.15 – ns – TXCLK Clock High (10M) TXCLK Clock Low(100M) TXCLK Clock High (10M) TXCLK Clock Rise Time, VIL (max) to VIH (min) 5.4.4 Data Sheet MII Transmit Timing 82 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics ˧˫˖˟˞ ˧˫˘ˡ ˧˫˗ ̇˲ˠ˧˲˗˦˘˧˨ˣ ˃˃˃˃ ˣ˥˘˔ˠ ˣ˥˘˔ˠ ˦˙˗ ̇˲ˠ˧˲˗˛ˢ˟˗ ˧˫˗ ˧˫˗ ˧˫˗ ˧˫˗ ˧˫˗ ˃˃˃˃ ˃˃˃˃ ̇˲ˠ˧˲˧˫˘˅ˠ˟ ̇˲ˠ˧˲˧˫˘˅ˠ˛ ˗˔˧˔ʳ̂́ʳ ˠ˸˷˼̈̀ ̇˲ˠ˧˲˧˫˘˅˖˦˛ ̇˲ˠ˧˲˧˫˘˖˦˟ ˖˥˦ ʻ˛˴˿˹ʳ˗̈̃˿˸̋ʳˢ́˿̌ʼ Figure 33 MII Transmit Timing Table 34 MII Transmit Timing Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition TXD to TXCLK Rising Setup Time tMT_DSETUP 10 – 25 ns – TXD to TXCLK Rising Hold Time tMT_DHOLD 10 – 25 ns – TXEN asserts to data transmit to medium (100M) tMT_TXE2MH100 – – 75 ns – TXEN asserts to data transmit to medium (10M) tMT_TXE2MH10 – – 350 ns – TXEN asserts to CRS Assert (100M Half) tMT_TXE2CSH100 – – 15 ns – TXEN asserts to CRS Assert (10M Half) tMT_TXE2CSH10 – – 200 ns – TXEN de-asserts to finish transmitting (100M) tMT_TXE2ML100 – – 95 ns – TXEN de-asserts to finish transmitting (10M) tMT_TXE2ML10 – – 660 ns – TXEN de-asserts to CRS deasserts (100M) tMT_TXE2CSL100 – – 15 ns – TXEN de-asserts to CRS deasserts (10M) tMT_TXE2CSL10 – – 190 ns – 5.5 GPSI Timing 5.5.1 GPSI Receive Timing Data Sheet 83 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics ̇˲˚ˣ˦˜˲˥˖˞˲ˣ˘˥ ̇˲˚ˣ˦˜˲˥˖˞˲˛˜ ̇˲˚ˣ˦˜˲˥˖˞˲˟ˢ ˥˫˖˟˞ ˖˴̅̅˼˸̅ʳ˗˸̇˸˶̇ʳ ̂́ʳˠ˸˷˼̈̀ ̇˲˚˥˲ˠ˛˅˖˦˛ ̇˲˚˥˲ˠ˟˅˖˦˟ ˖˥˦ ̇˲˚˥˲ˠ˛˅˗˔˧ ˥˫˗ ˃ ˃ ˃ Figure 34 GPSI Receive Timing Table 35 GPSI Receive Timing ̇˲˚˥˲˗˗˟ˬ ˣ˥˘˔ˠ ˣ˥˘˔ˠ Parameter Symbol 10M Receive Clock Period tGPSI_RCK_PE 100.0 ˦˙˗ ˥˫˗ ˥˫˗ Values Min. ˥˫˗ ˥˫˗ Unit Note / Test Condition Typ. Max. 100.0 100.0 ns + 50 ppm – 10M Receive Clock High – – ns – 10M Receive Clock Low – – ns – – 1500 ns – - 50 ppm R tGSPI_RCK_HI 40 tGSPI_RCK_LO 40 Signal Detected on Medium to tGR_MH2CSH – ˃ CRS High Signal Detected on Medium to Data Valid tGR_MH2DAT – – 1600 ns – RXCLK rising to Data Valid Delay Time tGR_DDLY 40 – 60 ns – IDLE Detected on Medium to CRS Low tGR_ML2CSL – – 230 ns – 5.5.2 GPSI Transmit Timing ̇˲˚ˣ˦˜˲˧˖˞˲ˣ˘˥ ̇˲˚ˣ˦˜˲˧˖˞˲˛˜ ̇˲˚ˣ˦˜˲˧˖˞˲˟ˢ ˧˫˖˟˞ ˧˫˘ˡ ˧˫˗ ̇˲˚˧˲˗˦˘˧˨ˣ ˃ ˣ˥˘˔ˠ ˣ˥˘˔ˠ ˦˙˗ ̇˲˚˧˲˗˛ˢ˟˗ ˧˫˗ ˧˫˗ ˧˫˗ ˧˫˗ ˧˫˗ ˃ ˃ ̇˲˚˧˲˧˫˘˅ˠ˟ ̇˲˚˧˲˧˫˘˅ˠ˛ ˗˔˧˔ʳ̂́ʳ ˠ˸˷˼̈̀ ̇˲˚˧˲˧˫˘˅˖˦˛ ̇˲˚˧˲˧˫˘˖˦˟ ˖˥˦ ʻ˛˴˿˹ʳ˗̈̃˿˸̋ʳˢ́˿̌ʼ Figure 35 Data Sheet GPSI Transmit Timing 84 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics Table 36 GPSI Transmit Timing Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. 100.0 100.0 ns + 50 ppm – tGSPI_TCK_HI 40 tGSPI_TCK_LO 40 tGT_DSETUP 40 – – ns – – – ns – – – ns – TXD to TXCLK Rising Hold Time tGT_DHOLD 40 – – ns – TXEN asserts to data transmit to medium tGT_TXE2MH – – 150 ns – TXEN asserts to CRS Assert (Half) tGT_TXE2CSH – – 10 ns – TXEN de-asserts to finish transmitting tGT_TXE2ML – – 900 ns – TXEN de-asserts to CRS deasserts tGT_TXECSL – – 10 ns – tGPSI_TCK_PE 100.0 10M Transmit Clock Period - 50 ppm R 10M Transmit Clock High 10M Transmit Clock Low TXD to TXCLK Rising Setup Time 5.6 Serial Management Interface (MDC/MDIO) Timing t_MDC_LO t_MDC_PER t_MDC_HI MDC t_MDIO_DLY MDIO(Output) MDC t_MDIO_SETUP t_MDIO_HOLD MDIO(Input) Figure 36 Serial Management Interface (MDC/MDIO) Timing Table 37 Serial Management Interface (MDC/MDIO) Timing Parameter MDC Period MDC High Data Sheet Symbol tMDC_PER tMDC_HI Values Unit Note / Test Condition Min. Typ. Max. 100 – – ns – 40 – – ns – 85 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Electrical Characteristics Table 37 Serial Management Interface (MDC/MDIO) Timing (cont’d) Parameter Symbol Values tMDC_LO MDC to MDIO Delay Time tMDIO_DLY MDIO Input to MDC Setup Time tMDIO_SETUP MDIO Input to MDC Hold Time tMDIO_HOLD MDC Low 5.7 Unit Note / Test Condition Min. Typ. Max. 40 – – ns – – – 20 ns – 10 – – ns – 10 – – ns – Power On Configuration Timing VCC3IN t_V33_V25 VCC25OUT t_V25_RST t_RST_PW RESET# XI/OSCI t_PL_DSETUP t_PL_DHOLD PWR ON LATCH Figure 37 Power On Configuration Timing Table 38 Power On Configuration Timing Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition 3.3V Power Good to 2.5 V Power Good tV33_V25 TBD – – ms – Hardware Reset With Device Powered up tV25_RST 200 – – ms – Hardware Reset With Clock Running tRST_PW 800 – – ns – Reset High to Configuration Setup Time tPL_DSETUP 200 – – ns – Reset High to Configuration Hold Time tPL_DHOLD 0 – – ns – Data Sheet 86 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Packaging 6 Packaging ADM7001/X, Low Profile Quad Flat Package (LQFP) 48 Pin Figure 38 Data Sheet ADM7001/X,Low Profile Quad Flat Package (LQFP) 87 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Packaging Table 39 Dimensions for 100 Pin LQFP Package Symbol Millimeter (mm) Inch Min. Typ. Max. Min. Typ. Max. A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.005 0.057 D 9.00 BSC. 0.354 BSC. D1 7.00 BSC 0.276 BSC. E 9.00 BSC 0.354 BSC. E1 7.00 BSC 0.276 BSC. R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – Θ 0° 3.5° 7° 0° 3.5° 7° Θ1 0° – – 0° – – Θ2 11° 12° 13° 11° 12° 13° Θ3 11° 12° 13° 11° 12° 13° c 0.09 – 0.20 0.004 – 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 S 1.00 Ref. 0.20 – 0.039 Ref. – 0.008 – – 0.012 0.014 0.018 32L b 0.30 0.35 0.45 e 0.80 BSC. 0.031 BSC. D2 5.60 0.220 E2 5.60 0.220 Tolerance of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.10 0.003 ddd 0.20 0.008 44L b 0.17 0.20 0.27 0.007 0.008 e 0.50 BSC. 0.020 BSC. D2 5.00 0197 E2 5.00 0.197 0.011 Tolerance of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 48L b Data Sheet 0.17 0.20 0.27 88 0.007 0.008 0.011 Rev. 1.07, 2005-11-25 ADM7001/X Data sheet Packaging Table 39 Dimensions for 100 Pin LQFP Package (cont’d) Symbol Millimeter (mm) Inch e 0.50 BSC. 0.020 BSC. D2 5.50 0.217 E2 5.50 0.217 Tolerance of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 Data Sheet 89 Rev. 1.07, 2005-11-25 www.infineon.com Published by Infineon Technologies AG
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