Qseven-Spec_2.0_SGET_errata_sheet_E2.00

Qseven-Spec_2.0_SGET_errata_sheet_E2.00
Qseven® Specification
Errata Sheet for Version 2.0,
dated September 20, 2012
Version E2.0-001, July 02, 2013
Note
Please ensure to follow all available Errata Sheets of the current Version of your
Specification or Design Guide
Qseven Spec V2.0 Errata Sheet
Page 2 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Erratum 001 - New pin assignment for pin 154
applies to Qseven Specification Version.2.0 dated September 20, 2012
Motivation
Different Chip set Vendors feature different implementations of the Graphics, e.g. Display
port (DP) is currently not supported on ARM Systems. With the change from Qseven Spec
1.2 to 2.0 pin 154 was changed from Display Port Hot Plug Detect (DP_HPD#) to
reserved.
Change Overview
1. Set back to old Status DP_HPD# for use in future releases as HDMI Detect Pin to
support HDMI/DP++ adapters on releases beyond Qseven Spec 2.0
Remarks
There might be compatibility issues between V1.x and V2.x
Please note updated Table 3-1 in appendix A after Erratum 002
Qseven Spec V2.0 Errata Sheet
Page 3 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Erratum 002 - Changes to support USB-OTG
applies to Qseven Specification Version.2.00 dated September 20, 2012
Motivation
The existing Qseven specification 2.0 does not fully implement USB-OTG (USB On-TheGo). The following changes will add full OTG capability to the Rev 2.0 specification.
Furthermore the description of the USB_ID pin has been corrected. It is (and should have
been) defined as a resistance to ground, i.e. an analog pin which needs to be directly
connected to external sensing circuitry and not as formerly described as a 3.3V CMOS
signal level (this could damage module components!).
The changes are described in the following sections
Change Overview
1. Introduction of a new signal on the Qseven connector for Power enable
(USB_DRIVE_VBUS (pin 56)
2. Redefinition of the USB_CC signal to USB_VBUS (pin 91)
3. Update pin technology of the USB_ID signal from 3.3V CMOS Open Drain to
Analog
Remarks
Further changes/additions might be necessary depending on the relevant chipsets.
Please refer to the appropriate USB-OTG documentation from your module vendor and
check for compatibility with your 1.0/1.2 implementations.
Please note updated tables 3-7 and 3-1 in the appendices A and B
Qseven Spec V2.0 Errata Sheet
Page 4 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Erratum 003 - Changes in HD Audio / AC97 Signal description
applies to Qseven Specification Version.2.00 dated September 20, 2012
Motivation
There are Errors in the current description of pins/signals of the HD Audio interface which
need to be corrected.
The changes are described in the following sections
Change Overview
1. Change Signal flow direction on pin 59 (HDA_SYNC / AC97_SYNC / I2S_WS) from
O (Output) to I/O (Input/Output bidirectional) for I2S Signal only.
2. Change Signal name signal on the Qseven connector for pin 63 from
HDA_BITCLK / I2S_CLK to
HDA_BCLK / AC97_BCLK / I2S_CLK
3. Change Signal flow direction on this pin 63 from
O (Output) to I/O (Input/Output bidirectional) for I2S Signal only.
4. Change Signal description on this pin 63 from
“HD Audio/AC97 24MHz Serial Bit Clock
Multiplexed with I2S Serial data Clock” to
“HD Audio Serial Bit Clock.
AC97 Serial Bit Clock.
Multiplexed with I2S Serial data Clock”
5. Add AC97 Signal name instances for pins 59, 61, 65, 67
6. Change name of Chapter 3.1.7 from
High Definition Audio Signals/AC'97 to
High Definition Audio Signals/AC'97/I²S
7. Change name of Table 3-9 from
Signal Definition HDA/AC'97 to
Signal Definition HDA/AC'97/I²S
8. Add missing AC97 instances to table 3-9
Remarks
Depending on setup pins 59to 67 (odd numbers) can be used for
HD Audio (HDA), AC97 or I²S signals.
There is no specific Frequency required for the Bit clock. (3)
Please note updated tables 3-9 and 3-1 in the appendices B and C
Qseven Spec V2.0 Errata Sheet
Page 5 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Appendix A to Errata 001 and 002Changes in Signal definitions
Table 3-7 (partial) old Signal Definition USB
Signal
Description
I/O Type
I OL /I IL
I/O
USB_ID
USB ID pin.
CMOS
Configures the mode of the USB Port 1. If the signal is
3.3V Suspend
detected as being 'high active' the BIOS will automatically
configure USB Port 1 as USB Client and enable USB Client
support. This signal should be driven as OC signal by
external circuitry.
I
USB_CC
USB Client Connect pin.
CMOS
If USB Port 1 is configured for client mode then an
3.3V Suspend
externally connected USB host should set this signal to
high-active in order to properly make the connection with
the module's internal USB client controller. If the external
USB host is disconnected, this signal should be set to
low-active in order to inform the USB client controller that
the external host has been disconnected.
A level shifter/protection circuitry should be implemented on
the carrier board for this signal.
I
to be replaced by Table 3-7 (partial) new Signal Definition USB
Signal
Description
I/O Type
USB_ID
(pin #92)
USB ID pin.
Configures the mode of the USB Port 1.
Please refer to the Qseven Design guide and to your
module vendor's documentation for further details.
Analog
O
USB_VBUS
(former USB_CC,
pin #91)
USB VBUS pin.
•
5V tolerant
•
VBUS resistance has to be placed on the module
•
VBUS capacitance has to be placed on the carrier
board
Passive
Analog, 5.0V
I
CMOS 3.3V
O
USB_DRIVE_VBUS USB Power enable pin for USB Port 1
Enables the Power for the USB-OTG port on the carrier
(new, former RSV
pin #56,)
board.
Qseven Spec V2.0 Errata Sheet
Page 6 of 10
I OL /I IL
I/O
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Appendix B to Erratum 003Changes in Audio Signal definitions
Table 3-9 old
Table 3-9 Signal Definition HDA/AC97
Signal
Description
I/O Type
IOL/IIL
I/O
HDA_RST#
I2S_RST#
HD Audio/AC'97 Codec Reset.
Multiplexed with I2S Codec Reset.
CMOS 3.3V
O
HDA_SYNC
I2S_WS
Serial Bus Synchronization.
Multiplexed with I2S Word Select from Codec.
CMOS 3.3V
O
HDA_BCLK
I2S_CLK
HD Audio/AC'97 24 MHz Serial Bit Clock from Codec.
Multiplexed with I2S Serial Data Clock from Codec.
CMOS 3.3V
O
HDA_SDO
I2S_SDO
HD Audio/AC'97 Serial Data Output to Codec.
Multiplexed with I2S Serial Data Output from Codec.
CMOS 3.3V
O
HDA_SDI
I2S_SDI
HD Audio/AC'97 Serial Data Input from Codec.
Multiplexed with I2S Serial Data Input from Codec.
CMOS 3.3V
I
to be replaced by Table 3-9 new
Table 3-9 Signal Definition HDA/AC97/I²S
Signal
Description
I/O Type
HDA_RST#
AC97_RST#
I2S_RST#
HD Audio Codec Reset.
AC'97 Codec Reset.
Multiplexed with I2S Codec Reset.
CMOS 3.3V
O
O
O
HDA_SYNC
AC97_SYNC
I2S_WS
Serial Bus Synchronization.
Serial Bus Synchronization.
Multiplexed with I2S Word Select.
CMOS 3.3V
O
O
I/O
HDA_BCLK
AC97_BCLK
I2S_CLK
HD Audio Serial Bit Clock.
AC'97 Serial Bit Clock.
Multiplexed with I2S Serial data Clock.
CMOS 3.3V
O
O
I/O
HDA_SDO
AC97_SDO
I2S_SDO
HD Audio Serial Data Output.
AC'97 Serial Data Output.
Multiplexed with I2S Serial Data Output.
CMOS 3.3V
O
O
O
HDA_SDI
AC97_SDI
I2S_SDI
HD Audio Serial Data Input.
AC'97 Serial Data Input.
Multiplexed with I2S Serial Data Input.
CMOS 3.3V
I
I
I
Qseven Spec V2.0 Errata Sheet
Page 7 of 10
IOL/IIL
I/O
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Appendix C to Errata 001, 002 and 003Changes in Pinout Description
Table 3-1 Connector Pinout Description
Old Description
to be replaced by
New Description
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
3
5
GND
GBE_MDI3GBE_MDI3+
2
4
6
GND
GBE_MDI2GBE_MDI2+
1
3
5
GND
GBE_MDI3GBE_MDI3+
2
4
6
GND
GBE_MDI2GBE_MDI2+
7
9
11
GBE_LINK100#
GBE_MDI1GBE_MDI1+
8
10
12
GBE_LINK1000#
GBE_MDI0GBE_MDI0+
7
9
11
GBE_LINK100#
GBE_MDI1GBE_MDI1+
8
10
12
GBE_LINK1000#
GBE_MDI0GBE_MDI0+
13
15
GBE_LINK#
GBE_CTREF
14
16
GBE_ACT#
SUS_S5#
13
15
GBE_LINK#
GBE_CTREF
14
16
GBE_ACT#
SUS_S5#
17
19
21
WAKE#
SUS_STAT#
SLP_BTN#
18
20
22
SUS_S3#
PWRBTN#
LID_BTN#
17
19
21
WAKE#
SUS_STAT#
SLP_BTN#
18
20
22
SUS_S3#
PWRBTN#
LID_BTN#
23
24
25
GND
KEY
GND
24
26
GND
KEY
PWGIN
23
25
GND
KEY
GND
26
GND
KEY
PWGIN
27
29
BATLOW#
SATA0_TX+
28
30
RSTBTN#
SATA1_TX+
27
29
BATLOW#
SATA0_TX+
28
30
RSTBTN#
SATA1_TX+
31
33
35
SATA0_TXSATA_ACT#
SATA0_RX+
32
34
36
SATA1_TXGND
SATA1_RX+
31
33
35
SATA0_TXSATA_ACT#
SATA0_RX+
32
34
36
SATA1_TXGND
SATA1_RX+
37
39
41
38
40
42
SATA1_RXGND
SDIO_CLK#
37
39
41
SATA1_RXGND
SDIO_CLK#
44
SDIO_LED
43
SATA0_RXGND
BIOS_DISABLE# /
BOOT_ALT#
SDIO_CD#
38
40
42
43
SATA0_RXGND
BIOS_DISABLE# /
BOOT_ALT#
SDIO_CD#
44
SDIO_LED
45
47
49
SDIO_CMD
SDIO_PWR#
SDIO_DAT0
46
48
50
SDIO_WP
SDIO_DAT1
SDIO_DAT3
45
47
49
SDIO_CMD
SDIO_PWR#
SDIO_DAT0
46
48
50
SDIO_WP
SDIO_DAT1
SDIO_DAT3
51
53
SDIO_DAT2
SDIO_DAT4
52
54
SDIO_DAT5
SDIO_DAT7
51
53
SDIO_DAT2
SDIO_DAT4
52
54
SDIO_DAT5
SDIO_DAT7
RSVD
GND
55
SDIO_DAT6
56
57
GND
58
USB_DRIVE_VBUS
GND
55
SDIO_DAT6
56
57
GND
58
59
HDA_SYNC / I2S_WS 60
SMB_CLK /
GP1_I2C_CLK
59
HDA_SYNC /
AC97_SYNC /
I2S_WS
60
SMB_CLK /
GP1_I2C_CLK
61
HDA_RST# /
I2S_RST#
62
SMB_DAT /
GP1_I2C_DAT
61
HDA_RST# /
AC97_RST# /
I2S_RST#
62
SMB_DAT /
GP1_I2C_DAT
63
HDA_BITCLK /
I2S_CLK
64
SMB_ALERT#
63
HDA_BCLK /
AC97_BCLK /
I2S_CLK
64
SMB_ALERT#
65
HDA_SDI / I2S_SDI
66
GP0_I2C_CLK
65
HDA_SDI /
AC97_SDI /
I2S_SDI
66
GP0_I2C_CLK
67
HDA_SDO / I2S_SDO 68
GP0_I2C_DAT
67
HDA_SDO /
AC97_SDO /
I2S_SDO
68
GP0_I2C_DAT
69
71
73
THRM#
THRMTRIP#
GND
WDTRIG#
WDOUT
GND
69
71
73
THRM#
THRMTRIP#
GND
70
72
74
WDTRIG#
WDOUT
GND
70
72
74
Qseven Spec V2.0 Errata Sheet
Page 8 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
75
USB_P7- /
USB_SSTX0USB_P7+ /
USB_SSTX0+
76
USB_P6- /
USB_SSRX0USB_P6+ /
USB_SSRX0+
75
USB_P7- /
USB_SSTX0USB_P7+ /
USB_SSTX0+
76
USB_P6- /
USB_SSRX0USB_P6+ /
USB_SSRX0+
77
79
81
83
85
87
USB_6_7_OC#
USB_P5- /
USB_SSTX1USB_P5+ /
USB_SSTX1+
USB_2_3_OC#
USB_P3-
78
80
82
77
79
81
86
88
USB_4_5_OC#
USB_P4- /
USB_SSRX1USB_P4+ /
USB_SSRX1+
USB_0_1_OC#
USB_P2-
84
83
85
87
78
USB_6_7_OC#
USB_P5- /
USB_SSTX1USB_P5+ /
USB_SSTX1+
USB_2_3_OC#
USB_P3-
80
82
86
88
USB_4_5_OC#
USB_P4- /
USB_SSRX1USB_P4+ /
USB_SSRX1+
USB_0_1_OC#
USB_P2-
84
89
91
USB_P3+
90
92
USB_P2+
USB_ID
89
91
USB_P3+
USB_CC
USB_VBUS
90
92
USB_P2+
USB_ID
93
95
USB_P1USB_P1+
94
96
USB_P0USB_P0+
93
95
USB_P1USB_P1+
94
96
USB_P0USB_P0+
97
99
GND
eDP0_TX0+ /
LVDS_A0+
eDP0_TX0- /
LVDS_A0-
98
100
GND
eDP1_TX0+ /
LVDS_B0+
eDP1_TX0- /
LVDS_B0-
97
99
GND
eDP0_TX0+ /
LVDS_A0+
eDP0_TX0- /
LVDS_A0-
98
100
GND
eDP1_TX0+ /
LVDS_B0+
eDP1_TX0- /
LVDS_B0-
103
eDP0_TX1+ /
LVDS_A1+
104
eDP1_TX1+ /
LVDS_B1+
103
eDP0_TX1+ /
LVDS_A1+
104
eDP1_TX1+ /
LVDS_B1+
105
eDP0_TX1- /
LVDS_A1-
106
eDP1_TX1- /
LVDS_B1-
105
eDP0_TX1- /
LVDS_A1-
106
eDP1_TX1- /
LVDS_B1-
107
eDP0_TX2+ /
LVDS_A2+
eDP0_TX2- /
LVDS_A2LVDS_PPEN
108
eDP1_TX2+ /
LVDS_B2+
eDP1_TX2- /
LVDS_B2LVDS_BLEN
107
eDP0_TX2+ /
LVDS_A2+
eDP0_TX2- /
LVDS_A2LVDS_PPEN
108
eDP1_TX2+ /
LVDS_B2+
eDP1_TX2- /
LVDS_B2LVDS_BLEN
101
109
111
102
110
112
101
109
111
102
110
112
113
eDP0_TX3+ /
LVDS_A3+
114
eDP1_TX3+ /
LVDS_B3+
113
eDP0_TX3+ /
LVDS_A3+
114
eDP1_TX3+ /
LVDS_B3+
115
eDP0_TX3- /
LVDS_A3GND
116
eDP1_TX3- /
LVDS_B3GND
115
eDP0_TX3- /
LVDS_A3GND
116
eDP1_TX3- /
LVDS_B3GND
117
118
117
118
119
eDP0_AUX+ /
LVDS_A_CLK+
120
eDP1_AUX+ /
LVDS_B_CLK+
119
eDP0_AUX+ /
LVDS_A_CLK+
120
eDP1_AUX+ /
LVDS_B_CLK+
121
eDP0_AUX- /
LVDS_A_CLK-
122
eDP1_AUX- /
LVDS_B_CLK-
121
eDP0_AUX- /
LVDS_A_CLK-
122
eDP1_AUX- /
LVDS_B_CLK-
123
LVDS_BLT_CTRL
/GP_PWM_OUT0
GP2_I2C_DAT /
LVDS_DID_DAT
GP2_I2C_CLK /
LVDS_DID_CLK
CAN0_TX
124
GP_1-Wire_Bus
123
124
GP_1-Wire_Bus
126
eDP0_HPD# /
LVDS_BLC_DAT
eDP1_HPD# /
LVDS_BLC_CLK
CAN0_RX
125
LVDS_BLT_CTRL
/GP_PWM_OUT0
GP2_I2C_DAT /
LVDS_DID_DAT
GP2_I2C_CLK /
LVDS_DID_CLK
CAN0_TX
126
eDP0_HPD# /
LVDS_BLC_DAT
eDP1_HPD# /
LVDS_BLC_CLK
CAN0_RX
125
127
129
131
130
129
136
136
DP_LANE1+ /
TMDS_LANE1+
138
DP_AUX+
137
DP_LANE1+ /
TMDS_LANE1+
138
DP_AUX+
139
DP_LANE1- /
TMDS_LANE1GND
140
DP_AUX-
139
DP_LANE1- /
TMDS_LANE1GND
140
DP_AUX-
141
133
135
DP_LANE3+ /
TMDS_CLK+
DP_LANE3- /
TMDS_CLKGND
130
137
134
131
128
RSVD (Differential
Pair)
RSVD (Differential
Pair)
GND
135
132
127
RSVD (Differential
Pair)
RSVD (Differential
Pair)
GND
133
DP_LANE3+ /
TMDS_CLK+
DP_LANE3- /
TMDS_CLKGND
128
132
134
142
GND
141
142
GND
143
DP_LANE2+ /
TMDS_LANE0+
144
RSVD (Differential
Pair)
143
DP_LANE2+ /
TMDS_LANE0+
144
RSVD (Differential
Pair)
145
DP_LANE2- /
TMDS_LANE0-
146
RSVD (Differential
Pair)
145
DP_LANE2- /
TMDS_LANE0-
146
RSVD (Differential
Pair)
147
149
GND
DP_LANE0+ /
148
150
GND
HDMI_CTRL_DAT
147
149
GND
DP_LANE0+ /
148
150
GND
HDMI_CTRL_DAT
Qseven Spec V2.0 Errata Sheet
Page 9 of 10
Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
Pin
Signal
Pin
Signal
Pin
153
TMDS_LANE2+
DP_LANE0- /
TMDS_LANE2DP_HDMI_HPD#
154
RSVD
155
PCIE_CLK_REF+
156
PCIE_WAKE#
157
159
161
PCIE_CLK_REFGND
PCIE3_TX+
158
160
162
163
165
167
PCIE3_TXGND
PCIE2_TX+
169
171
Signal
Pin
Signal
152
HDMI_CTRL_CLK
153
TMDS_LANE2+
DP_LANE0- /
TMDS_LANE2DP_HDMI_HPD#
154
DP_HPD#
155
PCIE_CLK_REF+
156
PCIE_WAKE#
PCIE_RST#
GND
PCIE3_RX+
157
159
161
PCIE_CLK_REFGND
PCIE3_TX+
158
160
162
PCIE_RST#
GND
PCIE3_RX+
164
166
168
PCIE3_RXGND
PCIE2_RX+
163
165
167
PCIE3_TXGND
PCIE2_TX+
164
166
168
PCIE3_RXGND
PCIE2_RX+
PCIE2_TXUART0_TX
170
172
PCIE2_RXUART0_RTS#
169
171
PCIE2_TXUART0_TX
170
172
PCIE2_RXUART0_RTS#
173
175
177
PCIE1_TX+
PCIE1_TXUART0_RX
174
176
178
PCIE1_RX+
PCIE1_RXUART0_CTS#
173
175
177
PCIE1_TX+
PCIE1_TXUART0_RX
174
176
178
PCIE1_RX+
PCIE1_RXUART0_CTS#
179
181
183
PCIE0_TX+
PCIE0_TXGND
180
182
184
PCIE0_RX+
PCIE0_RXGND
179
181
183
PCIE0_TX+
PCIE0_TXGND
180
182
184
PCIE0_RX+
PCIE0_RXGND
185
187
LPC_AD0 / GPIO0
LPC_AD2 / GPIO2
186
188
LPC_AD1 / GPIO1
LPC_AD3 / GPIO3
185
187
LPC_AD0 / GPIO0
LPC_AD2 / GPIO2
186
188
LPC_AD1 / GPIO1
LPC_AD3 / GPIO3
189
LPC_CLK / GPIO4
190
189
LPC_CLK / GPIO4
190
191
SERIRQ / GPIO6
192
LPC_FRAME# /
GPIO5
LPC_LDRQ# / GPIO7
191
SERIRQ / GPIO6
192
LPC_FRAME# /
GPIO5
LPC_LDRQ# / GPIO7
193
VCC_RTC
194
SPKR /
GP_PW M_OUT2
193
VCC_RTC
194
SPKR /
GP_PWM_OUT2
195
FAN_TACHOIN /
GP_TIMER_IN
196
FAN_PWMOUT /
GP_PW M_OUT1
195
FAN_TACHOIN /
GP_TIMER_IN
196
FAN_PWMOUT /
GP_PWM_OUT1
197
199
201
GND
SPI_MOSI
SPI_MISO
198
200
202
GND
SPI_CS0#
SPI_CS1#
197
199
201
GND
SPI_MOSI
SPI_MISO
198
200
202
GND
SPI_CS0#
SPI_CS1#
203
205
207
SPI_SCK
VCC_5V_SB
MFG_NC0
204
206
208
MFG_NC4
VCC_5V_SB
MFG_NC2
203
205
207
SPI_SCK
VCC_5V_SB
MFG_NC0
204
206
208
MFG_NC4
VCC_5V_SB
MFG_NC2
209
211
MFG_NC1
VCC
210
212
MFG_NC3
VCC
209
211
MFG_NC1
VCC
210
212
MFG_NC3
VCC
213
215
217
VCC
VCC
VCC
214
216
218
VCC
VCC
VCC
213
215
217
VCC
VCC
VCC
214
216
218
VCC
VCC
VCC
219
221
223
VCC
VCC
VCC
220
222
224
VCC
VCC
VCC
219
221
223
VCC
VCC
VCC
220
222
224
VCC
VCC
VCC
225
227
VCC
VCC
226
228
VCC
VCC
225
227
VCC
VCC
226
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HDMI_CTRL_CLK
Qseven Spec V2.0 Errata Sheet
Page 10 of 10
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Version E2.0-001, July 02, 2013 © 2013 SGeT e.V.
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