datasheet for VL491T2863T

datasheet for VL491T2863T
Product Specifications
PART NO:
VL491T2863T-E7/E6/D5/CC
REV: 1.3
General Information
1GB 128Mx72 DDR2 SDRAM ECC UNBUFFERED SO-CDIMM 200-PIN WITH THERMAL SENSOR
Description:
The VL491T2863T is a 128Mx72 DDR2 SDRAM high density SO-CDIMM. This memory module consists of
nine CMOS 128Mx8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages, a zero delay PLL clock
in BGA package, and a 2K EEPROM with built-in thermal sensor in 8-pin TSSOP package. This module is a
200-pin dual in-line memory module and is intended for mounting into an edge connector socket. Decoupling
capacitors are mounted on the printed circuit board for each DDR2 SDRAM.
Features
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200-pin, small-outline dual in-line memory module (SO-CDIMM)
JEDEC pin out
Fast data transfer rates: PC2-6400, PC2-5300, PC2-4200, & PC2-3200
Supports ECC error detection and correction
VDD = VDDQ = 1.8V
VDDSPD = 3.0V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18 compatible)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
Four-bit pre-fetch architecture
DLL aligns DQ and DQS transition with CK
Programmable CAS# latency (CL): 6 (DDR2-800), 5 (DDR2-667),
4 (DDR2-533), 3 (DDR2-400)
Write latency = Read latency - 1tCK
Eight internal component banks for concurrent operation
Programmable burst; length (4, 8)
Adjustable data-output drive strength
On-die termination (ODT)
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM built-in thermal sensor
Thermal sensor range: -200C to +125 0C (+/- 10C accuracy)
Gold edge contacts
Lead-free RoHS
PCB: Height 30.00mm (1.181”), double sided components
Order Information :
VL491T2863T-E6 S
DRAM MANUFACTURER
S - SAMSUNG
M - MICRON
MODULE SPEED
E7: PC2-6400 @ CL6
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
Pin Name
Function
A0~A13
Address Inputs
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
CB0 ~ C B7
Check Bits
DQS0~DQS8
Data Strobes
DQS0#~DQS8#
Data Strobes Complement
ODT0
On-die Termination Control
CK,CK#
Clock Input
C KE0
Clock Enables
C S 0#
Chip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
RESET#
Register Reset Input
DM0~DM8
Data Masks
VD D
Voltage Supply 1.8V +/- 0.1V
A10/AP
Address Input/Auto Precharge
VD D SPD
SPD Voltage Supply 3.0V to 3.6V
VSS
Ground
SA0~SA1
SPD Address
SD A
SPD Data Input/Output
SC L
SPD Clock Input
EVENT#
Temperature Sensor Alarm Output
VREF
SSTL_18 Reference Voltage
NC
No Connect
REV./ THERMAL SENSOR (OPTION)
T - WITH THERMAL SENSOR
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
Pin Configuration
200-PIN DDR2 SO-CDIMM FRONT
200-PIN DDR2 SO-CDIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQ18
101
VD D
15 1
VSS
2
VSS
52
VSS
102
A6
152
VSS
3
DQ0
53
DQ19
103
A5
153
DQS5#
4
DQ4
54
DQ28
104
A4
154
DM5
5
VSS
55
VSS
105
A3
155
DQS5
6
DQ5
56
DQ29
106
VD D
156
VSS
7
DQ1
57
DQ24
107
A2
157
VSS
8
VSS
58
VSS
108
A1
158
DQ46
9
DQS0#
59
DQ25
109
VD D
159
DQ42
10
DM0
60
DM3
110
A0
160
DQ47
11
DQS0
61
VSS
111
A10/AP
161
DQ43
12
VSS
62
VSS
112
BA1
162
VSS
13
VSS
63
DSQ3#
113
BA0
163
VSS
14
DQ6
64
DQ30
114
VD D
164
DQ52
15
DQ2
65
DSQ3
115
RAS#
165
DQ48
16
DQ7
66
DQ31
116
WE#
166
DQ53
17
DQ3
67
VSS
117
VD D
167
DQ49
18
VSS
68
VSS
118
C S 0#
168
VSS
19
VSS
69
DQ26
119
C AS#
169
VSS
20
DQ12
70
C B4
120
ODT0
170
DM6
21
DQ8
71
DQ27
121
NC/
C S 1#
171
DQS6#
22
DQ13
72
C B5
122
A 13
172
VSS
23
DQ9
73
VSS
123
VD D
173
DQS6
24
VSS
74
VSS
124
VD D
174
DQ54
25
VSS
75
C B0
125
NC/
ODT1
175
VSS
26
DM1
76
DM8
126
CK
176
DQ55
27
DQS1#
77
C B1
127
NC/
C S 3#
177
DQ50
28
VSS
78
VSS
128
CK#
178
VSS
29
DSQ1
79
VSS
129
DQ32
179
DQ51
30
DQ14
80
C B6
130
VSS
180
DQ60
31
VSS
81
DQS8#
131
VSS
181
VSS
32
DQ15
82
C B7
132
DQ36
182
DQ61
33
DQ10
83
DQS8
133
DQ33
183
DQ56
34
VSS
84
VSS
134
DQ37
184
VSS
35
DQ11
85
VSS
135
DQS4#
185
DQ57
36
DQ20
86
C B2
136
VSS
186
DM7
37
VSS
87
C KE0
137
DQS4
187
VSS
38
DQ21
88
C B3
138
DM4
188
DQ62
39
DQ16
89
NC/
C KE1
139
VSS
189
DQS7#
40
VSS
90
VSS
140
VSS
190
VSS
41
DQ17
91
EVENT#
141
DQ34
191
DQS7
42
RESET#
92
BA2
142
DQ38
192
DQ63
43
VSS
93
VD D
143
DQ35
193
DQ58
44
DM2
94
NC
144
DQ39
194
SD A
45
DQS2#
95
A 12
145
VSS
195
VSS
46
VSS
96
A11
146
VSS
196
SC L
47
DQS2
97
A9
147
DQ40
197
DQ59
48
DQ22
98
VD D
148
DQ44
198
SA1
49
VSS
99
A7
149
DQ41
199
VD D SPD
50
DQ23
100
A8
150
DQ45
200
SA0
Note: 1. NC/CS2#, NC/CS3# (pins 91, 127) are used for 4 rank module
2. NC/CS1# (pin 121), NC/CKE1 (pin 89), NC/ODT1 (pin 125) are used for 2 rank module
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
Functional Block Diagram
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1#
DM1
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5#
DM5
DM/
RDQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6#
DM6
DQS2
DQS2#
DM2
DM/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3#
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D6
DQS7
DQS7#
DM7
DM/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/
RDQS
CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D7
VDDSPD
DQS8
DQS8#
DM8
Serial PD
SCL
DM/
RDQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SDA
EVT A0
CS# DQS DQS#
EVENT#
D8
A1
SA0 SA1
A2
Serial PD
VDD/ VDDQ
VREF
VSS
SA2
D0-D8
D0-D8
D0-D8
Notes:
Unless otherwise noted, resistor values are 22 Ohms – 5%
> CS0#: SDRAMs D0-D8
> BA0-BA2: SDRAMs D0-D8
> A0-A13: SDRAMs D0-D8
> RAS#: SDRAMs D0-D8
> CAS# : SDRAMs D0-D8
> WE# : SDRAMs D0-D8
> CKE0 :SDRAMs D0-D8
> ODT0: SDRAMs D0-D8
CK
CK#
P
L
L
PCK0, PCK4-PCK6, PCK9 -> CK: SDRAMs D0-D8
PCK0#,PCK4#-PCK6#,PCK9# -> CK#: SDRAMs D0-D8
OE
RESET#
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
0
C
0
85
0
C
Command/Address,
RAS#, CAS#, WE#, BA
-45
45
uA
C S #, C K E
-45
45
C K, C K#
-10
10
uA
DM
-5
5
uA
DQ, DQS, DQS#
-5
5
uA
-18
18
uA
VIN, VOUT
TSTG
Device operating temperature
TCASE
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disabled
IOZ
IVREF
VREF leakage current; VREF = Valid VREF level
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
VDD
1.7
1.8
1.9
V
1
I/O Supply voltage
VDDQ
1.7
1.8
1.9
V
4
VDDL Supply voltage
VDDL
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
Operating Temperature Condition
Parameter
Operating temperature
Symbol
Rating
TOPER
0 to 85
Units
Notes
C
1,2
0
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85°C < TC <= 95°C
In p u t DC L o g ic L ev el
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
VIH(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage DDR2-667 & DDR2-800
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VIL(AC)
-
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667 & DDR2-800
VIL(AC)
-
VREF - 0.200
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Input capacitance (A0~A13, BA0~BA2, RAS#,CAS#,WE#)
Input capacitance (CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK, CK#)
Input capacitance (DM0 ~ DM8)
Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS8)
Symbol
Min
Max
Unit
CIN1 (E7)
13
19.75
pF
CIN1 (E6,D5,CC)
13
22
pF
CIN2 (E7)
13
19.75
pF
CIN2 (E6,D5,CC)
13
22
pF
CIN3 (E7)
13
19.75
pF
CIN3 (E6,D5,CC)
13
22
pF
CIN4
6
7
pF
CIN5 (E6,E7)
6.5
7.5
pF
CIN5 (D5,CC)
6.5
8
pF
COUT1 (E6,E7)
6.5
7.5
pF
COUT1 (D5,CC)
6.5
8
pF
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
IDD Specification
Condition
Symbol
E7
E6
D5
CC
(DDR2-800) (DDR2-667) (DDR2-533) (DDR2-400)
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0
1010
965
920
875
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1
1100
1055
1010
965
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P
335
335
335
335
mA
P r ec h ar g e q u i et s t an d b y c u r r en t ;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q
560
560
560
515
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N
650
605
605
560
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
560
560
515
515
mA
IDD3P
362
362
362
362
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N
785
740
740
695
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W
1505
1370
1280
1145
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R
1595
1460
1370
1235
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5
1595
1550
1550
1505
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6
135
135
135
135
mA
IDD7
2540
2360
2360
2225
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note:
IDD specification is based on Samsung D-die components. Other DRAM Manufacturers specification may be different.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
AC Timming Parameters & Specifications
Parameter
Clock
Data
E7
E6
D5
CC
(DDR2-800)
(DDR2-667)
(DDR2-533)
(DDR2-400)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
CL=6
tCK (6)
2500
8000
-
-
-
-
-
-
ps
CL=5
tCK (5)
3000
8000
3000
8000
3,750
8,000
-
-
ps
CL=4
tCK (4)
3750
8000
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK (3)
-
-
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-100
100
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
-400
400
-450
+450
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
DQ and DM input setup time relative to DQS
tDS
50
100
100
150
DQ and DM input hold time relative to DQS
tDH
125
175
225
275
DQ and DM input pulse width (for each input)
tDIPW
0.35
0.35
0.35
0.35
Data hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-350
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
DQS write preamble setup time
tWPRES
0
0
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock cycle time
Data Strobe
Symbol
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
300
350
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MIN)
340
-400
200
+400
MIN
(tCH,tCL)
tAC (MAX)
tAC (MIN)
400
-450
240
tCK
450
+450
-500
300
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
ps
+500
ps
ps
350
ps
0.9
1.1
tCK
0.4
0.6
tCK
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
AC Timming Parameters & Specifications ( cont')
Parameter
Command and Address
Self Refresh
E6
D5
CC
(DDR2-667)
(DDR2-533)
(DDR2-400)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tIPW
0.6
0.6
0.6
0.6
tCK
Address and control input setup time
tIS
175
200
250
350
ps
tIH
250
275
375
475
ps
CAS# to CAS# command delay
tCCD
2
2
2
2
ps
ACTIVE to ACTIVE (same bank) command
tRC
60
60
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
12.5
15
15
15
ns
Four Bank Activate period
tFAW
37.5
ACTIVE to PRECHARGE command
tRAS
45
Internal READ to precharge command delay
tRTP
7.5
7.5
7.5
7.5
ns
Write recovery time
tWR
15
15
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READcommand delay
tWTR
10
7.5
7.5
10
ns
PRECHARGE command period
tRP
15
15
15
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
2
2
2
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
tRFC
127.5
REFRESH to Active or Refresh to Refresh
command interval
37.5
70,000
70,000
45
127.5
7.8
37.5
70,000
70,000
45
127.5
7.8
37.5
70,000
70,000
40
127.5
7.8
ns
70,000
ns
70,000
ns
7.8
us
Average periodic refresh interval
tREFI
Exit self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exit self refresh to READ
tXSRD
200
200
200
200
tCK
Exit self refresh timing reference
tISXR
tIS
tIS
tIS
tIS
ps
ODT turn-on delay
tAOND
2
2
2
2
2
2
2
2
tCK
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
ps
ODT turn-on
tAON
tAC(MIN)
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off
ODT
E7
(DDR2-800)
Address and control input pulse width for each
input
Address and control input hold time
Power-Down
Symbol
ODT turn-on (power-down mode)
ODT to power-down entry latency
tANPD
3
3
3
3
tCK
ODT power-down exit latency
tAXPD
10
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
8-AL
7-AL
6-AL
6-AL
tCK
Exit precharge power-down to any non-READ
command.
tXP
2
2
2
2
tCK
CKE minimum high/low time
tCKE
3
3
3
3
tCK
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
Product Specifications
VL491T2863T-E7/E6/D5/CC
PART NO:
REV: 1.3
Package Dimensions
FRONT VIEW
3.40
MAX
67.60
4.00 +/- 0.10 (2X)
30.00
2.00 +/- 0.10 (2X)
20.00 TYP
+
1.80 D (2X)
10.00 TYP
6.00 TYP
1.00 TYP
1.00 +/- 0.10
0.45 TYP
1.00 TYP
2.00 TYP
PIN 1
0.60 TYP
PIN 199
63.60
TYP
BACK VIEW
+
+
4.00 +/- 0.10
2.70
PIN 200
4.20 TYP
47.40
TYP
TYP
PIN 2
11.40
TYP
NOTE:
All dimensions are in millimeters with tolerance +/- 0.13mm unless otherwise specified.
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL491T2863T-E7/E6/D5/CC
Revision History:
Date
Rev.
P ag e
C h an g es
10/30/2007
1.0
All
Released spec
11/15/2007
1.1
All
Added speed E7 (D D R2-800)
03/17/2009
1.2
All
Update data sheet
12/21/2010
1.3
All
Update data sheet
Virtium Technology, Inc. 30052Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.3
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