null  null
PIC16C63A/65B/73B/74B
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
• PIC16C73B
• PIC16C65B
• PIC16C74B
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 200 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit multichannel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI
and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide with
external RD, WR and CS controls
• Brown-out detection circuitry for Brown-out Reset
(BOR)
PIC16CXX Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power-saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Automotive
temperature ranges
• Low-power consumption:
- < 5 mA @ 5V, 4 MHz
- 23 µA typical @ 3V, 32 kHz
- < 3 µA typical standby current
Devices
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
I/O
Pins
22
33
22
33
A/D
Chan.
5
8
 1999 Microchip Technology Inc.
Pin Diagram:
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
PSP
Interrupts
No
Yes
No
Yes
10
11
11
12
Preliminary
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C65B
PIC16C74B
• PIC16C63A
PIC16C7X Peripheral Features:
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
DS30605B-page 1
PIC16C63A/65B/73B/74B
SDIP, SOIC, SSOP, Windowed CERDIP
27
3
26
4
25
5
6
7
8
9
10
24
23
22
21
20
19
11
18
12
17
13
16
14
15
MQFP
TQFP
PIC16C65B
PIC16C74B
39
38
37
36
35
34
33
32
31
30
29
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
1
2
3
4
5
6
7
8
9
10
11
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
Key Features
PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023)
PIC16C65B
PIC16C74B
12
13
14
15
16
17
18
19
20
21
22
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
PLCC
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
28
2
PIC16C63A
PIC16C73B
•1
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Program Memory (EPROM) x 14
4K
4K
4K
4K
Data Memory (Bytes) x 8
192
192
192
192
Pins
28
40
28
40
Parallel Slave Port
—
Yes
—
Yes
Capture/Compare/PWM Modules
2
2
2
2
Timer Modules
3
3
3
3
A/D Channels
—
—
5
8
SPI/I2C, USART
SPI/I2C, USART
SPI/I2C, USART
SPI/I2C, USART
Serial Communication
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
Yes
Yes
Yes
Interrupt Sources
Packages
DS30605B-page 2
10
11
11
12
28-pin SDIP, SOIC,
SSOP, Windowed
Cerdip
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed Cerdip
28-pin SDIP, SOIC,
SSOP, Windowed
Cerdip
40-pin PDIP;
44-pin PLCC,
MQFP, TQFP,
Windowed Cerdip
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Table of Contents
1.0 General Description ...................................................................................................................................................................... 5
2.0 PIC16C63A/65B/73B/74B Device Varieties .................................................................................................................................. 7
3.0 Architectural Overview .................................................................................................................................................................. 9
4.0 Memory Organization.................................................................................................................................................................. 15
5.0 I/O Ports...................................................................................................................................................................................... 29
6.0 Timer0 Module ............................................................................................................................................................................ 39
7.0 Timer1 Module ............................................................................................................................................................................ 43
8.0 Timer2 Module ............................................................................................................................................................................ 47
9.0 Capture/Compare/PWM ModuleS .............................................................................................................................................. 49
10.0 Synchronous Serial Port (SSP) Module...................................................................................................................................... 55
11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..................................................................................... 67
12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79
13.0 Special Features of the CPU ...................................................................................................................................................... 85
14.0 Instruction Set Summary............................................................................................................................................................. 99
15.0 Development Support ............................................................................................................................................................... 107
16.0 Electrical Characteristics........................................................................................................................................................... 113
17.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 137
18.0 Packaging Information .............................................................................................................................................................. 139
Appendix A: Revision History ........................................................................................................................................................ 151
Appendix B: Device Differences..................................................................................................................................................... 151
Appendix C: DEVICE MIGRATIONS - PIC16C63/65A/73A/74A → PIC16C63A/65B/73B/74B ..................................................... 152
Appendix D: Migration from Baseline to Midrange Devices ........................................................................................................... 154
On-Line Support................................................................................................................................................................................. 161
Reader Response .............................................................................................................................................................................. 162
Product Identification System ............................................................................................................................................................ 163
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
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Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
• E-mail us at [email protected]
We appreciate your assistance in making this a better document.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 3
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 4
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
1.0
GENERAL DESCRIPTION
The PIC16C63A/65B/73B/74B devices are low-cost,
high-performance, CMOS, fully-static, 8 bit microcontrollers in the PIC16CXX mid-range family.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
The PIC16C63A/73B devices have 22 I/O pins. The
PIC16C65B/74B devices have 33 I/O pins. Each
device has 192 bytes of RAM. In addition, several
peripheral features are available including: three timer/
counters, two Capture/Compare/PWM modules and
two serial ports. The Synchronous Serial Port (SSP)
can be configured as either a 3-wire Serial Peripheral
Interface (SPI) or the two-wire Inter-Integrated Circuit
(I 2C) bus. The Universal Synchronous Asynchronous
Receiver Transmitter (USART) is also known as the
Serial Communications Interface or SCI. Also, a 5channel high-speed 8-bit A/D is provided on the
PIC16C73B, while the PIC16C74B offers 8 channels.
The 8-bit resolution is ideally suited for applications
requiring low-cost analog interface, e.g., thermostat
control, pressure sensing, etc.
The PIC16C63A/65B/73B/74B devices have special
features to reduce external components, thus reducing
cost, enhancing system reliability and reducing power
consumption. There are four oscillator options, of which
the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption,
XT is a standard crystal, and the HS is for high speed
crystals. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake up the chip
from SLEEP through several external and internal
interrupts and resets.
 1999 Microchip Technology Inc.
A highly reliable Watchdog Timer (WDT), with its own
on-chip RC oscillator, provides protection against software lock-up, and also provides one way of waking the
device from SLEEP.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume.
The PIC16C63A/65B/73B/74B devices fit nicely in many
applications ranging from security and remote sensors
to appliance control and automotive. The EPROM technology makes customization of application programs
(transmitter codes, motor speeds, receiver frequencies,
etc.) extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for all
applications with space limitations. Low cost, low power,
high performance, ease of use and I/O flexibility make
the PIC16C63A/65B/73B/74B devices very versatile,
even in areas where no microcontroller use has been
considered before (e.g., timer functions, serial communication, capture and compare, PWM functions and
coprocessor applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).
1.2
Development Support
PICmicro® devices are supported by the complete line
of Microchip Development tools.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
Preliminary
DS30605B-page 5
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 6
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.0
PIC16C63A/65B/73B/74B
DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C63A/65B/73B/74B
Product Identification System section at the end of this
data sheet. When placing orders, please use that page
of the data sheet to specify the correct part number.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1.
2.
2.1
C, as in PIC16C74. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC16LC74. These devices have
EPROM type memory and operate over an
extended voltage range.
UV Erasable Devices
The UV erasable version, offered in windowed CERDIP
packages, is optimal for prototype development and
pilot programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C63A/65B/73B/74B.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 7
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 8
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture in which program and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, most instructions
execute in a single cycle (200 ns @ 20 MHz) except for
program branches.
All devices covered by this datasheet contain 4K x 14-bit
program memory and 192 x 8-bit data memory.
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function registers, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 9
PIC16C63A/65B/73B/74B
FIGURE 3-1:
PIC16C63A/65B/73B/74B BLOCK DIAGRAM
13
8
Data Bus
Program Counter
PORTA
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF(2)
RA4/T0CKI
RA5/SS/AN4(2)
EPROM
Program
Memory
Program
Bus
RAM
File
Registers
8 Level Stack
(13-bit)
14
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
RB0/INT
Indirect
Addr
8
RB7:RB1
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Brown-out
Reset
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MUX
ALU
Power-on
Reset
8
PORTD(3)
W reg
RD7/PSP7:RD0/PSP0(3)
Parallel Slave Port
MCLR
PORTC
PORTE(3)
(3)
VDD, VSS
RE0/RD/AN5(2, 3)
RE1/WR/AN6(2, 3)
Timer0
Timer1
Timer2
A/D(2)
CCP1
CCP2
Synchronous
Serial Port
USART
RE2/CS/AN7(2, 3)
Note 1: Higher order bits are from the STATUS register.
2: A/D is not available on the PIC16C63A/65B.
3: PSP and Ports D and E are not available on PIC16C63A/73B.
DS30605B-page 10
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-1:
PIC16C63A/73B PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
OSC1/CLKIN
9
9
I
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP
1
1
I/P
ST
Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
RA0/AN0(4)
2
2
I/O
TTL
RA0 can also be analog input 0(4)
(4)
3
3
I/O
TTL
RA1 can also be analog input 1(4)
4
4
I/O
TTL
RA2 can also be analog input 2(4)
5
5
I/O
TTL
RA3 can also be analog input 3 or analog reference
voltage(4)
RA4/T0CKI
6
6
I/O
ST
RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4(4)
7
7
I/O
TTL
RA5 can also be analog input 4(4) or the slave select for
the synchronous serial port.
Pin Name
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA1/AN1
RA2/AN2(4)
RA3/AN3/VREF
(4)
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
21
21
I/O
TTL/ST(1)
RB1
22
22
I/O
TTL
RB2
23
23
I/O
TTL
RB3
24
24
I/O
TTL
RB4
25
25
I/O
TTL
RB5
26
26
I/O
TTL
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
(2)
Interrupt on change pin. Serial programming clock.
RB6
27
27
I/O
TTL/ST
RB7
28
28
I/O
TTL/ST(2)
RC0/T1OSO/T1CKI
11
11
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2
12
12
I/O
ST
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1
13
13
I/O
ST
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL
14
14
I/O
ST
RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA
15
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
17
17
I/O
ST
RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
VSS
8, 19
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
20
P
—
Positive supply for logic and I/O pins.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
Legend: I = input
Note 1:
2:
3:
4:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
A/D module is not available in the PIC16C63A.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 11
PIC16C63A/65B/73B/74B
TABLE 3-2:
PIC16C65B/74B PINOUT DESCRIPTION
TQFP
I/O/P
MQFP
Type
Pin#
Buffer
Type
DIP
Pin#
PLCC
Pin#
OSC1/CLKIN
13
14
30
I
OSC2/CLKOUT
14
15
31
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
Pin Name
Description
ST/CMOS(4) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA0/AN0(5)
2
3
19
I/O
TTL
RA0 can also be analog input 0(5)
(5)
RA1/AN1
3
4
20
I/O
TTL
RA1 can also be analog input 1(5)
RA2/AN2(5)
4
5
21
I/O
TTL
RA2 can also be analog input 2(5)
RA3/AN3/VREF(5)
5
6
22
I/O
TTL
RA3 can also be analog input 3 or analog reference
voltage(5)
RA4/T0CKI
6
7
23
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4(5)
7
8
24
I/O
TTL
RA5 can also be analog input 4(5) or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
8
I/O
TTL/ST(1)
37
9
I/O
TTL
38
10
I/O
TTL
36
39
11
I/O
TTL
37
41
14
I/O
TTL
Interrupt on change pin.
RB5
38
42
15
I/O
TTL
Interrupt on change pin.
RB6
39
43
16
I/O
TTL/ST(2)
I/O
(2)
RB0/INT
33
36
RB1
34
RB2
35
RB3
RB4
RB7
40
44
17
TTL/ST
RB0 can also be the external interrupt pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
Legend: I = input
Note 1:
2:
3:
4:
5:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the parallel
slave port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
A/D is not available on the PIC16C65B.
DS30605B-page 12
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 3-2:
PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED)
TQFP
I/O/P
MQFP
Type
Pin#
Buffer
Type
Pin Name
DIP
Pin#
PLCC
Pin#
RC0/T1OSO/T1CKI
15
16
32
I/O
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2
16
18
35
I/O
ST
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1
17
19
36
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
18
20
37
I/O
ST
RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA
23
25
42
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
24
26
43
I/O
ST
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
25
27
44
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Description
PORTC is a bi-directional I/O port.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
19
21
38
I/O
ST/TTL(3)
RD1/PSP1
20
22
39
I/O
ST/TTL(3)
RD2/PSP2
21
23
40
I/O
ST/TTL(3)
RD3/PSP3
22
24
41
I/O
ST/TTL(3)
RD4/PSP4
27
30
2
I/O
ST/TTL(3)
RD5/PSP5
28
31
3
I/O
ST/TTL(3)
RD6/PSP6
29
32
4
I/O
ST/TTL(3)
RD7/PSP7
30
33
5
I/O
ST/TTL(3)
RE0 can also be read control for the parallel slave port,
or analog input 5(5).
PORTE is a bi-directional I/O port.
(5)
8
9
25
I/O
ST/TTL(3)
RE1/WR/AN6(5)
9
10
26
I/O
ST/TTL(3)
RE1 can also be write control for the parallel slave port,
or analog input 6(5).
RE2/CS/AN7(5)
10
11
27
I/O
ST/TTL(3)
RE2 can also be select control for the parallel slave
port, or analog input 7(5).
RE0/RD/AN5
VSS
12,31
13,34
6,29
P
—
Ground reference for logic and I/O pins.
VDD
11,32
12,35
7,28
P
—
Positive supply for logic and I/O pins.
NC
—
1,17,28,
40
12,13,
33,34
—
These pins are not internally connected. These pins should
be left unconnected.
Legend: I = input
Note 1:
2:
3:
4:
5:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the parallel
slave port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
A/D is not available on the PIC16C65B.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 13
PIC16C63A/65B/73B/74B
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely, Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Internal
phase
clock
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
Note:
PC+2
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS30605B-page 14
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.0
MEMORY ORGANIZATION
4.2
4.1
Program Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this datasheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1:
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL,RETURN
RETFIE,RETLW
RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
Note:
13
4.2.1
Stack Level 1
Data Memory Organization
Maintain the IRP and RP1 bits clear in
these devices.
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indirectly through the File Select Register (FSR)
(Section 4.5).
User Memory
Space
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
On-chip Program
Memory (Page 1)
0800h
0FFFh
1000h
1FFFh
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 15
PIC16C63A/65B/73B/74B
FIGURE 4-2:
REGISTER FILE MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
4.2.2
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES(3)
ADCON0(3)
General
Purpose
Register
INDF(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1(3)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
General
Purpose
Register
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read
as ’0’.
Note 1:
2:
3:
Not a physical register.
These registers are not implemented on the
PIC16C63A/73B, read as '0'.
These registers are not implemented on the
PIC16C63A/65B, read as '0'.
DS30605B-page 16
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
resets(3)
Bank 0
00h
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
(4)
PCL
03h
STATUS(4)
04h
FSR(4)
05h
PORTA
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
(5)
PORTD Data Latch when written: PORTD pins when read
08h
PORTD
09h
PORTE(5)
0Ah
PCLATH(1,4)
—
—
—
0Bh
INTCON(4)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
ADIF(6)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
—
—
–
—
—
—
CCP2IF
---- ---0 ---- ---0
—
PSPIF
—
(5)
—
—
—
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
—
—
—
T1CKPS1
T1CKPS0 T1OSCEN
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
T1SYNC
TMR1CS
TMR1ON --00 0000 --uu uuuu
Timer2 module’s register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
SPEN
RX9
SREN
CREN
—
FERR
OERR
CCP1M0 --00 0000 --00 0000
RX9D
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register2 (MSB)
1Dh
CCP2CON
1Eh
ADRES(6)
1Fh
ADCON0(6)
—
—
xxxx xxxx uuuu uuuu
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CHS2
CHS1
CHS0
GO/DONE
—
CCP2M0 --00 0000 --00 0000
A/D Result Register
ADCS1
ADCS0
0000 -00x 0000 -00x
xxxx xxxx uuuu uuuu
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) resets include external reset through MCLR and watchdog timer reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 17
PIC16C63A/65B/73B/74B
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
resets(3)
Bank 1
80h
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register)
81h
OPTION_REG
82h
PCL(4)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
83h
STATUS
84h
FSR(4)
(4)
IRP
(2)
(2)
RP1
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
TRISD(5)
PORTD Data Direction Register
1111 1111 1111 1111
89h
TRISE
(5)
8Ah
PCLATH(1,4)
(4)
IBF
OBF
IBOV
—
—
—
PSPMODE
—
--11 1111 --11 1111
PORTE Data Direction Bits
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(5)
ADIE(6)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
—
91h
—
Unimplemented
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
94h
SSPSTAT
—
—
1111 1111 1111 1111
D/A
P
0000 0000 0000 0000
S
R/W
UA
BF
--00 0000 --00 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
—
Unimplemented
—
—
97h
TXEN
SYNC
TRMT
TX9D
99h
SPBRG
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
ADCON1
TX9
BRGH
TXSTA
9Fh
CSRC
—
98h
Baud Rate Generator Register
(6)
—
—
—
0000 -010 0000 -010
0000 0000 0000 0000
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) resets include external reset through MCLR and watchdog timer reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
DS30605B-page 18
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.1
STATUS REGISTER
It is recommended that only BCF, BSF, SWAPF and
MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, C or DC bits
in the STATUS register. For other instructions which do
not affect status bits, see the "Instruction Set Summary."
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>), maintain these bits
clear to ensure upward compatibility with
future products.
2: The C and DC bits operate as borrow and
digit borrow bits, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
REGISTER 4-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C(2)
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
IRP(1): Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1(1):RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C(2): Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note 1: Maintain the IRP and RP1 bits clear.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF,RLF) instructions, this bit is loaded with either the high or low order bit
of the source register.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 19
PIC16C63A/65B/73B/74B
4.2.2.2
OPTION REGISTER
Note:
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the watchdog timer.
REGISTER 4-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS30605B-page 20
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 21
PIC16C63A/65B/73B/74B
4.2.2.4
PIE1 REGISTER
Note:
This register contains the individual enable bits for the
peripheral interrupts.
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE
(1)
R/W-0
(2)
ADIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
ADIE(2): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1:
2:
PIC16C63A/73B devices do not have a parallel slave port implemented; always maintain this bit clear.
PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit clear.
DS30605B-page 22
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
peripheral interrupts.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-5: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch)
R/W-0
PSPIF
(1)
R/W-0
(2)
ADIF
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
ADIF(2): A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (clear by reading RCREG)
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (clear by writing to TXREG)
0 = The USART transmit buffer is full
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1:
PIC16C63A/73B devices do not have a parallel slave port implemented. This bit location is reserved on these
devices.
PIC16C63A/65B devices do not have an A/D implemented. This bit location is reserved on these devices.
2:
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 23
PIC16C63A/65B/73B/74B
4.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
4.2.2.7
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIR2 REGISTER
Note:
This register contains the CCP2 interrupt flag bit.
.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
DS30605B-page 24
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.2.2.8
PCON REGISTER
Note:
The Power Control (PCON) register contains flag bits to
allow differentiation between a Power-on Reset (POR),
a Brown-out Reset (BOR), a Watch-dog Reset (WDT)
and an external MCLR Reset.
BOR is unknown on POR. It must be set by
the user and checked on subsequent
resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).
REGISTER 4-8: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
bit7
R/W-q
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No power-on reset occurred
0 = A power-on reset occurred (must be set in software after a power-on reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No brown-out reset occurred
0 = A brown-out reset occurred (must be set in software after a brown-out reset occurs)
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 25
PIC16C63A/65B/73B/74B
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 4-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 4-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
PCL
8
4.4
PCLATH<4:3>
Program Memory Paging
PIC16CXX devices are capable of addressing a continuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
Note:
GOTO,CALL
2
11
Opcode <10:0>
PCLATH<4> is not used in these PICmicro®
devices. The use of PCLATH<4> as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).
PCLATH
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
0
7
PC
4.3.1
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
STACK
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
EXAMPLE 4-1:
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF PCLATH,3
CALL SUB1_P1
:
:
ORG 0x900
SUB1_P1
:
:
:
RETURN
;Select page 1 (800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30605B-page 26
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-2:
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
movlw
movwf
clrf
incf
btfss
goto
NEXT
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-4.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
Note:
;yes continue
Maintain the IRP and RP1 bits clear.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
6
Indirect Addressing
from opcode
0
IRP
7
FSR register
0
0
0
bank select
bank select
location select
00
00h
01
80h
10
100h
location select
11
180h
not used
Data
Memory
7Fh
Bank 0
Note:
FFh
17Fh
Bank 1
1FFh
Bank 2
Bank 3
For register file map detail see Figure 4-2.
Shaded portions are not implemented; maintain the IRP and RP1 bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 27
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 28
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0
AND RA5 PINS
Data
Bus
D
VDD
WR
Port
PORTA and TRISA Registers
Q
Q
CK
PORTA is a 6-bit latch.
Data Latch
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can configure these pins as output or input.
D
WR
TRIS
TRIS Latch
TTL
Input
Buffer
RD TRIS
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
RD PORT
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control
Register1).
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 5-2:
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data
Bus
WR
PORT
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
CK
Q
N
EXAMPLE 5-1:
INITIALIZING PORTA
(PIC16C73B/74B)
BCF
CLRF
STATUS, RP0
PORTA
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
;
;
I/O pin (1)
VSS
Analog
input
mode
Q
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
On all resets, pins with analog functions
are configured as analog and digital inputs.
N
Q
CK
Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Note:
P
I/O pin (1)
Data Latch
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as ’0’.
WR
TRIS
D
Q
CK
Q
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 29
PIC16C63A/65B/73B/74B
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit#
Buffer Function
(1)
bit0
TTL
Digital input/output or analog input
RA1/AN1(1)
bit1
TTL
Digital input/output or analog input
RA2/AN2(1)
bit2
TTL
Digital input/output or analog input
RA3/AN3/VREF(1)
bit3
TTL
Digital input/output or analog input or VREF
RA4/T0CKI
bit4
ST
Digital input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4(1)
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input
RA0/AN0
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
TABLE 5-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7 Bit 6
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1(1)
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
--11 1111
--11 1111
---- -000
---- -000
PORTA Data Direction Register
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented;
maintain this register clear.
DS30605B-page 30
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a power-on reset.
FIGURE 5-3:
WR Port
weak
P pull-up
Data Latch
D
FIGURE 5-4:
Q
I/O
(1)
pin
CK
TRIS Latch
D
Q
WR TRIS
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
RB0/INT is discussed in detail in Section 13.5.1.
VDD
Data Bus
This interrupt on mismatch feature, together with software configure able pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>).
BLOCK DIAGRAM OF
RB3:RB0 PINS
RBPU(2)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
CK
VDD
RBPU(2)
Data Bus
TTL
Input
Buffer
BLOCK DIAGRAM OF
RB7:RB4 PINS
WR Port
weak
P pull-up
Data Latch
D
Q
I/O
pin (1)
CK
TRIS Latch
D
Q
RD TRIS
WR TRIS
Q
RD Port
D
TTL
Input
Buffer
CK
EN
RD TRIS
RB0/INT
Q
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
Latch
D
EN
RD Port
ST
Buffer
Q1
Set RBIF
From other
RB7:RB4 pins
Q
D
RD Port
EN
Q3
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 31
PIC16C63A/65B/73B/74B
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
RB0/INT
bit0
TTL/ST(1)
Function
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable weak
pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable weak
pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable weak
pull-up. Serial programming clock.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable weak
pull-up. Serial programming data.
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
1111 1111
1111 1111
06h, 106h
PORTB
86h, 186h
TRISB
PORTB Data Direction Register
81h, 181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30605B-page 32
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.3
FIGURE 5-5:
PORTC and TRISC Registers
PORTC is an 8-bit bi-directional port. Each pin is individually configure able as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
PORTC BLOCK DIAGRAM
PORT/PERIPHERAL Select(2)
Peripheral Data Out
Data Bus
WR
PORT
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
D
VDD
0
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin (1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
TABLE 5-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit1
ST
Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
bit6
ST
Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
87h
TRISC
1111 1111
1111 1111
Address
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 33
PIC16C63A/65B/73B/74B
5.4
PORTD and TRISD Registers
Note:
FIGURE 5-6:
Data
Bus
The PIC16C63A and PIC16C73B do not
provide PORTD. The PORTD and TRISD
registers are not implemented.
WR
PORT
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or
output.
PORTD BLOCK DIAGRAM
D
Q
I/O pin (1)
CK
Data Latch
D
WR
TRIS
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Q
D
ENEN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0
RD1/PSP1
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1
RD2/PSP2
bit2
ST/TTL(1)
Input/output port pin or parallel slave port bit2
bit3
ST/TTL(1)
Input/output port pin or parallel slave port bit3
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
RD5/PSP5
bit5
ST/TTL(1)
Input/output port pin or parallel slave port bit5
RD6/PSP6
bit6
ST/TTL(1)
Input/output port pin or parallel slave port bit6
bit7
ST/TTL(1)
Input/output port pin or parallel slave port bit7
RD0/PSP0
RD3/PSP3
RD4/PSP4
RD7/PSP7
Function
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in parallel slave port mode.
TABLE 5-8:
Address
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
08h
PORTD
RD7
88h
TRISD
PORTD Data Direction Register
89h
TRISE
IBF
RD6
OBF IBOV PSPMODE
—
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30605B-page 34
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.5
PORTE and TRISE Register
FIGURE 5-7:
Data
Bus
Note 1: The PIC16C63A and PIC16C73B do not
provide PORTE. The PORTE and TRISE
registers are not implemented.
D
WR
PORT
Q
I/O pin(1)
CK
2: The PIC16C63A/65B does not provide an
A/D module. A/D functions are not implemented.
Data Latch
D
WR
TRIS
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configured as
inputs or outputs. These pins have Schmitt Trigger
input buffers.
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured for digital I/O. In this mode the input buffers are TTL.
Register 5-1 shows the TRISE register, which also controls the parallel slave port operation.
PORTE BLOCK DIAGRAM
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
PORTE pins may be multiplexed with analog inputs
(PIC16C74B only). The operation of these pins is
selected by control bits in the ADCON1 register. When
selected as an analog input, these pins will read as ’0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
On a Power-on Reset these pins are configured as analog inputs.
TABLE 5-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
RE0/RD/AN5
bit0
ST/TTL(1)
Input/output port pin or read control input in parallel slave port mode or analog
input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
Function
RE1/WR/AN6
bit1
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode or analog
input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7
bit2
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port mode or
analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in parallel slave port mode.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 35
PIC16C63A/65B/73B/74B
REGISTER 5-1: TRISE REGISTER (ADDRESS 89h)
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7 :
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2:
TRISE2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1:
TRISE1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0:
TRISE0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
TABLE 5-10:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1
—
—
—
—
—
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
0000 -111
---- -000
---- -000
PORTE Data Direction Bits
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
DS30605B-page 36
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.6
Note:
Parallel Slave Port (PSP)
The PIC16C63A and PIC16C73B do not
provide a parallel slave port. The PORTD,
PORTE, TRISD and TRISE registers are
not implemented.
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode, it is asynchronously readable and writable, by the external world
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input,
RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to
be the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0>) must be set, which will configure pins
RE2:RE0 as digital I/O.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 5-8:
Data Bus
D
WR
PORT
Q
RDx
pin
CK
TTL
Q
RD
PORT
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
There are actually two 8-bit latches, one for data-out
(from the PICmicro®) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored,
since the microprocessor is controlling the direction of
data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full (IBF) status flag bit (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal the
write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buffer Overflow (IBOV) status flag
bit (TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
Read
TTL
RD
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 5-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 37
PIC16C63A/65B/73B/74B
FIGURE 5-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-11:
Address
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port data latch when written: Port pins when read
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
---- -xxx
---- -uuu
08h
PORTD
09h
PORTE
89h
TRISE
0000 -111
0000 -111
0Ch
PIR1
PSPIF ADIF RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE ADIE RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
9Fh
ADCON1
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
—
—
IBF
OBF
—
—
—
—
—
IBOV PSPMODE
—
—
RE2
RE1
RE0
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
DS30605B-page 38
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
6.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The prescaler is not readable or writable. Section 6.3 details the
operation of the prescaler.
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Additional information on the Timer0 module is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A).
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 6-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
M
U
X
1
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 39
PIC16C63A/65B/73B/74B
6.2
Using Timer0 with an External Clock
module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.3
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Prescaler
Note:
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
REGISTER 6-1: OPTION_REG REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7:
RBPU
bit 6:
INTEDG
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Note:
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023A) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30605B-page 40
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 6-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
01h,101h
TMR0
0Bh,8Bh,
10Bh,18Bh
INTCON
81h,181h
OPTION_REG RBPU INTEDG
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 41
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 42
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by either of the two CCP modules
(Section 9.0). Register 7-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored.
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023A).
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
R/W-0
R/W-0
TMR1CS TMR1ON
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
bit 2:
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 43
PIC16C63A/65B/73B/74B
7.1
Timer1 Operation in Timer Mode
7.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The prescaler however will continue to increment.
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
clock input
TMR1L
1
TMR1ON
on/off
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(2)
T1SYNC
(2)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
SLEEP input
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in external clock mode.
DS30605B-page 44
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.3
Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
7.3.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
± 20 PPM
Note 1: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
7.5
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in compare
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A) show how to read
and write Timer1 when it is running in asynchronous
mode.
7.4
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
Note:
Resetting Timer1 using a CCP Trigger
Output
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for
Timer1.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 45
PIC16C63A/65B/73B/74B
TABLE 7-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh, INTCON
10Bh,
18Bh
0Ch
PIR1
Value on:
POR,
BOR
Value on
all other
resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
PSPIF(1) ADIF(2)
(1)
(2)
8Ch
PIE1
PSPIE
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
—
ADIE
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605B-page 46
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.0
TIMER2 MODULE
8.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any
device reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is initialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSPort module, which optionally uses it to generate
shift clock.
FIGURE 8-1:
Sets flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
output (1)
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
TMR2 reg
Register 8-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A).
EQ
Comparator
4
PR2 reg
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS1:
T2CKPS0
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected
by the SSP module as a baud clock.
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
R/W-0
R/W-0
T2CKPS1 T2CKPS0
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6-3:
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0:
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 1999 Microchip Technology Inc.
Preliminary
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30605B-page 47
PIC16C63A/65B/73B/74B
TABLE 8-1:
Address
Name
0Bh,8Bh,
INTCON
10Bh,18Bh
0Ch
8Ch
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
ADIF(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
TMR2
T2CON
92h
PR2
Value on
all other
resets
Bit 6
PSPIF(1)
11h
Value on:
POR,
BOR
Bit 7
PIR1
12h
Legend:
Note 1:
2:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
PSPIE
ADIE
Timer2 module’s register
—
0000 0000 0000 0000
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605B-page 48
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.0
CAPTURE/COMPARE/PWM
MODULES
CCP2 Module:
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
Capture/Compare/PWM Register1 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in “Using the CCP Modules”
(AN594).
TABLE 9-1:
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.
TABLE 9-2:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be configured for the special event trigger, which clears TMR1.
Compare
Compare
The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None.
PWM
Compare
None.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 49
PIC16C63A/65B/73B/74B
REGISTER 9-1: CCP1CON REGISTER/CCP2CON REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as
‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets
TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
DS30605B-page 50
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.1
9.1.2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a capture condition.
FIGURE 9-1:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
Prescaler
÷ 1, 4, 16
Set flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
Pin
CCPR1H
and
edge detect
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
9.1.3
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
SOFTWARE INTERRUPT
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
9.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. Any reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 9-1:
CCPR1L
Capture
Enable
TMR1H
TIMER1 MODE SELECTION
TMR1L
CLRF
MOVLW
MOVWF
CCP1CON<3:0>
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new precscaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Q’s
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 51
PIC16C63A/65B/73B/74B
9.2
Compare Mode
9.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
PWM Mode (PWM)
In pulse width modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
COMPARE MODE OPERATION
BLOCK DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Figure 9-3 shows a simplified block diagram of the CCP
module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
CCPR1L
CCPR1H CCPR1L
Q S Output
Logic
match
RC2/CCP1
R
Pin
TRISC<2>
Output Enable CCP1CON<3:0>
Mode Select
CCP1CON<5:4>
Duty cycle registers
Comparator
TMR1H
CCPR1H (Slave)
TMR1L
R
Comparator
9.2.1
CCP PIN CONFIGURATION
RC2/CCP1
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
9.2.2
(Note 1)
S
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
9.2.4
TMR2
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 9-4) has a time base (period) and
a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 9-4:
PWM OUTPUT
Period
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Duty Cycle
The special event trigger output of CCP1 resets the TMR1
register pair. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note:
Q
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
The special event trigger from the
CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
DS30605B-page 52
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
9.3.2
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
Resolution
The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
9.3.3
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
Note:
(
log(2)
)
bits
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
 1999 Microchip Technology Inc.
=
FOSC
log FPWM
Preliminary
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
DS30605B-page 53
PIC16C63A/65B/73B/74B
TABLE 9-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
PSPIF(1) ADIF(2)
0000 000x 0000 000u
0Ch
PIR1
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
—
—
CCP1X
—
CCP2X
CCP1Y
CCP2Y
CCP1M3
CCP2M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear.
2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear.
TABLE 9-4:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
Value on:
POR,
BOR
Value on
all other
resets
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
(1)
PSPIE
(2)
8Ch
PIE1
8Dh
PIE2
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 module’s register
0000 0000 0000 0000
92h
PR2
Timer2 module’s period register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
—
—
—
ADIE
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM register2 (LSB)
1Ch
CCPR2H
Capture/Compare/PWM register2 (MSB)
1Dh
CCP2CON
—
—
—
CCP1X
CCP2X
CCP1Y
CCP2Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605B-page 54
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.0
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
10.1
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral
or microcontroller devices. These peripheral devices
may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate
in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional information on the SSP module can be found in the PICmicro™
Mid-Range
MCU
Family
Reference
Manual
(DS33023A).
10.2 SPI Mode......................................................... 58
10.3 SSP I2C Operation .......................................... 61
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment.”
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 55
PIC16C63A/65B/73B/74B
10.2
SPI Mode for PIC16C63A/65B/73B/74B
REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0
SMP
CKE
R-0
R-0
R-0
R-0
R-0
R-0
D/A
P
S
R/W
UA
BF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 7:
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire®)
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
I2C Mode
This bit must be maintained clear
bit 6:
CKE: SPI Clock Edge Select (Figure 10-2, Figure 10-3, and Figure 10-4)
SPI Mode
CKP = 0
1 = Data transmitted on rising edge of SCK (Microwire® alternate)
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK (Microwire® default)
0 = Data transmitted on rising edge of SCK
I2C Mode
This bit must be maintained clear
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last. SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is ’0’ on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last. SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is ’0’ on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS30605B-page 56
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
REGISTER 10-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level (Microwire® default)
0 = Idle state for clock is a low level (Microwire® alternate)
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 57
PIC16C63A/65B/73B/74B
10.2.1
SPI MODE
This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Manual
(DS33023A).
FIGURE 10-1: SSP BLOCK DIAGRAM
(SPI MODE)
Internal
data bus
Read
Write
SSPBUF reg
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accomplish communication, typically three pins are used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
SSPSR reg
RC4/SDI/SDA
Additionally, a fourth pin may be used when in a slave
mode of operation:
Shift
clock
bit0
RC5/SDO
• Slave Select (SS) RA5/SS/AN4
SS Control
Enable
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the following to be specified:
RA5/SS/AN4
Edge
Select
2
Clock Select
•
•
•
•
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
SSPM3:SSPM0
4
Edge
Select
RC3/SCK/
SCL
TMR2 output
2
Prescaler TCY
4, 16, 64
TRISC<3>
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appropriately programmed. That is:
•
•
•
•
•
.
SDI must have TRISC<4> set
SDO must have TRISC<5> cleared
SCK (Master mode) must have TRISC<3> cleared
SCK (Slave mode) must have TRISC<3> set
SS must have TRISA<5> set
Note 1:
When the SPI is in slave mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is
set to VDD.
2: If the SPI is used in slave mode with
CKE = '1', then the SS pin control must be
enabled.
DS30605B-page 58
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 10-2: SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit6
bit7
SDO
bit5
bit2
bit3
bit4
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
bit7
bit0
SSPIF
FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit6
bit7
SDO
bit5
bit2
bit3
bit4
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 59
PIC16C63A/65B/73B/74B
TABLE 10-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh.
INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
Value on:
POR,
BOR
Value on
all other
resets
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF(2)
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIE
ADIE
8Ch
PIE1
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON WCOL
85h
TRISA
94h
SSPSTAT
SSPOV SSPEN
—
—
SMP
CKE
CKP
SSPM3 SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
PORTA Data Direction Register
D/A
P
S
R/W
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605B-page 60
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.3
SSP I 2C Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
The SSP module functions are enabled by setting
SSP enable bit SSPEN (SSPCON<5>).
FIGURE 10-5: SSP BLOCK DIAGRAM
(I2C MODE)
RC3/SCK/SCL
Write
SLAVE MODE
SSPBUF reg
In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
SSPSR reg
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
MSb
LSb
Match detect
Addr Match
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
The SSP module has five registers for I2C operation.
These are the:
•
•
•
•
•
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits.
10.3.1
shift
clock
RC4/
SDI/
SDA
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with start and
stop bit interrupts enabled to support firmware
Master mode
• I 2C Slave mode (10-bit address), with start and
stop bit interrupts enabled to support firmware
Master mode
• I 2C start and stop bit interrupts enabled to support
firmware Master mode, Slave is idle
Additional information on SSP I 2C operation can be
found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A).
Internal
Data Bus
Read
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
SSP Address Register (SSPADD)
a)
b)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and SSPOV.
The shaded cells show the condition where user software did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPBUF register while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the SSP
module, is shown in timing parameter #100 and parameter #101.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 61
PIC16C63A/65B/73B/74B
10.3.1.1
ADDRESSING
1.
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 10-7). The five Most Significant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
TABLE 10-2:
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
No
No
Yes
1
0
Note:
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
DS30605B-page 62
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.3.1.2
RECEPTION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 10-6:
Receiving Address
Receiving Data
R/W=0
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
S
1
2
3
4
5
6
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
Cleared in software
9
P
Bus Master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 63
PIC16C63A/65B/73B/74B
10.3.1.3
TRANSMISSION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 10-7).
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 10-7: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30605B-page 64
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.3.2
MASTER MODE
10.3.3
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I 2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the
TRISC<3> bit.
In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address transfer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 10-3:
MULTI-MASTER MODE
REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
Address
8Ch
PIE1
13h
SSPBUF
PSPIF(1) ADIF(2)
(1)
PSPIE
ADIE
(2)
Synchronous Serial Port Receive Buffer/Transmit Register
2
Synchronous Serial Port (I C mode) Address Register
93h
SSPADD
14h
SSPCON
WCOL
SSPOV SSPEN
94h
SSPSTAT
SMP(3)
CKE(3)
87h
TRISC
CKP
D/A
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
UA
BF
PORTC Data Direction register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’.
Shaded cells are not used by SSP module in I 2C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear.
3: Maintain these bits clear in I2C mode.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 65
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 66
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial I/
O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be set
in order to configure pins RC6/TX/CK and RC7/RX/DT as
the universal synchronous asynchronous receiver
transmitter.
REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit7
bit 7:
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
Unimplemented: Read as '0'
bit 2:
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data. Can be parity bit.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 67
PIC16C63A/65B/73B/74B
REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
FERR
R-0
OERR
R-x
RX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
Unimplemented: Read as '0'
bit 2:
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of received data (Can be parity bit)
DS30605B-page 68
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.1
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
11.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
near the center of each bit time by a majority detect circuit to determine if a high or a low level is present at the
RX pin.
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
TABLE 11-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(SPBRG+1))
(Synchronous) Baud Rate = FOSC/(4(SPBRG+1))
Baud Rate= FOSC/(16(SPBRG+1))
NA
TABLE 11-2:
Address
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN CREN
—
FERR
OERR RX9D
0000 -00x
0000 -00x
99h
SPBRG
Baud Rate Generator Register
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 69
PIC16C63A/65B/73B/74B
11.2
USART Asynchronous Mode
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
11.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
LSb
• • •
(8)
Pin Buffer
and Control
0
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30605B-page 70
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Steps to follow when setting up an Asynchronous
Transmission:
4.
1.
5.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
2.
3.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
6.
7.
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 2
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
Start Bit
Bit 0
WORD 2
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 11-3:
Address
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
PSPIF(1)
ADIF(2)
SPEN
RX9
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
SREN
CREN
—
FERR
OERR
0Ch
PIR1
18h
RCSTA
19h
TXREG USART Transmit Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
PSPIE(1)
ADIE(2)
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
SSPIE CCP1IE
—
BRGH
TMR2IE
TRMT
Bit 0
Value on:
POR,
BOR
TMR1IF 0000 0000
RX9D
0000 -00x
Value on
all other
Resets
0000 0000
0000 -00x
0000 0000
0000 0000
TMR1IE 0000 0000
0000 0000
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 71
PIC16C63A/65B/73B/74B
11.2.2
USART ASYNCHRONOUS RECEIVER
two bytes of data to be received and transferred to the
RCREG FIFO and a third byte to begin shifting to the
RSR register. On the detection of the STOP bit of the
third byte, if the RCREG register is still full, then overrun
error bit OERR (RCSTA<1>) will be set. The word in the
RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Overrun bit
OERR has to be cleared in software. This is done by
resetting the receive logic (CREN is cleared and then
set). If bit OERR is set, transfers from the RSR register
to the RCREG register are inhibited, so it is essential to
clear error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit
FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG, will load
bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before
reading RCREG register in order not to lose the old
FERR and RX9D information.
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buffered register, i.e. it is a two deep FIFO. It is possible for
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
³ 64
or
³ 16
Baud Rate Generator
RSR register
MSb
Stop (8)
• • •
7
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 11-5: ASYNCHRONOUS RECEPTION
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
Start
bit
bit0
bit1
bit7/8 Stop
bit
Start
bit
bit0
WORD 1
RCREG
bit7/8
Stop
bit
Start
bit
bit7/8
Stop
bit
WORD 2
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS30605B-page 72
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
6.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
TABLE 11-4:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
PSPIF(1)
ADIF(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
18h
RCSTA
1Ah
RCREG USART Receive Register
PIE1
TXSTA
99h
SPBRG
9.
Bit 7
PIR1
8Ch
8.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
0Ch
98h
7.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
(1)
PSPIE
(2)
ADIE
RCIE
TXIE
TX9
TXEN
SYNC
CSRC
SSPIE CCP1IE
—
BRGH
Baud Rate Generator Register
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 73
PIC16C63A/65B/73B/74B
11.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e., transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
11.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-impedance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-impedance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock
(Figure 11-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back transfers are possible.
DS30605B-page 74
Preliminary
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-5:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
PSPIF(1)
ADIF(2)
SPEN
RX9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Bit 5
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
98h
TXSTA
99h
SPBRG
SSPIE CCP1IE
—
BRGH
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-6: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
bit 0
bit 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit 2
bit 7
bit 0
bit 1
bit 7
WORD 2
WORD 1
RC6/TX/CK pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
TXEN bit
’1’
’1’
Note: Sync master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words
FIGURE 11-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 75
PIC16C63A/65B/73B/74B
11.3.2
if it is set. The ninth receive bit is buffered the same way
as the receive data. Reading the RCREG register will
load bit RX9D with a new value, therefore it is essential
for the user to read the RCSTA register before reading
RCREG in order not to lose the old RX9D information.
USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on the
RC7/RX/DT pin on the falling edge of the clock. If enable
bit SREN is set, then only a single word is received. If
enable bit CREN is set, the reception is continuous until
CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the
Receive Shift Register (RSR) is transferred to the
RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual
interrupt can be enabled/disabled by setting/clearing
enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only
bit, which is reset by the hardware. In this case, it is reset
when the RCREG register has been read and is empty.
The RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third
byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register
is still full, then overrun error bit OERR (RCSTA<1>) is
set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO.
Bit OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to the
RCREG are inhibited, so it is essential to clear bit OERR
TABLE 11-6:
Address
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. (Section 11.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
PSPIF(1)
ADIF(2)
SPEN
RX9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
Bit 5
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
98h
TXSTA
99h
SPBRG
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
DS30605B-page 76
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.4
11.4.2
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a don’t care in slave mode.
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a)
1.
11.4.1
b)
c)
d)
e)
USART SYNCHRONOUS SLAVE
TRANSMIT
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the interrupt vector (0004h).
2.
3.
4.
5.
6.
Steps to follow when setting up a synchronous slave
transmission:
7.
1.
8.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
 1999 Microchip Technology Inc.
Preliminary
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
DS30605B-page 77
PIC16C63A/65B/73B/74B
TABLE 11-7:
Address
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7
Bit 6
PSPIF(1)
ADIF(2)
SPEN
RX9
Value on:
POR,
BOR
Value on all
other Resets
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
0Ch
PIR1
18h
RCSTA
19h
TXREG USART Transmit Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
SREN CREN
PSPIE(1)
ADIE(2)
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
SSPIE CCP1IE TMR2IE
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
TABLE 11-8:
Address
Name
0Ch
PIR1
18h
RCSTA
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7
Bit 6
PSPIF(1)
ADIF(2)
SPEN
RX9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0000
0000 0000
Bit 5
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG
Baud Rate Generator Register
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.
DS30605B-page 78
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
12.0
Note:
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The PIC16C63A and PIC16C65B do not
include A/D modules. ADCON0, ADCON1
and ADRES registers are not implemented. ADIF and ADIE bits are reserved
and should be maintained clear.
The 8-bit analog-to-digital (A/D) converter module has
five inputs for the PIC16C73B and eight for the
PIC16C74B.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD) or the
voltage level on the RA3/AN3/VREF pin.
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in sleep, the A/D conversion clock must be derived from
the A/D’s internal RC oscillator.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 12-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 12-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference)
or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A) and in Application Note,
AN546.
REGISTER 12-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C74B only.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 79
PIC16C63A/65B/73B/74B
REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
RA0
RA1
RA2
RA5
RA3
000
001
010
011
100
101
11x
A
A
A
A
A
A
D
A
A
A
A
A
A
D
A
A
A
A
D
D
D
A
A
A
A
D
D
D
A
VREF
A
VREF
A
VREF
D
RE0(1) RE1(1) RE2(1)
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
VREF
VDD
RA3
VDD
RA3
VDD
RA3
VDD
A = Analog input
D = Digital I/O
Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only.
DS30605B-page 80
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The following steps should be followed for doing an A/D
conversion:
4.
1.
5.
2.
3.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
7.
• Waiting for the A/D interrupt
Read A/D result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 12-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
100
RA5/AN4
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
VREF
VDD
000 or
010 or
100 or
11x
(Reference
voltage)
000
RA0/AN0
001 or
011 or
101
PCFG2:PCFG0
Note 1: Not available on PIC16C73B.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 81
PIC16C63A/65B/73B/74B
12.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 12-2. The source impedance affects the
offset voltage at the analog input (due to pin leakage
current).
The maximum recommended impedance for analog sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition must pass before
the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A). In general, however, given a max
of 10kΩ and a worst case temperature of 100°C, TACQ
will be no more than 16µsec.
FIGURE 12-2: ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS
RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
EQUATION 12-1:
TACQ
RIC
= interconnect resistance
SS
CHOLD
= sampling switch
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
ACQUISITION TIME
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
TAMP = 5µS
TC = - (51.2pF)(1kΩ + RSS + RS) In(1/511)
TCOFF = (Temp -25°C)(0.05µS/°C)
DS30605B-page 82
6V
5V
VDD 4V
3V
2V
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
12.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
2TOSC
8TOSC
32TOSC
Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
12.3
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of the devices specification.
3: The TRISE register is not provided on the
PIC16C73B.
12.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed
conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
 1999 Microchip Technology Inc.
12.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the A/
D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
12.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruction that sets the GO/DONE bit.
Effects of a RESET
A device reset forces all registers to their reset state.
The A/D module is disabled and any conversion in
progress is aborted. All pins with analog functions are
configured as available inputs.
The ADRES register will contain unknown data after a
power-on reset.
12.7
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/DONE
bit will be set, starting the A/D conversion, and the Timer1
counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired
location). The appropriate analog input channel must be
selected and the minimum acquisition done before the
“special event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
Preliminary
DS30605B-page 83
PIC16C63A/65B/73B/74B
TABLE 12-1:
Address
SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY)
Name
INTCON
0Bh,8Bh,
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
Value on:
POR,
BOR
Value on all
other
Resets
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
(1)
PSPIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE 0000 0000 0000 0000
1Eh
ADRES
A/D Result Register
1Fh
ADCON0
ADCS1
9Fh
ADCON1
—
—
05h
PORTA
—
—
85h
TRISA
—
—
09h
PORTE
—
—
0Ch
89h
TRISE
IBF
xxxx xxxx uuuu uuuu
CHS1
CHS0
GO/
DONE
—
—
—
—
PCFG2
PCFG1
RA5
RA4
RA3
RA2
RA1
ADCS0 CHS2
OBF
ADON
PCFG0 ---- -000 ---- -000
RA0
IBOV
—
—
PSPMODE
—
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
—
0000 00-0 0000 00-0
RE2
RE1
RE0
PORTE Data Direction Bits
---- -xxx ---- -uuu
0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C63A/73B; always maintain these bits clear.
DS30605B-page 84
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming (ICSP)
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only and is
designed to keep the part in reset, while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, WDT wake-up or through an
interrupt. Several oscillator options are also made
available to allow the part to fit the application. The RC
oscillator option saves system cost, while the LP crystal
option saves power. A set of configuration bits are used
to select various options.
13.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the user
program memory space. In fact, it belongs to the special
test/configuration memory space (2000h - 3FFFh),
which can be accessed only during programming.
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its own
RC oscillator for added reliability. There are two timers
that offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
REGISTER 13-1: CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0
—
BODEN
CP1
CP0
PWRTE WDTE FOSC1 FOSC0
bit13
bit0
Register:
Address
CONFIG
2007h
bit 13-8
5-4:
CP1:CP0: Code Protection bits (2)
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
Unimplemented: Read as ’1’
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1:
2:
Enabling brown-out reset automatically enables power-up timer (PWRT), regardless of the value of bit PWRTE.
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 85
PIC16C63A/65B/73B/74B
13.2
Oscillator Configurations
13.2.1
OSCILLATOR TYPES
TABLE 13-1:
Ranges Tested:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
13.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
These values are for design guidance only. See notes at
bottom of page.
Resonators Used:
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 13-1). The
PIC16CXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source to drive the OSC1/CLKIN pin
(Figure 13-2). See the PICmicro™ Mid-Range MCU
Reference Manual (DS33023A) for details on building
an external oscillator.
455 kHz
Panasonic EFO-A455K04B
± 0.3%
2.0 MHz
Murata Erie CSA2.00MG
± 0.5%
4.0 MHz
Murata Erie CSA4.00MG
± 0.5%
8.0 MHz
Murata Erie CSA8.00MT
± 0.5%
16.0 MHz
Murata Erie CSA16.00MX
± 0.5%
Resonators used did not have built-in capacitors.
TABLE 13-2:
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
XT
HS
To internal
logic
C1
XTAL
RF
OSC2
C2
SLEEP
PIC16CXX
These values are for design guidance only. See notes at
bottom of page.
RS
Note1
Crystals Used:
See Table 13-1 and Table 13-2 for recommended values
of C1 and C2.
Note 1:
32 kHz
200 kHz
FIGURE 13-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
PIC16CXX
Open
DS30605B-page 86
OSC2
Epson C-001R32.768K-A
± 20 PPM
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
A series resistor may be required for AT strip
cut crystals.
Clock from
ext. system
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
FIGURE 13-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
OSC1
CERAMIC RESONATORS
Note 1: Higher capacitance increases the stability of
the oscillator, but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate
values of external components.
3: Rs may be required in HS mode, as well as
XT mode to avoid overdriving crystals with low
drive level specification.
4: When migrating from other PICmicro devices,
oscillator performance should be verified.
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.2.3
RC OSCILLATOR
13.3
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. The oscillator frequency will vary from
unit to unit due to normal process parameter variation.
The difference in lead frame capacitance between
package types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 13-3 shows how the
R/C combination is connected to the PIC16CXX.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for
waveform).
FIGURE 13-3: RC OSCILLATOR MODE
V DD
Reset
The PIC16CXX differentiates between various kinds of
reset:
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on POR, on the MCLR and WDT Reset, on
MCLR reset during SLEEP, and on BOR. The TO and
PD bits are set or cleared differently in different reset
situations as indicated in Table 13-4. These bits are
used in software to determine the nature of the reset.
See Table 13-6 for a full description of reset states of all
registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 13-4.
Rext
Internal
clock
OSC1
Cext
PIC16CXX
VSS
Fosc/4
The PICmicro devices have a MCLR noise filter in the
MCLR reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT reset does not drive
MCLR pin low.
OSC2/CLKOUT
Recommended Values: REXT = 3k to 100kΩ
CEXT = 20 pf to 30 pf
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 87
PIC16C63A/65B/73B/74B
FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip Reset
R
10-bit Ripple counter
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
DS30605B-page 88
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.4
Resets
13.4.4
13.4.1
POWER-ON RESET (POR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VPP falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situation will reset the device. If VDD falls below VBOR for
less than TBOR, a reset may not occur.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create
a POR. A maximum rise time for VDD is specified. See
Electrical Specifications for details.
Once the brown-out occurs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the brown-out reset
process will restart when VDD rises above VBOR with
the power-up timer reset. The power-up timer is
always enabled when the brown-out reset circuit is
enabled regardless of the state of the PWRT configuration bit.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature) must be met to ensure operation. If these conditions are not met, the device must be
held in reset until the operating conditions are met.
Brown-out reset may be used to meet the startup conditions.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.2
13.4.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT operates on an internal RC oscillator. The device is kept in
reset as long as the PWRT is active. The PWRT’s time
delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in
parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
13.4.3
BROWN-OUT RESET (BOR)
Table 13-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 13-6 shows the
reset conditions for all the registers.
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
delay. This ensures that the crystal oscillator or resonator has started and stabilized.
13.4.6
POWER CONTROL/STATUS REGISTER
(PCON)
The Brown-out Reset Status bit, BOR, is unknown on a
POR. It must be set by the user and checked on subsequent resets to see if bit BOR was cleared, indicating a
BOR occurred. The BOR bit is not predictable if the
brown-out reset circuitry is disabled.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent resets
to see if it has been cleared.
TABLE 13-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from SLEEP
1024TOSC
72 ms + 1024TOSC
1024TOSC
—
72 ms
—
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
RC
72 ms
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 89
PIC16C63A/65B/73B/74B
TABLE 13-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 13-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
000x xuuu
---- --u0
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
PC +
1(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit read as ’0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
Status Register
IRP
RP1
RP0
TO
PD
Z
DC
C
POR
BOR
PCON Register
DS30605B-page 90
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 13-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
63A
65B
73B
74B
N/A
N/A
N/A
TMR0
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
63A
65B
73B
74B
0000h
0000h
PC + 1(2)
STATUS
63A
65B
73B
74B
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
63A
65B
73B
74B
--0x 0000
--0u 0000
--uu uuuu
PORTB
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
63A
65B
73B
74B
---- -xxx
---- -uuu
---- -uuu
PCLATH
63A
65B
73B
74B
---0 0000
---0 0000
---u uuuu
INTCON
63A
65B
73B
74B
0000 000x
0000 000u
uuuu uuuu(1)
63A
65B
73B
74B
-0-- 0000
-0-- 0000
-u-- uuuu(1)
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu(1)
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu(1)
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu(1)
PIR2
63A
65B
73B
74B
---- ---0
---- ---0
---- ---u(1)
TMR1L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
63A
65B
73B
74B
--00 0000
--uu uuuu
--uu uuuu
TMR2
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
T2CON
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu
SSPBUF
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
CCPR1L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu
RCSTA
63A
65B
73B
74B
0000 -00x
0000 -00x
uuuu -uuu
TXREG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
PIR1
RCREG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
CCPR2L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
ADRES
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
63A
65B
73B
74B
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
Legend:
Note 1:
2:
3:
u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 13-5 for reset value for specific condition.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 91
PIC16C63A/65B/73B/74B
TABLE 13-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
TRISA
63A
65B
73B
74B
--11 1111
--11 1111
--uu uuuu
TRISB
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISC
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISD
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISE
63A
65B
73B
74B
0000 -111
0000 -111
uuuu -uuu
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu
63A
65B
73B
74B
0-00 0000
0-00 0000
u-uu uuuu
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
PIE2
63A
65B
73B
74B
---- ---0
---- ---0
---- ---u
PCON
63A
65B
73B
74B
---- --uu
---- --uu
PR2
63A
65B
73B
74B
1111 1111
1111 1111
1111 1111
SSPADD
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
PIE1
----
--0q(3)
SSPSTAT
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu
TXSTA
63A
65B
73B
74B
0000 -010
0000 -010
uuuu -uuu
SPBRG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
63A
65B
73B
74B
---- -000
---- -000
---- -uuu
ADCON1
Legend:
Note 1:
2:
3:
u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 13-5 for reset value for specific condition.
DS30605B-page 92
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.5
Interrupts
Note:
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be reenabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged.
2.
The program branches to the interrupt vector and executes the interrupt
service routine.
3.
The interrupt service routine completes the execution of the RETFIE
instruction. This causes the GIE bit to
be set (enables interrupts), and the
program returns to the instruction
after the one which was meant to disable interrupts.
Perform the following to ensure that interrupts are globally disabled:
LOOP BCF
The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function register INTCON.
INTCON, GIE
BTFSC INTCON, GIE
GOTO
:
LOOP
; Disable global
;
interrupt bit
; Global interrupt
;
disabled?
; NO, try again
;
Yes, continue
;
with program
;
flow
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 93
PIC16C63A/65B/73B/74B
FIGURE 13-5: INTERRUPT LOGIC
PSPIF
PSPIE
ADIF
ADIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF
INTF
RBIF
PIC16C63A
Yes
Yes
PIC16C65B
Yes
Yes
PIC16C73B
Yes
PIC16C74B
Yes
13.5.1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
CCP2IF
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
INT INTERRUPT
13.6
The external interrupt on RB0/INT pin is edge triggered: either rising, if bit INTEDG (OPTION_REG<6>)
is set or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 13.8 for details on SLEEP mode.
13.5.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
13.5.3
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Users may wish to save key registers during an interrupt i.e., W register and STATUS register.
This will have to be implemented in software.
Example 13-1 stores and restores the STATUS, W, and
PCLATH registers. The register W_TEMP must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
The example:
a)
b)
c)
d)
e)
f)
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register.
Executes the ISR code.
Restores the STATUS register
(and bank select bit).
Restores the W and PCLATH registers.
PORTB INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
DS30605B-page 94
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
:
(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
;Copy
;Swap
;bank
;Save
;Only
;Save
PCLATH_TEMP, W
PCLATH
STATUS_TEMP, W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
13.7
W to TEMP register, could be bank one or zero
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
required if using pages 1, 2 and/or 3
PCLATH into W
Watchdog Timer (WDT)
The watchdog timer is a free running on-chip RC oscillator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. The WDT will run, even if the
clock on the OSC1/CLKIN and OSC2/CLKOUT pins of
the device has been stopped, for example, by execution
of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.7.1
WDT PERIOD
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEP instruction prevents the WDT from generating a reset, but will allow the WDT to wake the device
from sleep mode.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.7.2
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note:
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
 1999 Microchip Technology Inc.
WDT PROGRAMMING CONSIDERATIONS
Preliminary
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
DS30605B-page 95
PIC16C63A/65B/73B/74B
FIGURE 13-6: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
WDT Timer
1
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 MUX
(Figure 6-1)
0
1
MUX
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 13-7:
PSA
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h,181h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS30605B-page 96
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
13.8
Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present.
Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
13.8.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was enabled).
Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
External MCLR reset will cause a device reset. All other
events are considered a continuation of program execution and cause a “wake-up”. The TO and PD bits in
the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from SLEEP:
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
1.
2.
3.
4.
5.
6.
7.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode
(SPI / I2C).
CCP capture mode interrupt.
Parallel slave port read or write.
A/D conversion (when A/D clock source is RC).
USART TX or RX (synchronous slave mode).
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 97
PIC16C63A/65B/73B/74B
FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency (2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
Note 1:
2:
3:
4:
13.9
PC+1
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
13.10
Program Verification/Code Protection
Microchip does not recommend code protecting windowed devices. Devices that are
code protected may be erased, but not programmed again.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the four least significant bits of the ID
location are used.
13.11
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay is not present in RC osc mode.
GIE = ’1’ assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
PC+2
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then
supplied to or from the device, depending if the command was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
FIGURE 13-8: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
In-Circuit Serial Programming
PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming voltage. This allows customers to manufacture boards with
unprogrammed devices, and then program the microcontroller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
External
Connector
Signals
To Normal
Connections
PIC16CXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
DS30605B-page 98
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file register designator and ’d’ represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
TABLE 14-1:
OPCODE FIELD
DESCRIPTIONS
Field
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Table 14-2 lists the instructions recognized by the
MPASM assembler.
Figure 14-1 shows the general formats that the instructions can have.
Note:
0xhh
Description
where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
FIGURE 14-1: GENERAL FORMAT FOR
INSTRUCTIONS
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Top of Stack
Program Counter
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
Literal and control operations
General
13
Options
( )
Contents
→
Assigned to
<>
∈
8
7
OPCODE
Destination either the W register or the specified
dest
register file location
[ ]
0
b = 3-bit bit address
f = 7-bit file register address
PCLATH Program Counter High Latch
GIE
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
label Label name
TOS
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
f
d
The instruction set is highly orthogonal and is grouped
into three basic categories:
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
10
0
Register bit field
OPCODE
k (literal)
In the set of
k = 11-bit immediate value
italics User defined term (font is courier)
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 99
PIC16C63A/65B/73B/74B
TABLE 14-2:
PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
DS30605B-page 100
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[label] ADDLW
Syntax:
[label] ANDWF
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Z
Description:
AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
k
Operation:
(W) + k → (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the eight bit literal ’k’ and the
result is placed in the W register.
f,d
BCF
Bit Clear f
Syntax:
[label] BCF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) + (f) → (destination)
Operation:
0 → (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
Bit 'b' in register 'f' is cleared.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[label] ANDLW
Syntax:
[label] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
ADDWF
Add W and f
Syntax:
[label] ADDWF
Operands:
f,d
k
Operands:
0 ≤ k ≤ 255
Operation:
(W) .AND. (k) → (W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register.
 1999 Microchip Technology Inc.
f,b
f,b
Status Affected:
None
Description:
Bit 'b' in register 'f' is set.
Preliminary
DS30605B-page 101
PIC16C63A/65B/73B/74B
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
Operation:
skip if (f<b>) = 1
00h → (f)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
instruction is executed.
If bit ’b’ is ’1’, then the next instruction
is discarded and a NOP is executed
instead making this a 2TCY instruction.
Description:
The contents of register ’f’ are cleared
and the Z bit is set.
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BTFSC f,b
CLRW
Clear W
Operands:
0 ≤ f ≤ 127
0≤b≤7
Syntax:
[ label ] CLRW
Operands:
None
Operation:
skip if (f<b>) = 0
Operation:
00h → (W)
1→Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected:
None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0 ≤ k ≤ 2047
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
None
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle instruction.
DS30605B-page 102
f
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
COMF
Complement f
GOTO
Unconditional Branch
Syntax:
[ label ] COMF
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 2047
Operation:
(f) → (destination)
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected:
Z
Status Affected:
None
Description:
The contents of register ’f’ are complemented. If ’d’ is 0, the result is stored
in W. If ’d’ is 1, the result is stored
back in register ’f’.
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
DECF
Decrement f
INCF
Increment f
Syntax:
[label] DECF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
Decrement register ’f’. If ’d’ is 0, the
result is stored in the W register. If ’d’
is 1, the result is stored back in register ’f’.
Description:
The contents of register ’f’ are incremented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ’f’ are decremented. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, then a NOP is
executed instead making it a 2TCY
instruction.
Description:
The contents of register ’f’ are incremented. If ’d’ is 0, the result is placed
in the W register. If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead making it a 2TCY
instruction.
 1999 Microchip Technology Inc.
f,d
Preliminary
GOTO k
INCF f,d
INCFSZ f,d
DS30605B-page 103
PIC16C63A/65B/73B/74B
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Description:
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble as 0’s.
IORLW k
MOVLW k
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
(W) .OR. (f) → (destination)
Operation:
(W) → (f)
Operation:
Status Affected:
None
Status Affected:
Z
Description:
Description:
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Move data from W register to register
'f'.
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
None
Status Affected:
Z
Description:
No operation.
Description:
The contents of register f are moved
to a destination dependant upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
DS30605B-page 104
IORWF
f,d
MOVF f,d
MOVWF
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Preliminary
f
NOP
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
RETFIE
Return from Interrupt
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC,
1 → GIE
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
None
Status Affected:
C
Description:
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
Status Affected:
RETFIE
RLF
C
f,d
Register f
RETLW
Return with Literal in W
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k → (W);
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
RETLW k
RRF f,d
C
RETURN
Return from Subroutine
SLEEP
Register f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
TOS → PC
Operation:
Status Affected:
None
Description:
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 13.8 for more details.
RETURN
 1999 Microchip Technology Inc.
Preliminary
SLEEP
DS30605B-page 105
PIC16C63A/65B/73B/74B
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[label]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W
register.
Description:
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
SUBWF
Subtract W from f
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Syntax:
[label]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (destination)
Operation:
(W) .XOR. (f) → (destination)
Status
Affected:
C, DC, Z
Status Affected:
Z
Description:
Description:
Subtract (2’s complement method) W
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd'
is 1, the result is stored back in register 'f'.
SUBLW k
SUBWF f,d
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected:
None
Description:
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the
result is placed in W register. If 'd' is 1,
the result is placed in register 'f'.
DS30605B-page 106
Preliminary
XORLW k
XORWF
f,d
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.0
DEVELOPMENT SUPPORT
®
The PICmicro microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB™ IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
Emulator
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
- KEELOQ
15.1
•
•
•
•
•
•
MPLAB Integrated Development
Environment Software
- The MPLAB IDE software brings an ease of
software development previously unseen in
the 8-bit microcontroller market. MPLAB is a
Windows-based application which contains:
Multiple functionality
- editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
A full featured editor
A project manager
Customizable tool bar and key mapping
A status bar
On-line help
 1999 Microchip Technology Inc.
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
- object code
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
15.2
MPASM Assembler
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device programmers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB
debugging.
MPASM features include:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi purpose source files.
• MPASM directives allow complete control over the
assembly process.
15.3
MPLAB-C17 and MPLAB-C18
C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and integrated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compilers provide symbol information that is compatible with the
MPLAB IDE memory display.
DS30605B-page 107
PIC16C63A/65B/73B/74B
15.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with precompiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes linking easier because single libraries can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
15.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and
debug code outside of the laboratory environment making it an excellent multi-project software development
tool.
15.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30605B-page 108
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcontrollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
15.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER systems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
15.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
15.9
MPLAB-ICD In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Circuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.10
PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
15.11
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
15.12
SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry-level system development.
15.13
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
 1999 Microchip Technology Inc.
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
15.14
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
15.15
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS30605B-page 109
PIC16C63A/65B/73B/74B
15.16
PICDEM-17
The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and
modified using either emulator. Additionally, a generous prototype area is available for user hardware.
15.17
SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
15.18
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS30605B-page 110
 1999 Microchip Technology Inc.
 1999 Microchip Technology Inc.
Software Tools
Emulators
Programmers Debugger
á
á
á
PIC16C5X
á
á á á á
á
á
PIC14000
á
á á á
á
á
PIC12CXXX
á
á á á á
á
á
PICSTARTPlus
Low-Cost Universal Dev. Kit
PRO MATE II
Universal Programmer
á á
á
á
PIC16C8X
á
á á á á
á
á
PIC16C7XX
á
á á á á
á
á
PIC16C7X
á
á á á á
á
á
PIC16F62X
á
á á
PIC16CXXX
á
á á á á
PIC16C6X
á
á á á á
á
á
á
á
á á
á
á
á
á
á
á á
á
á
á
á á
á
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
†
á
MCP2510 CAN Developer’s Kit
PIC16F8XX
á
†
MCRFXXX
á á á
13.56 MHz Anticollision microID
Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
125 kHz microID Developer’s Kit
á á á á
microID™ Programmer’s Kit
PIC16C9XX
á
KEELOQ Transponder Kit
á
KEELOQ® Evaluation Kit
á
PICDEM-17
á á á
á
PICDEM-14A
PIC17C4X
á á
á
†
á
PICDEM-3
á
á á á
**
24CXX/
25CXX/
93CXX
á
PICDEM-2
á
**
á
PICDEM-1
á á á
*
PIC17C7XX
á á
**
HCSXXX
á
SIMICE
MPLAB-ICD In-Circuit Debugger
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/PICMASTER-CE
MPLAB™-ICE
MPASM/MPLINK
MPLAB C18 Compiler
PIC18CXX2
á
*
á
MPLAB C17 Compiler
TABLE 15-1:
Demo Boards and Eval Kits
MPLAB Integrated
Development Environment
PIC16C63A/65B/73B/74B
DEVELOPMENT TOOLS FROM MICROCHIP
MCP2510
á
DS30605B-page 111
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 112
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)........................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
3: PORTD and PORTE not available on the PIC16C63A/73B.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 113
PIC16C63A/65B/73B/74B
FIGURE 16-1: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
PIC16CXXX-20
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 16-2: PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
4.5 V
PIC16LCXXX-04
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30605B-page 114
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-3: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
PIC16CXXX-04
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
Frequency
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 115
PIC16C63A/65B/73B/74B
16.1
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Param
No.
D001
D001A
Sym
VDD
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
-40°C ≤ TA ≤
-40°C ≤ TA ≤ +125°C for extended
Min
Typ†
Max Units
4.0
4.5
VBOR*
–
–
–
5.5
5.5
5.5
V
V
V
–
1.5
–
V
V
Conditions
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
D002*
VDR
D003
VPOR VDD Start Voltage to
ensure internal
Power-on Reset signal
–
VSS
–
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
Power-on Reset signal
0.05
TBD
–
–
–
–
D005
VBOR Brown-out Reset
voltage trip point
3.65
–
4.35
V
–
2.7
5
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 5.5V (Note 4)
–
10
20
mA
HS osc mode
FOSC = 20 MHz, VDD = 5.5V
–
–
–
–
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
–
–
6.0
100
20
150
µA
µA
WDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
D010
IDD
Supply Current
(Note 2, 5)
D013
D020
IPD
Power-down Current
(Note 3, 5)
D021
D021B
D022*
D022A*
Module Differential
Current (Note 6)
∆IWDT Watchdog Timer
∆IBOR Brown-out Reset
See section on Power-on Reset for details
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
BODEN bit set
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30605B-page 116
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.2
DC Characteristics:
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions (unless otherwise stated)
+70°C for commercial
Operating temperature
0°C ≤ TA ≤
+85°C for industrial
-40°C ≤ TA ≤
Min
Typ†
Max Units
2.5
VBOR*
–
–
5.5
5.5
V
V
–
1.5
–
V
V
Conditions
D001
VDD
Supply Voltage
D002*
VDR
RAM Data Retention
Voltage (Note 1)
D003
VPOR VDD Start Voltage to
ensure internal
Power-on Reset signal
–
VSS
–
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
Power-on Reset signal
0.05
TBD
–
–
–
–
D005
VBOR Brown-out Reset
voltage trip point
3.65
–
4.35
V
–
2.0
3.8
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
–
22.5
48
µA
LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
–
–
–
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
–
–
6.0
100
20
150
µA
µA
WDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
D010
IDD
Supply Current
(Note 2, 5)
D010A
D020
D021
D021A
D022*
D022A*
IPD
Power-down Current
(Note 3, 5)
Module Differential
Current (Note 6)
∆IWDT Watchdog Timer
∆IBOR Brown-out Reset
LP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
See section on Power-on Reset for details
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
BODEN bit set
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula
Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 117
PIC16C63A/65B/73B/74B
16.3
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions (unless otherwise stated)
+70°C for commercial
Operating temperature
0°C ≤ TA ≤
+85°C for industrial
-40°C ≤ TA ≤
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 16.1
and Section 16.2
Min
Typ†
Max
Units
Conditions
Input Low Voltage
VIL
I/O ports
D030
D030A
with TTL buffer
VSS
VSS
-
0.15VDD
0.8V
V
V
D031
with Schmitt Trigger buffer
VSS
-
0.2VDD
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
D032
MCLR, OSC1 (in RC mode)
Vss
-
0.2VDD
V
D033
OSC1 (in XT, HS and LP
modes)
Vss
-
0.3VDD
V
Note 1
Input High Voltage
VIH
I/O ports
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
2.0
-
VDD
V
4.5V ≤ VDD ≤ 5.5V
0.25VDD + 0.8V
-
VDD
V
For entire VDD range
0.8VDD
-
VDD
V
For entire VDD range
D042
MCLR
0.8VDD
-
VDD
V
D042A
OSC1 (XT, HS and LP modes)
0.7VDD
-
VDD
V
D043
OSC1 (in RC mode)
0.9VDD
-
VDD
V
I/O ports
-
-
±1
µA
Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
MCLR, RA4/T0CKI
-
-
±5
µA
Vss ≤ VPIN ≤ VDD
D063
OSC1
-
-
±5
µA
Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
50
250
400
µA
VDD = 5V, VPIN = VSS
Note 1
Input Leakage Current
(Notes 2, 3)
D060
D070
IIL
IPURB PORTB weak pull-up current
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be
driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30605B-page 118
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial) (CONTINUED)
DC CHARACTERISTICS
Param
No.
Sym
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec
Section 16.1 and Section 16.2
Characteristic
Min
Typ†
Max
Units
Conditions
-
-
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
-
-
0.6
V
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
-
-
0.6
V
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
-
-
0.6
V
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
VDD-0.7
-
-
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7
-
-
V
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
VDD-0.7
-
-
V
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7
-
-
V
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
-
-
8.5
V
RA4 pin
-
-
15
pF
In XT, HS and LP modes
when external clock is used to
drive OSC1.
Output Low Voltage
D080
VOL
D083
I/O ports
OSC2/CLKOUT (RC osc mode)
Output High Voltage
D090
VOH
D092
D150*
I/O ports (Note 3)
OSC2/CLKOUT (RC osc mode)
VOD
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
D101
CIO
All I/O pins and OSC2 (in RC mode)
-
-
50
pF
D102
Cb
SCL, SDA in I2C mode
-
-
400
pF
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be
driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 119
PIC16C63A/65B/73B/74B
16.4
AC (Timing) Characteristics
16.4.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
DS30605B-page 120
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 16-1
apply to all timing specifications unless otherwise
noted. Figure 16-4 specifies the load conditions for the
timing specifications.
TABLE 16-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤+125°C for extended
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2. LC parts operate for commercial/industrial temperatures only.
FIGURE 16-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464Ω
CL = 50 pF
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
CL = 15 pF
for OSC2 output
Note 1: PORTD and PORTE are not implemented on the PIC16C63A/73B.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 121
PIC16C63A/65B/73B/74B
16.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-5: EXTERNAL CLOCK TIMING
Q1
Q4
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 16-2:
Param
No.
1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc External CLKIN Frequency
(Note 1)
Oscillator Frequency
(Note 1)
1
Tosc
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
2
3*
4*
TCY
Instruction Cycle Time (Note 1)
TosL, External Clock in (OSC1) High or
TosH Low Time
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
Min
Typ†
Max
Units
Conditions
DC
—
4
MHz RC and XT osc modes
DC
—
4
MHz HS osc mode (-04)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz
DC
—
4
MHz RC osc mode
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz
250
—
—
ns
RC and XT osc modes
250
—
—
ns
HS osc mode (-04)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
250
—
—
ns
RC osc mode
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
—
DC
ns
TCY = 4/FOSC
100
—
—
ns
XT oscillator
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
—
—
25
ns
XT oscillator
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
LP osc mode
LP osc mode
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When
an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
DS30605B-page 122
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-6: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
12
19
14
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH Port in valid before CLKOUT ↑
Tosc + 200
—
—
ns
Note 1
16*
TckH2ioI
0
—
—
ns
Note 1
17*
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18*
TosH2ioI
100
—
—
ns
200
—
—
ns
18A*
Port in hold after CLKOUT ↑
OSC1↑ (Q2 cycle) to Port PIC16CXX
input invalid (I/O in hold
PIC16LCXX
time)
19*
TioV2osH Port input valid to OSC1↑ (I/O in setup
time)
0
—
—
ns
20*
TioR
PIC16CXX
—
10
40
ns
PIC16LCXX
—
—
80
ns
PIC16CXX
—
10
40
ns
PIC16LCXX
—
—
80
ns
Port output rise time
20A*
21*
TioF
Port output fall time
21A*
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 123
PIC16C63A/65B/73B/74B
FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 16-4 for load conditions.
FIGURE 16-8: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 16-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param
No.
Sym
Characteristic
30
TmcL
31*
Min
Typ†
Max
Units
Conditions
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +125°C
Twdt
Watchdog Timer Time-out
Period (No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +125°C
32
Tost
Oscillation Start-up Timer
Period
—
1024
TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +125°C
34
TIOZ
I/O Hi-impedance from
MCLR Low or WDT reset
—
—
2.1
µs
35
TBOR
Brown-out Reset Pulse
Width
100
—
—
µs
VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605B-page 124
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-5:
Param
No.
Sym
40*
Tt0H
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41*
Tt0L
T0CKI Low Pulse Width
No Prescaler
42*
Tt0P
T0CKI Period
No Prescaler
With Prescaler
45*
Tt1H
—
ns
With Prescaler Greater of:
20 or TCY + 40
N
—
—
ns
N = prescale value
(2, 4,..., 256)
—
—
ns
Must also meet
parameter 47
0.5TCY + 20
15
—
—
ns
25
—
—
ns
30
—
—
ns
50
—
—
ns
Synchronous, Prescaler = 1
0.5TCY + 20
—
—
ns
Synchronous, PIC16CXX
Prescaler =
PIC16LCXX
2,4,8
15
—
—
ns
25
—
—
ns
Synchronous
Must also meet
parameter 42
ns
30
—
—
ns
50
—
—
ns
—
—
ns
PIC16CXX
Greater of:
30 OR TCY + 40
N
PIC16LCXX
Greater of:
50 OR TCY + 40
N
PIC16LCXX
48
—
ns
Asynchronous PIC16CXX
Ft1
0.5TCY + 20
Must also meet
parameter 42
—
PIC16LCXX
T1CKI input
period
ns
—
Asynchronous PIC16CXX
Tt1P
ns
—
—
PIC16LCXX
47*
—
—
—
T1CKI High Time Synchronous, Prescaler = 1
T1CKI Low Time
—
10
10
Asynchronous PIC16CXX
Tt1L
0.5TCY + 20
Conditions
TCY + 40
Synchronous, PIC16CXX
Prescaler =
PIC16LCXX
2,4,8
46*
Typ† Max Units
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
60
—
—
100
—
—
ns
ns
DC
—
200
kHz
2Tosc
—
7Tosc
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 125
PIC16C63A/65B/73B/74B
FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
53
54
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
Sym
No.
50*
Characteristic
Min
TccL CCP1 and CCP2 No Prescaler
input low time
With Prescaler PIC16CXX
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16CXX
—
10
25
ns
PIC16LCXX
—
25
45
ns
—
10
25
ns
—
25
45
ns
PIC16LCXX
51*
TccH CCP1 and CCP2 No Prescaler
input high time
With Prescaler PIC16CXX
PIC16LCXX
52*
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise
time
54*
Typ† Max Units Conditions
TccF CCP1 and CCP2 output fall time PIC16CXX
PIC16LCXX
N = prescale
value (1,4, or
16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605B-page 126
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-7:
Param No.
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Sym
Characteristic
Min
Typ†
Max
Units
62*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI WR↑ or CS↑ to data–in
invalid (hold time)
PIC16CXX
20
—
—
ns
PIC16LCXX
35
—
—
ns
64
TrdL2dtV RD↓ and CS↓ to data–out valid
—
—
80
ns
65*
TrdH2dtI RD↑ or CS↑ to data–out invalid
10
—
30
ns
Conditions
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 127
PIC16C63A/65B/73B/74B
FIGURE 16-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-8:
Param
No.
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Symbol
Characteristic
Min
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
TscH
71A
72
TscL
72A
73
Typ† Max Units
SCK input high time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
SCK input low time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
100
—
—
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75
TdoR
SDO data output rise time PIC16CXX
—
10
25
ns
PIC16LCXX
—
20
45
ns
—
10
25
ns
PIC16CXX
—
10
25
ns
PIC16LCXX
—
20
45
ns
—
10
25
ns
73A
76
TdoF
SDO data output fall time
78
TscR
SCK output rise time
(master mode)
79
TscF
80
TscH2doV, SDO data output valid
TscL2doV after SCK edge
SCK output fall time (master mode)
PIC16CXX
—
—
50
ns
PIC16LCXX
—
—
100
ns
Conditions
Note 1
Note 1
Note 1
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605B-page 128
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
LSb
BIT6 - - - - - -1
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-9:
Param
No.
71
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Symbol
TscH
71A
72
TscL
72A
73
Characteristic
Min
Typ† Max Units
SCK input high time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
SCK input low time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
100
—
—
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75
TdoR
SDO data output rise
time
—
10
25
ns
20
45
ns
—
10
25
ns
—
10
25
ns
20
45
ns
10
25
ns
73A
76
TdoF
SDO data output fall time
78
TscR
SCK output rise time
(master mode)
79
TscF
80
TscH2doV, SDO data output valid
TscL2doV after SCK edge
81
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
SCK output fall time (master mode)
PIC16CXX
—
—
PIC16LCXX
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
—
50
ns
—
100
ns
—
—
ns
Conditions
Note 1
Note 1
Note 1
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 129
PIC16C63A/65B/73B/74B
FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
Min
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
—
—
ns
71
TscH
SCK input high time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
TscL
SCK input low time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
100
—
—
ns
71A
72
72A
Typ† Max Units
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75
TdoR
SDO data output rise time PIC16CXX
—
10
25
ns
20
45
ns
73
73A
PIC16LCXX
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time
(master mode)
—
79
TscF
80
TscH2doV, SDO data output valid
TscL2doV after SCK edge
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
PIC16CXX
10
25
ns
20
45
ns
—
10
25
ns
—
—
50
ns
—
100
ns
—
—
ns
PIC16LCXX
SCK output fall time (master mode)
PIC16CXX
PIC16LCXX
1.5TCY + 40
Conditions
Note 1
Note 1
Note 1
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605B-page 130
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 16-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
70
71
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TscH
SCK input high time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
TscL
SCK input low time
(slave mode)
Continuous
1.25TCY + 30
—
—
ns
40
—
—
ns
Note 1
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
ns
Note 1
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75
TdoR
SDO data output rise
time
71A
72
72A
73A
Single Byte
PIC16CXX
—
PIC16LCXX
Typ† Max Units
10
25
ns
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time
(master mode)
PIC16CXX
—
10
25
ns
PIC16LCXX
—
20
45
ns
79
TscF
—
10
25
ns
80
TscH2doV, SDO data output valid
TscL2doV after SCK edge
SCK output fall time (master mode)
PIC16CXX
—
—
50
ns
PIC16LCXX
—
—
100
ns
82
TssL2doV
PIC16CXX
—
—
50
ns
—
—
100
ns
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
—
—
ns
SDO data output valid
after SS↓ edge
PIC16LCXX
Conditions
Note 1
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 131
PIC16C63A/65B/73B/74B
FIGURE 16-16: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-12: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Sym
Characteristic
TSU:STA START condition
90*
Setup time
91*
THD:STA START condition
92*
TSU:STO STOP condition
Hold time
Setup time
THD:STO STOP condition
93
Hold time
Min Typ Max Units
100 kHz mode
4700
—
—
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
100 kHz mode
4700
—
—
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
Conditions
ns
Only relevant for repeated
START condition
ns
After this period the first clock
pulse is generated
ns
ns
*These parameters are characterized but not tested.
FIGURE 16-17: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 16-4 for load conditions.
DS30605B-page 132
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 16-13: I2C BUS DATA REQUIREMENTS
Param.
No.
Sym
100*
THIGH
Characteristic
Clock high time
Min
Max
Units
100 kHz mode
4.0
—
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs
Device must operate at a
minimum of 10 MHz
1.5TCY
—
100 kHz mode
4.7
—
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
µs
Device must operate at a
minimum of 10 MHz
1.5TCY
—
SSP Module
101*
TLOW
Clock low time
SSP Module
102*
103*
90*
91*
106*
107*
92*
109*
110*
TR
Conditions
SDA and SCL rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
SDA and SCL fall
time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10-400 pF
TSU:STA START condition
setup time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Only relevant for repeated
START condition
THD:STA START condition
hold time
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
TSU:DAT Data input setup
time
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
TSU:STO STOP condition
setup time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus free time
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
—
400
pF
TF
TAA
TBUF
Cb
Bus capacitive loading
Cb is specified to be from
10-400 pF
After this period the first
clock pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can start
*These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line
is released.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 133
PIC16C63A/65B/73B/74B
FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
TckH2dtV
120*
Tckrf
121*
Tdtrf
122*
Characteristic
Min
Typ†
Max
Units Conditions
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16CXX
—
—
80
ns
PIC16LCXX
—
—
100
ns
Clock out rise time and fall
time (Master Mode)
PIC16CXX
—
—
45
ns
PIC16LCXX
—
—
50
ns
—
—
45
ns
—
—
50
ns
Data out rise time and fall time PIC16CXX
PIC16LCXX
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 16-19: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
125*
126*
Sym
TdtV2ckL
TckL2dtl
Characteristic
Min
Typ†
Max
Units
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup
time)
15
—
—
ns
Data hold after CK ↓ (DT hold time)
15
—
—
ns
Conditions
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30605B-page 134
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 16-16: A/D CONVERTER CHARACTERISTICS:
PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)
Param
Sym
No.
A01
A02
NR
Characteristic
Resolution
Min
Typ†
Max
Units
PIC16CXX
—
—
8 bits
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LCXX
—
—
8 bits
bit
VREF = VDD = 2.5V
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EABS Total Absolute error
Conditions
A03
EIL
Integral linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05
EFS
Full scale error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF Offset error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
guaranteed
—
—
2.5V
—
VDD + 0.3
V
VSS - 0.3
—
VREF + 0.3
V
A10
—
Monotonicity (Note 3)
A20
VREF Reference voltage
A25
VAIN Analog input voltage
A30
ZAIN Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
A/D conversion PIC16CXX
current (VDD)
PIC16LCXX
—
180
—
µA
—
90
—
µA
10
—
1000
µA
—
—
10
µA
A50
*
†
Note 1:
2:
3:
IREF VREF input current (Note 2)
VSS ≤ VAIN ≤ VREF
Average current consumption when A/D is
on. (Note 1)
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see
Section 12.1.
During A/D Conversion
cycle
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 135
PIC16C63A/65B/73B/74B
FIGURE 16-20: A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 Tcy
(TOSC/2)
(1)
131
Q4
130
A/D CLK
132
7
A/D DATA
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 16-17: A/D CONVERSION REQUIREMENTS
Param
Sym
No.
Characteristic
TAD A/D clock period
130
Min
Typ†
Max
Units
Conditions
PIC16CXX
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
PIC16LCXX
2.0
—
—
µs
TOSC based,
2.5V ≤ VREF ≤ 5.5V
PIC16CXX
2.0
4.0
6.0
µs
A/D RC Mode
PIC16LCXX
3.0
6.0
9.0
µs
A/D RC Mode
131
TCNV Conversion time (not including S/H
time) (Note 1)
11
—
11
TAD
132
TACQ Acquisition time
5*
—
—
µs
The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
1.5 §
—
—
TAD
TSWC Switching from convert → sample time
135
*
†
Note 1:
2:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
ADRES register may be read on the following TCY cycle.
See Section 12.1 for min conditions.
DS30605B-page 136
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
17.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this time.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 137
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 138
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.0
PACKAGING INFORMATION
18.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
AABBCDE
28-Lead CERDIP Windowed
PIC16C73B-04/SP
8/4/9917HAT
Example
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C73B/JW
8/4/9917CAT
Example
28-Lead SOIC
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
AABBCDE
28-Lead SSOP
PIC16C73B-20/SO
8/4/9910/SAA
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C73B
20I/SS025
8/4/9917SBP
AABBCAE
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 139
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
40-Lead PDIP
Example
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead CERDIP Windowed
PIC16C74B-04/P
8/4/9912SAA
Example
PIC16C74B/JW
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
8/4/9905HAT
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16C74B
-20/PT
8/4/9911HAT
44-Lead MQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16C74B
-20/PQ
8/4/9904SAT
44-Lead PLCC
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
DS30605B-page 140
PIC16C74B
-20/L
8/4/9903SAT
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.2
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
β
B1
A1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
28
.100
.150
.130
MAX
MILLIMETERS
NOM
28
2.54
3.56
3.81
3.18
3.30
0.38
7.62
7.94
7.09
7.80
34.16
34.67
3.18
3.30
0.20
0.29
1.02
1.33
0.41
0.48
8.13
8.89
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.160
Molded Package Thickness
A2
.125
.135
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.279
.307
.335
Overall Length
D
1.345
1.365
1.385
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.040
.053
.065
Lower Lead Width
B
.016
.019
.022
Overall Row Spacing
eB
.320
.350
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
 1999 Microchip Technology Inc.
Preliminary
MAX
4.06
3.43
8.26
8.51
35.18
3.43
0.38
1.65
0.56
10.92
15
15
DS30605B-page 141
PIC16C63A/65B/73B/74B
18.3
28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
D
W2
2
n
1
W1
E
A2
A
c
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Ceramic Package Height
Standoff
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
Window Length
*Controlling Parameter
JEDEC Equivalent: MO-058
Drawing No. C04-080
DS30605B-page 142
B1
B
A1
eB
A
A2
A1
E
E1
D
L
c
B1
B
eB
W1
W2
MIN
.170
.155
.015
.300
.285
1.430
.135
.008
.050
.016
.345
.130
.290
INCHES*
NOM
28
.100
.183
.160
.023
.313
.290
1.458
.140
.010
.058
.019
.385
.140
.300
Preliminary
MAX
.195
.165
.030
.325
.295
1.485
.145
.012
.065
.021
.425
.150
.310
p
MILLIMETERS
NOM
28
2.54
4.32
4.64
3.94
4.06
0.38
0.57
7.62
7.94
7.24
7.37
36.32
37.02
3.43
3.56
0.20
0.25
1.27
1.46
0.41
0.47
8.76
9.78
3.30
3.56
7.37
7.62
MIN
MAX
4.95
4.19
0.76
8.26
7.49
37.72
3.68
0.30
1.65
0.53
10.80
3.81
7.87
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.4
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
A1
MIN
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MIN
Number of Pins
Pitch
Overall Height
A
.093
.104
Molded Package Thickness
A2
.088
.094
Standoff
A1
.004
.012
Overall Width
E
.394
.420
Molded Package Width
E1
.288
.299
Overall Length
D
.695
.712
Chamfer Distance
h
.010
.029
Foot Length
L
.016
.050
φ
Foot Angle Top
0
8
c
Lead Thickness
.009
.013
Lead Width
B
.014
.020
α
Mold Draft Angle Top
0
15
β
Mold Draft Angle Bottom
0
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
 1999 Microchip Technology Inc.
Preliminary
MAX
2.64
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
0.33
0.51
15
15
DS30605B-page 143
PIC16C63A/65B/73B/74B
18.5
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
A
c
A2
φ
A1
L
β
Units
Dimension Limits
n
p
MIN
INCHES
NOM
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
.013
5
5
MAX
MILLIMETERS*
NOM
MAX
28
0.66
1.73
1.85
1.98
1.63
1.73
1.83
0.05
0.15
0.25
7.59
7.85
8.10
5.11
5.25
5.38
10.06
10.20
10.34
0.56
0.75
0.94
0.10
0.18
0.25
0.00
101.60
203.20
0.25
0.32
0.38
0
5
10
0
5
10
MIN
Number of Pins
Pitch
Overall Height
A
.068
.078
Molded Package Thickness
A2
.064
.072
Standoff
A1
.002
.010
Overall Width
E
.299
.319
Molded Package Width
.201
.212
E1
Overall Length
D
.396
.407
Foot Length
L
.022
.037
c
Lead Thickness
.004
.010
φ
Foot Angle
0
8
Lead Width
B
.010
.015
α
Mold Draft Angle Top
0
10
β
Mold Draft Angle Bottom
0
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS30605B-page 144
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.6
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
α
2
1
n
E
A2
A
L
c
β
B1
A1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
40
.100
.175
.150
MAX
MILLIMETERS
NOM
40
2.54
4.06
4.45
3.56
3.81
0.38
15.11
15.24
13.46
13.84
51.94
52.26
3.05
3.30
0.20
0.29
0.76
1.27
0.36
0.46
15.75
16.51
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.160
.190
Molded Package Thickness
A2
.140
.160
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.595
.600
.625
Molded Package Width
E1
.530
.545
.560
Overall Length
D
2.045
2.058
2.065
Tip to Seating Plane
L
.120
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.030
.050
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
eB
.620
.650
.680
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
 1999 Microchip Technology Inc.
Preliminary
MAX
4.83
4.06
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
15
DS30605B-page 145
PIC16C63A/65B/73B/74B
18.7
40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
W
D
2
1
n
E
A2
L
c
B1
B
eB
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Ceramic Package Height
Standoff
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
*Controlling Parameter
JEDEC Equivalent: MO-103
Drawing No. C04-014
DS30605B-page 146
A
A2
A1
E
E1
D
L
c
B
B1
eB
W
MIN
.185
.155
.030
.595
.514
2.040
.135
.008
.050
.016
.610
.340
INCHES*
NOM
40
.100
.205
.160
.045
.600
.520
2.050
.140
.011
.053
.020
.660
.350
Preliminary
MAX
.225
.165
.060
.625
.526
2.060
.145
.014
.055
.023
.710
.360
p
MILLIMETERS
NOM
40
2.54
4.70
5.21
3.94
4.06
0.76
1.14
15.11
15.24
13.06
13.21
51.82
52.07
3.43
3.56
0.20
0.28
1.27
1.33
0.41
0.51
15.49
16.76
8.64
8.89
MIN
MAX
5.72
4.19
1.52
15.88
13.36
52.32
3.68
0.36
1.40
0.58
18.03
9.14
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.8
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45 °
α
A
c
φ
β
L
A1
A2
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
n1
A
A2
A1
L
(F)
φ
E
D
E1
D1
c
B
CH
α
β
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.004
.012
.025
5
5
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039
3.5
.472
.472
.394
.394
.006
.015
.035
10
10
MAX
.047
.041
.006
.030
7
.482
.482
.398
.398
.008
.017
.045
15
15
MILLIMETERS*
NOM
44
0.80
11
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.09
0.15
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
15
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 147
PIC16C63A/65B/73B/74B
18.9
44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP)
E
E1
#leads=n1
p
D1 D
2
1
B
n
CH x 45°
c
A
β
φ
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
n1
A
A2
A1
L
(F)
φ
E
D
E1
D1
c
B
CH
α
β
MIN
.079
.077
.002
.029
0
.510
.510
.390
.390
.005
.012
.025
5
5
α
A1
(F)
INCHES
NOM
44
.031
11
.086
.080
.006
.035
.063
3.5
.520
.520
.394
.394
.007
.015
.035
10
10
MAX
.093
.083
.010
.041
7
.530
.530
.398
.398
.009
.018
.045
15
15
A2
MILLIMETERS*
NOM
44
0.80
11
2.00
2.18
1.95
2.03
0.05
0.15
0.73
0.88
1.60
0
3.5
12.95
13.20
12.95
13.20
9.90
10.00
9.90
10.00
0.13
0.18
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
2.35
2.10
0.25
1.03
7
13.45
13.45
10.10
10.10
0.23
0.45
1.14
15
15
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-022
Drawing No. C04-071
DS30605B-page 148
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
18.10
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
CH1 x 45 °
CH2 x 45°
α
A3
A2
35°
A
B1
B
c
β
E2
Units
Dimension Limits
n
p
A1
p
D2
INCHES*
NOM
44
.050
11
.165
.173
.145
.153
.028
.020
.024
.029
.040
.045
.000
.005
.685
.690
.685
.690
.650
.653
.650
.653
.590
.620
.590
.620
.008
.011
.026
.029
.013
.020
0
5
0
5
MIN
MAX
MILLIMETERS
NOM
44
1.27
11
4.19
4.39
3.68
3.87
0.71
0.51
0.61
0.74
1.02
1.14
0.00
0.13
17.40
17.53
17.40
17.53
16.51
16.59
16.51
16.59
14.99
15.75
14.99
15.75
0.20
0.27
0.66
0.74
0.33
0.51
0
5
0
5
MIN
Number of Pins
Pitch
Pins per Side
n1
Overall Height
A
.180
.160
Molded Package Thickness
A2
.035
Standoff
A1
A3
Side 1 Chamfer Height
.034
Corner Chamfer 1
CH1
.050
Corner Chamfer (others)
CH2
.010
Overall Width
E
.695
Overall Length
D
.695
Molded Package Width
E1
.656
Molded Package Length
D1
.656
Footprint Width
E2
.630
Footprint Length
D2
.630
c
Lead Thickness
.013
Upper Lead Width
B1
.032
Lower Lead Width
B
.021
α
Mold Draft Angle Top
10
β
Mold Draft Angle Bottom
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
 1999 Microchip Technology Inc.
Preliminary
MAX
4.57
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
10
DS30605B-page 149
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 150
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX A:
REVISION HISTORY
Version
Date
Revision Description
A
7/98
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234D, and
the PIC16C7X Data Sheet, DS30390E.
B
1/99
Corrections to Version A data sheet for technical accuracy.
Added data:
• Operation of the SMP and CKE bits of the SSPSTAT register in I2C mode
have been specified
• Frequency vs. VDD graphs for device operating area (in Electrical Specifications)
• Formula for calculating A/D acquisition time, TACQ (in the A/D section)
• Brief description of instructions
Removed data (see PICmicroTM Mid-Range MCU Family Reference Manual,
DS33023A, for additional data):
• USART Baud Rate Tables (formulas for calculating baud rate remain)
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Difference
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
A/D
no
no
5 channels, 8 bits
8 channels, 8 bits
Parallel Slave Port
no
yes
no
yes
Packages
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 151
PIC16C63A/65B/73B/74B
APPENDIX C:
DEVICE MIGRATIONS PIC16C63/65A/73A/74A → PIC16C63A/65B/73B/74B
This document is intended to describe the functional differences and the electrical specification differences that are
present when migrating from one device to the next. Table 1 shows functional differences, while Table 2 shows electrical
and timing differences.
Note:
Even though compatible devices are specified to be tested to the same electrical specification, the device
characteristics may be different from each other (due to process differences). For systems that were
designed to the device specifications, these process differences should not cause any issues in the application. For systems that did not tightly meet the electrical specifications, the process differences may cause
the device to behave differently in the application.
Note:
While there are no functional or electrical changes to the device oscillator specifications, the user should
verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/
or the oscillator mode may be required.
TABLE C-1:
No.
FUNCTIONAL DIFFERENCES
Module
Differences from PIC16C63/65A/73A/74A
H/W S/W Prog.
CCP Special Event Trigger clears Timer1.
—
✔
—
Compare mode drives pin correctly.
—
✔
—
Writing to TMR1L does not affect TMR1H.
—
✔
—
WDT/TMR0 prescaler assignment changes do not affect TMR0 count.
—
✔
—
TMR2 SPI clock synchronized to start of SPI Transmission.
—
✔
—
6
Can now transmit multiple words in SPI mode.
—
✔
—
7
Supports all four SPI modes. (Now uses SSP vs BSSP module.)
See SSP module in the PICmicro™ Mid-Range MCU Family Reference Manual
(DS33023A).
—
✔
—
8
I2C no longer generates ACK pulses when module is enabled.
—
✔
—
1
CCP
2
3
Timers
4
5
SSP
9
USART
Async receive errors due to BRGH setting corrected.
—
✔
—
10
A/D
VREF=VDD when all inputs are configured as digital.
This allows conversion of digital inputs. (A/D on PIC16C73X/74X only.)
—
✔
—
H/W - Issues may exist with regard to the application circuits.
S/W - Issues may exist with regard to the user program.
Prog. - Issues may exist when writing the program to the controller.
DS30605B-page 152
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE C-2:
Param
No.
SPECIFICATION DIFFERENCES
PIC16C63/65A/73A/74A
Symbol
Core
D001
D001A
VDD
D005
D150*
Bvdd
Vod
PIC16C63A/65B/73B/74B
Characteristic
Unit
Min
Typ†
Max
Min
Typ†
Max
4.0
—
—
—
6.0
—
4.0
VBOR(1)
—
—
5.5
5.5
V
V
Brown-out Reset Voltage
Open-Drain High Voltage on
RA4
3.7
—
4.0
—
4.3
14.0
3.65
-
—
—
4.35
8.5
V
V
Supply Voltage
A/D Converter
A20
VREF
Reference voltage
3.0
—
VDD + 0.3
2.5
—
VDD + 0.3
V
131
TCNV
Conversion time (Note 2)
(not including S/H time)
—
9.5
(Note 3)
—
11
(Note 4)
—
11
(Note 4)
TAD
—
—
1.25TCY + 30
—
—
ns
—
40
1.25TCY + 30
—
—
—
—
ns
ns
40
—
—
ns
SSP in SPI mode
71
TscH
71A
72
TscL
72A
73
TdiV2scH
TdiV2scL
T B 2B
73A
(Note 5)
74
TscH2diL
TscL2diL
75
TdoR
78
TscR
80
TscH2doV
TscL2doV
SCK input high
Continuous TCY+20
time (slave mode) Single Byte
SCK input low
Continuous TCY+20
time
Single Byte
(slave mode)
Setup time of SDI data input to
50
SCK edge
Last clock edge of Byte1 to the
—
1st clock edge of Byte2
Hold time of SDI data input to
50
SCK edge
SDO data output PIC16CXX
—
rise time
PIC16LCXX
SCK output rise PIC16CXX
—
time (master
PIC16LCXX
mode)
SDO data output PIC16CXX
—
valid after SCK
PIC16LCXX
edge
—
SS ↑ after SCK edge
—
—
—
100
—
—
ns
—
—
1.5TCY + 40
—
—
ns
—
—
100
—
—
ns
10
25
10
25
—
—
—
—
10
20
10
20
25
45
25
45
ns
ns
ns
ns
—
50
—
—
—
—
50
100
ns
ns
—
50
1.5TCY + 40
—
—
ns
TscH2ssH
TscL2ssH
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
83
Note 1:
2:
3:
4:
5:
When BOR is enabled, the device will operate until VDD drops below VBOR.
ADRES register may be read on the following TCY cycle.
This is the time that the actual conversion requires.
This is the time from when the GO/DONE bit is set to when the conversion result appears in ADRES.
Specification 73A is only required if specifications 71A and 72A are used.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 153
PIC16C63A/65B/73B/74B
APPENDIX D:
MIGRATION FROM BASELINE TO MIDRANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a midrange device (i.e.,
PIC16CXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1
and PA0 are removed from STATUS register.
Data memory paging is redefined slightly.
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW and SUBLW.
Two instructions, TRIS and OPTION, are being
phased out, although they are kept for compatibility with PIC16C5X.
OPTION and TRIS registers are made addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Registers are reset differently.
Wake up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These timers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change feature.
T0CKI pin is also a port pin (RA4) now.
FSR is made a full 8-bit register.
“In-Circuit Serial Programming” (ICSP) is made
possible. The user can program PIC16CXX
devices using only five pins: VDD, VSS, MCLR/
VPP, RB6 (clock) and RB7 (data in/out).
PCON status register is added with a Power-on
Reset status bit (POR).
Code protection scheme is enhanced, such that
portions of the program memory can be protected, while the remainder is unprotected.
DS30605B-page 154
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed setpoint.
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1.
2.
3.
4.
5.
Preliminary
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION and FSR
registers since these have changed.
Change reset vector to 0000h.
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
INDEX
A
A/D
ADCON0 Register....................................................... 79
ADCON1 Register....................................................... 80
Analog Input Model Block Diagram............................. 82
Analog-to-Digital Converter......................................... 79
Block Diagram............................................................. 81
Configuring Analog Port Pins...................................... 83
Configuring the Interrupt ............................................. 81
Configuring the Module............................................... 81
Conversion Clock........................................................ 83
Conversions ................................................................ 83
Converter Characteristics ......................................... 135
Effects of a Reset........................................................ 83
Faster Conversion - Lower Resolution Tradeoff ......... 83
Internal Sampling Switch (Rss) Impedance ................ 82
Operation During Sleep .............................................. 83
Sampling Requirements.............................................. 82
Source Impedance...................................................... 82
Timing Diagram......................................................... 136
Using the CCP Trigger................................................ 83
Absolute Maximum Ratings .............................................. 113
ACK............................................................................... 61, 63
ADRES Register ........................................................... 17, 79
Application Notes
AN552 (Implementing Wake-up on Key Strokes Using
PIC16CXXX) ............................................................... 31
AN556 (Table Reading Using PIC16CXX................... 26
AN578 (Use of the SSP Module in the I2C Multi-Master
Environment)............................................................... 55
AN607, Power-up Trouble Shooting ........................... 89
Architecture
Overview ....................................................................... 9
Assembler
MPASM Assembler................................................... 107
B
Baud Rate Formula ............................................................. 69
BF ................................................................................. 56, 61
Block Diagrams
A/D .............................................................................. 81
Analog Input Model ..................................................... 82
Capture ....................................................................... 51
Compare ..................................................................... 52
I2C Mode..................................................................... 61
On-Chip Reset Circuit ................................................. 88
PIC16C74 ................................................................... 10
PIC16C74A ................................................................. 10
PIC16C77 ................................................................... 10
PORTC ....................................................................... 33
PORTD (In I/O Port Mode).......................................... 34
PORTD and PORTE as a Parallel Slave Port............. 37
PORTE (In I/O Port Mode).......................................... 35
PWM ........................................................................... 52
RA4/T0CKI Pin............................................................ 29
RB3:RB0 Port Pins ..................................................... 31
RB7:RB4 Port Pins ..................................................... 31
SSP in I2C Mode......................................................... 61
SSP in SPI Mode ........................................................ 58
Timer0/WDT Prescaler ............................................... 39
Timer2......................................................................... 47
USART Receive.......................................................... 72
USART Transmit......................................................... 70
Watchdog Timer.......................................................... 96
BOR bit ......................................................................... 25, 89
BRGH bit ............................................................................. 69
 1999 Microchip Technology Inc.
Brown-out Reset (BOR)
Timing Diagram ........................................................ 124
Buffer Full Status bit, BF..................................................... 56
C
C bit .................................................................................... 19
Capture/Compare/PWM
Capture
Block Diagram .................................................... 51
CCP1CON Register............................................ 50
CCP1IF............................................................... 51
Mode .................................................................. 51
Prescaler ............................................................ 51
CCP Timer Resources................................................ 49
Compare
Block Diagram .................................................... 52
Mode .................................................................. 52
Software Interrupt Mode ..................................... 52
Special Event Trigger ......................................... 52
Special Trigger Output of CCP1 ......................... 52
Special Trigger Output of CCP2 ......................... 52
Interaction of Two CCP Modules................................ 49
Section........................................................................ 49
Special Event Trigger and A/D Conversions .............. 52
Capture/Compare/PWM (CCP)
PWM Block Diagram .................................................. 52
PWM Mode................................................................. 52
Timing Diagram ........................................................ 126
CCP1IF bit .......................................................................... 23
CCP2IE bit .......................................................................... 24
CCP2IF bit .......................................................................... 24
CCPR1H Register......................................................... 17, 49
CCPR1L Register ............................................................... 49
CCPR2H Register............................................................... 17
CCPR2L Register ............................................................... 17
CCPxM0 bit......................................................................... 50
CCPxM1 bit......................................................................... 50
CCPxM2 bit......................................................................... 50
CCPxM3 bit......................................................................... 50
CCPxX bit ........................................................................... 50
CCPxY bit ........................................................................... 50
CKE .................................................................................... 56
CKP .................................................................................... 57
Clock Polarity Select bit, CKP............................................. 57
Clocking Scheme................................................................ 14
Code Examples
Call of a Subroutine in Page 1 from Page 0 ............... 26
Indirect Addressing..................................................... 27
Initializing PORTA ...................................................... 29
Code Protection ............................................................ 85, 98
Computed GOTO................................................................ 26
Configuration Bits ............................................................... 85
CREN bit............................................................................. 68
CS pin................................................................................. 37
D
D/A...................................................................................... 56
Data Memory
Register File Map ....................................................... 16
Data/Address bit, D/A ......................................................... 56
DC bit.................................................................................. 19
DC Characteristics............................................ 116, 118, 119
Development Support ................................................... 5, 107
Device Differences............................................................ 151
Direct Addressing ............................................................... 27
E
Electrical Characteristics .................................................. 113
Errata .................................................................................... 3
DS30605B-page 155
PIC16C63A/65B/73B/74B
F
FERR bit.............................................................................. 68
FSR Register........................................................... 17, 18, 27
G
General Description .............................................................. 5
GIE bit ................................................................................. 93
I
I/O Ports
PORTA........................................................................ 29
PORTB........................................................................ 31
PORTC ....................................................................... 33
PORTD ................................................................. 34, 37
PORTE........................................................................ 35
Section ........................................................................ 29
I2C
Addressing .................................................................. 62
Block Diagram............................................................. 61
I2C Operation .............................................................. 61
Master Mode ............................................................... 65
Mode ........................................................................... 61
Mode Selection ........................................................... 61
Multi-Master Mode ...................................................... 65
Reception .................................................................... 63
Reception Timing Diagram ......................................... 63
SCL and SDA pins ...................................................... 61
Slave Mode ................................................................. 61
Transmission............................................................... 64
I2C (SSP Module)
Timing Diagram, Data ............................................... 132
Timing Diagram, Start/Stop Bits................................ 132
In-Circuit Serial Programming ....................................... 85, 98
INDF Register ......................................................... 17, 18, 27
Indirect Addressing ............................................................. 27
Instruction Cycle.................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Format ............................................................... 99
Instruction Set
ADDLW ..................................................................... 101
ADDWF ..................................................................... 101
ANDLW ..................................................................... 101
ANDWF ..................................................................... 101
BCF ........................................................................... 101
BSF ........................................................................... 101
BTFSC ...................................................................... 102
BTFSS ...................................................................... 102
CALL ......................................................................... 102
CLRF......................................................................... 102
CLRW ....................................................................... 102
CLRWDT................................................................... 102
COMF ....................................................................... 103
DECF ........................................................................ 103
DECFSZ.................................................................... 103
GOTO ....................................................................... 103
INCF.......................................................................... 103
INCFSZ ..................................................................... 103
IORLW ...................................................................... 104
IORWF ...................................................................... 104
MOVF........................................................................ 104
MOVLW .................................................................... 104
MOVWF .................................................................... 104
NOP .......................................................................... 104
RETFIE ..................................................................... 105
RETLW ..................................................................... 105
DS30605B-page 156
RETURN................................................................... 105
RLF ........................................................................... 105
RRF .......................................................................... 105
SLEEP ...................................................................... 105
SUBLW ..................................................................... 106
SUBWF..................................................................... 106
SWAPF ..................................................................... 106
XORLW .................................................................... 106
XORWF .................................................................... 106
Section........................................................................ 99
Summary Table ........................................................ 100
INT Interrupt........................................................................ 94
INTCON Register................................................................ 21
INTEDG bit ................................................................... 20, 94
Internal Sampling Switch (Rss) Impedance........................ 82
Interrupts............................................................................. 85
PortB Change ............................................................. 94
RB7:RB4 Port Change................................................ 31
Section........................................................................ 93
TMR0 .......................................................................... 94
IRP bit ................................................................................. 19
K
KeeLoq Evaluation and Programming Tools ................. 110
L
Loading of PC ..................................................................... 26
M
MCLR............................................................................ 87, 90
Memory
Data Memory .............................................................. 15
Program Memory ........................................................ 15
Program Memory Maps
PIC16C73 ........................................................... 15
PIC16C73A......................................................... 15
PIC16C74 ........................................................... 15
PIC16C74A......................................................... 15
Register File Maps
PIC16C73 ........................................................... 16
PIC16C73A......................................................... 16
PIC16C74 ........................................................... 16
PIC16C74A......................................................... 16
PIC16C76 ........................................................... 16
PIC16C77 ........................................................... 16
MPLAB Integrated Development Environment Software.. 107
O
OERR bit............................................................................. 68
OPCODE ............................................................................ 99
OPTION Register................................................................ 20
OSC selection..................................................................... 85
Oscillator
HS......................................................................... 86, 89
LP ......................................................................... 86, 89
RC .............................................................................. 86
XT ......................................................................... 86, 89
Oscillator Configurations..................................................... 86
Output of TMR2 .................................................................. 47
P
P ......................................................................................... 56
Packaging ......................................................................... 139
Paging, Program Memory................................................... 26
Parallel Slave Port ........................................................ 34, 37
Parallel Slave Port (PSP)
Timing Diagram ........................................................ 127
PCFG0 bit ........................................................................... 80
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PCFG1 bit ........................................................................... 80
PCFG2 bit ........................................................................... 80
PCL Register........................................................... 17, 18, 26
PCLATH .............................................................................. 91
PCLATH Register ................................................... 17, 18, 26
PCON Register ............................................................. 25, 89
PD bit ............................................................................ 19, 87
PICDEM-1 Low-Cost PICmicro Demo Board.................... 109
PICDEM-2 Low-Cost PIC16CXX Demo Board ................. 109
PICDEM-3 Low-Cost PIC16CXXX Demo Board............... 109
PICSTART Plus Entry Level Development System ....... 109
PIE1 Register ...................................................................... 22
PIE2 Register ...................................................................... 24
Pin Functions
MCLR/VPP............................................................. 11, 12
OSC1/CLKIN......................................................... 11, 12
OSC2/CLKOUT..................................................... 11, 12
RA0/AN0 ............................................................... 11, 12
RA1/AN1 ............................................................... 11, 12
RA2/AN2 ............................................................... 11, 12
RA3/AN3/VREF ...................................................... 11, 12
RA4/T0CKI............................................................ 11, 12
RA5/AN4/SS ......................................................... 11, 12
RB0/INT ................................................................ 11, 12
RB1 ....................................................................... 11, 12
RB2 ....................................................................... 11, 12
RB3 ....................................................................... 11, 12
RB4 ....................................................................... 11, 12
RB5 ....................................................................... 11, 12
RB6 ....................................................................... 11, 12
RB7 ....................................................................... 11, 12
RC0/T1OSO/T1CKI .............................................. 11, 13
RC1/T1OSI/CCP2................................................. 11, 13
RC2/CCP1 ............................................................ 11, 13
RC3/SCK/SCL ...................................................... 11, 13
RC4/SDI/SDA ....................................................... 11, 13
RC5/SDO .............................................................. 11, 13
RC6/TX/CK ............................................... 11, 13, ??–77
RC7/RX/DT ............................................... 11, 13, ??–77
RD0/PSP0................................................................... 13
RD1/PSP1................................................................... 13
RD2/PSP2................................................................... 13
RD3/PSP3................................................................... 13
RD4/PSP4................................................................... 13
RD5/PSP5................................................................... 13
RD6/PSP6................................................................... 13
RD7/PSP7................................................................... 13
RE0/RD/AN5............................................................... 13
RE1/WR/AN6 .............................................................. 13
RE2/CS/AN7 ............................................................... 13
VDD ....................................................................... 11, 13
VSS ........................................................................ 11, 13
Pinout Descriptions
PIC16C73 ................................................................... 11
PIC16C73A ................................................................. 11
PIC16C74 ................................................................... 12
PIC16C74A ................................................................. 12
PIC16C76 ................................................................... 11
PIC16C77 ................................................................... 12
 1999 Microchip Technology Inc.
PIR1 Register ..................................................................... 23
PIR2 Register ..................................................................... 24
POP .................................................................................... 26
POR .................................................................................... 89
Oscillator Start-up Timer (OST)............................ 85, 89
Power Control Register (PCON)................................. 89
Power-on Reset (POR)................................... 85, 89, 91
Power-up Timer (PWRT) ............................................ 85
Power-Up-Timer (PWRT) ........................................... 89
TO............................................................................... 87
POR bit ......................................................................... 25, 89
Port RB Interrupt................................................................. 94
PORTA ............................................................................... 91
PORTA Register ........................................................... 17, 29
PORTB ............................................................................... 91
PORTB Register ........................................................... 17, 31
PORTC ............................................................................... 91
PORTC Register........................................................... 17, 33
PORTD ............................................................................... 91
PORTD Register........................................................... 17, 34
PORTE ............................................................................... 91
PORTE Register ........................................................... 17, 35
Power-down Mode (SLEEP)............................................... 97
Power-on Reset (POR)
Timing Diagram ........................................................ 124
PR2 Register ................................................................ 18, 47
PRO MATE II Universal Programmer ............................ 109
Product Identification System ........................................... 163
Program Memory
Paging ........................................................................ 26
Program Memory Maps
PIC16C73 ................................................................... 15
PIC16C73A................................................................. 15
PIC16C74 ................................................................... 15
PIC16C74A................................................................. 15
Program Verification ........................................................... 98
PS0 bit ................................................................................ 20
PS1 bit ................................................................................ 20
PS2 bit ................................................................................ 20
PSA bit................................................................................ 20
PSPIF bit ............................................................................ 23
PSPMODE bit ......................................................... 34, 35, 37
PUSH.................................................................................. 26
R
R/W..................................................................................... 56
R/W bit .................................................................... 62, 63, 64
RBIF bit......................................................................... 31, 94
RBPU bit ............................................................................. 20
RC Oscillator................................................................. 87, 89
RCIF bit .............................................................................. 23
RCSTA Register ................................................................. 68
RD pin................................................................................. 37
Read/Write bit Information, R/W ......................................... 56
Receive Overflow Indicator bit, SSPOV.............................. 57
Register File........................................................................ 15
Register File Map................................................................ 16
DS30605B-page 157
PIC16C63A/65B/73B/74B
Registers
Maps
PIC16C73 ........................................................... 16
PIC16C73A ......................................................... 16
PIC16C74 ........................................................... 16
PIC16C74A ......................................................... 16
Reset Conditions......................................................... 90
SSPSTAT.................................................................... 56
Summary..................................................................... 17
Reset............................................................................. 85, 87
Timing Diagram......................................................... 124
Reset Conditions for Special Registers............................... 90
Revision History ................................................................ 151
RP0 bit .......................................................................... 15, 19
RP1 bit ................................................................................ 19
RX9 bit ................................................................................ 68
RX9D bit.............................................................................. 68
S
S.......................................................................................... 56
SCL ..................................................................................... 61
SEEVAL Evaluation and Programming System ............. 110
Serial Communication Interface (SCI) Module, See USART
Services
One-Time-Programmable (OTP) .................................. 7
Quick-Turnaround-Production (QTP) ............................ 7
Serialized Quick-Turnaround Production (SQTP) ......... 7
Slave Mode
SCL ............................................................................. 61
SDA............................................................................. 61
SLEEP........................................................................... 85, 87
SMP .................................................................................... 56
Software Simulator (MPLAB-SIM)..................................... 108
SPBRG Register ................................................................. 18
Special Features of the CPU............................................... 85
Special Function Registers
PIC16C73 ................................................................... 17
PIC16C73A ................................................................. 17
PIC16C74 ................................................................... 17
PIC16C74A ................................................................. 17
Special Function Registers, Section ................................... 16
SPEN bit.............................................................................. 68
SPI
Block Diagram............................................................. 58
Master Mode Timing ................................................... 59
Serial Clock ................................................................. 58
Serial Data In .............................................................. 58
Serial Data Out ........................................................... 58
Slave Mode Timing ..................................................... 59
Slave Mode Timing Diagram....................................... 59
Slave Select ................................................................ 58
SPI Mode .................................................................... 58
SSPCON ..................................................................... 57
SSPSTAT.................................................................... 56
SPI Clock Edge Select bit, CKE.......................................... 56
SPI Data Input Sample Phase Select bit, SMP................... 56
SREN bit ............................................................................. 68
SSP
Module Overview ........................................................ 55
Section ........................................................................ 55
SSPCON ..................................................................... 57
SSPSTAT.................................................................... 56
SSPADD Register ............................................................... 18
SSPBUF Register ............................................................... 17
SSPCON ............................................................................. 57
SSPCON Register............................................................... 17
SSPEN ................................................................................ 57
SSPIF bit ............................................................................. 23
DS30605B-page 158
SSPM3:SSPM0 .................................................................. 57
SSPOV ......................................................................... 57, 61
SSPSTAT Register ....................................................... 18, 56
Stack................................................................................... 26
Overflows.................................................................... 26
Underflow ................................................................... 26
Start bit, S ........................................................................... 56
STATUS Register ............................................................... 19
Stop bit, P ........................................................................... 56
Synchronous Serial Port Enable bit, SSPEN...................... 57
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 .................................................................. 57
Synchronous Serial Port Module ........................................ 55
Synchronous Serial Port Status Register ........................... 56
T
T0CS bit.............................................................................. 20
T1CKPS0 bit ....................................................................... 43
T1CKPS1 bit ....................................................................... 43
T1CON Register ................................................................. 43
T1OSCEN bit ...................................................................... 43
T1SYNC bit......................................................................... 43
T2CKPS0 bit ....................................................................... 47
T2CKPS1 bit ....................................................................... 47
T2CON Register ................................................................. 47
TAD...................................................................................... 83
Timer0
RTCC.......................................................................... 91
Timing Diagram ........................................................ 125
Timer1
Timing Diagram ........................................................ 125
Timers
Timer0
External Clock .................................................... 40
Interrupt .............................................................. 39
Prescaler ............................................................ 40
Prescaler Block Diagram .................................... 39
Section................................................................ 39
T0CKI ................................................................. 40
T0IF .................................................................... 94
TMR0 Interrupt ................................................... 94
Timer1
Asynchronous Counter Mode ............................. 45
Capacitor Selection ............................................ 45
Operation in Timer Mode.................................... 44
Oscillator............................................................. 45
Prescaler ............................................................ 45
Resetting of Timer1 Registers ............................ 45
Resetting Timer1 using a CCP Trigger Output ... 45
Synchronized Counter Mode .............................. 44
T1CON ............................................................... 43
TMR1H ............................................................... 45
TMR1L................................................................ 45
Timer2
Block Diagram .................................................... 47
Module................................................................ 47
Postscaler........................................................... 47
Prescaler ............................................................ 47
T2CON ............................................................... 47
Timing Diagrams
I2C Reception (7-bit Address)..................................... 63
SPI Master Mode ........................................................ 59
SPI Slave Mode (CKE = 1) ......................................... 59
SPI Slave Mode Timing (CKE = 0) ............................. 59
USART Asynchronous Master Transmission ............. 71
USART Asynchronous Reception............................... 72
USART Synchronous Reception ................................ 76
USART Synchronous Transmission ........................... 75
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Wake-up from Sleep via Interrupt ............................... 98
Timing Diagrams and Specifications................................. 122
A/D Conversion......................................................... 136
Brown-out Reset (BOR) ............................................ 124
Capture/Compare/PWM (CCP)................................. 126
CLKOUT and I/O....................................................... 123
External Clock........................................................... 122
I2C Bus Data ............................................................. 132
I2C Bus Start/Stop Bits.............................................. 132
Oscillator Start-up Timer (OST) ................................ 124
Parallel Slave Port (PSP).......................................... 127
Power-up Timer (PWRT) .......................................... 124
Reset......................................................................... 124
Timer0 and Timer1.................................................... 125
USART Synchronous Receive ( Master/Slave) ........ 134
USART SynchronousTransmission ( Master/Slave) . 134
Watchdog Timer (WDT) ............................................ 124
TMR0 Register .................................................................... 17
TMR1CS bit ........................................................................ 43
TMR1H Register ................................................................. 17
TMR1IF bit .......................................................................... 23
TMR1L Register .................................................................. 17
TMR1ON bit ........................................................................ 43
TMR2 Register .................................................................... 17
TMR2IF bit .......................................................................... 23
TMR2ON bit ........................................................................ 47
TO bit .................................................................................. 19
TOUTPS0 bit....................................................................... 47
TOUTPS1 bit....................................................................... 47
TOUTPS2 bit....................................................................... 47
TOUTPS3 bit....................................................................... 47
TRISA Register ............................................................. 18, 29
TRISB Register ............................................................. 18, 31
TRISC Register ............................................................. 18, 33
TRISD Register ............................................................. 18, 34
TRISE Register ....................................................... 18, 35, 36
TXIF bit ............................................................................... 23
TXSTA Register .................................................................. 67
USART
Asynchronous Mode................................................... 70
Asynchronous Receiver.............................................. 72
Asynchronous Reception............................................ 73
Asynchronous Transmitter.......................................... 70
Baud Rate Generator (BRG) ...................................... 69
Receive Block Diagram .............................................. 72
Sampling..................................................................... 69
Synchronous Master Mode......................................... 74
Timing Diagram, Synchronous Receive ........... 134
Timing Diagram, Synchronous Transmission... 134
Synchronous Master Reception ................................. 76
Synchronous Master Transmission ............................ 74
Synchronous Slave Mode........................................... 77
Synchronous Slave Reception ................................... 77
Synchronous Slave Transmit...................................... 77
Transmit Block Diagram ............................................. 70
UV Erasable Devices............................................................ 7
W
Wake-up from SLEEP......................................................... 97
Watchdog Timer (WDT).................................... 85, 87, 90, 95
Timing Diagram ........................................................ 124
WCOL ................................................................................. 57
WDT ................................................................................... 90
Block Diagram ............................................................ 96
Period ......................................................................... 95
Programming Considerations ..................................... 95
Timeout....................................................................... 91
WR pin ................................................................................ 37
Write Collision Detect bit, WCOL........................................ 57
WWW, On-Line Support ....................................................... 3
Z
Z bit..................................................................................... 19
U
UA ....................................................................................... 56
Universal Synchronous Asynchronous Receiver Transmitter
(USART) ............................................................................. 67
Update Address bit, UA ...................................................... 56
 1999 Microchip Technology Inc.
DS30605B-page 159
PIC16C63A/65B/73B/74B
NOTES:
DS30605B-page 160
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
ON-LINE SUPPORT
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and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events
 1999 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
Preliminary
DS30605B-page 161
PIC16C63A/65B/73B/74B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: PIC16C63A/65B/73B/74B Literature Number: DS30605B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30605B-page 162
Preliminary
 1999 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device
PIC16C6X(1), PIC16C6XT(2);VDD range 4.0V to
PIC16LC6X(1), PIC16LC6XT(2);VDD range 2.5V
PIC16C7X(1), PIC16C7XT(2);VDD range 4.0V to
PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V
Frequency Range
04
20
5.5V
to 5.5V
5.5V
to 5.5V
c)
PIC16C74B -04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
PIC16LC63A - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
PIC16C65B - 20I/P = Industrial temp., PDIP
package, 20MHz, normal VDD limits.
Note 1:
= 4 MHz
= 20 MHz
2:
Temperature Range
blank
I
E
=
0°C to
70°C
= -40°C to +85°C
= -40°C to +125°C
(Commercial)
(Industrial)
(Extended)
Package
JW
PQ
PT
SO
SP
P
L
SS
=
=
=
=
=
=
=
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
C
LC
T
= CMOS
= Low Power CMOS
= in tape and reel - SOIC, SSOP,
PLCC, QFP, TQ and FP
packages only.
Windowed CERDIP
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
PLCC
SSOP
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 1999 Microchip Technology Inc.
Preliminary
DS30605B-page 163
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
After September 1, 1999:
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
42705 Grand River, Suite 190
Novi, MI 48375-1727
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
ASIA/PACIFIC
Hong Kong
Beijing
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Arizona Microchip Technology
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
+45 4420 9895
+45 4420 9910 fax
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
New York
06/17/99
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer fabrication
facilities in January 1997. Our field-programmable PICmicro® 8-bit MCUs,
KEELOQ® code hopping devices, Serial
EEPROMs, related specialty memory products and development systems conform to
the stringent quality standards of the International Standard Organization (ISO).
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 8/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30605B-page 164
Preliminary
 1999 Microchip Technology Inc.
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