UPD78056F,78058F Data Sheet

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD78056F,78058F

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The

µ

PD78056F,78058F reduce the electromagnetic interference (EMI) noise in comparison with the conventional

µ

PD78056F,78058F. The

µ

PD78056F,78058F belong to the

µ

PD78058F Subseries products of the 78K/0 Series.

These microcontrollers include a variety of peripheral hardware, such as an 8-bit resolution A/D converter, 8-bit resolution D/A converter, timer, serial interface, real-time output ports, and interrupt functions.

The

µ

PD78P058FY, a one-time PROM which can be operated in the same supply voltage range as for the mask

ROM version, and various development tools are also available.

Detailed function descriptions are provided in the following user’s manual. Be sure to read them before designing.

µ

PD78058F, 78058FY Subseries User's Manual: U12068E

78K/0 Series User’s Manual-Instruction: U12326E

FEATURES

EMI noise reduction version (The overall peak level is reduced by 5 to 10 dB.)

Large on-chip ROM & RAM

Products

µ

Items

Program Memory

(ROM)

PD78056F

µ

PD78058F

48 Kbytes

60 Kbytes

Internal High-

Speed RAM

1024 bytes

Data Memory

Buffer RAM

32 bytes

Internal

Expansion RAM

None

1024 bytes

Packages

80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12

×

12 mm)

Note

Note This package is available only for the

µ

PD78058F.

External memory expansion space: 64 Kbytes

Minimum instruction execution time can be varied from high-speed (0.4

µ s) to ultra-low-speed (122

µ s)

I/O ports: 69 (N-ch open-drain: 4)

8-bit resolution A/D converter: 8 channels

8-bit resolution D/A converter: 2 channels

Serial interface: 3 channels

Timer: 5 channels

Supply voltage: V

DD

= 2.7 to 6.0 V

APPLICATIONS

Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC, fuzzy home appliances, vending machines, etc.

The information in this document is subject to change without notice.

Document No. U11795EJ2V0DS00 (2nd edition)

Date Published September 1997 N

Printed in Japan

The mark

shows major revised points.

©

1997

2

µ

PD78056F, 78058F

ORDERING INFORMATION

Part Number Package

µ

PD78056FGC-

×××

-3B9

µ

PD78056FGC-

×××

-8BT

µ

PD78058FGC-

×××

-3B9

µ

PD78058FGC-

×××

-8BT

µ

PD78058FGK-

×××

-BE9

80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

80-pin plastic TQFP (fine pitch) (12

×

12 mm)

Caution The

µ

PD78056FGC,

µ

PD78058FGC come in two types of packages (see 12 Package Drawings). For the packages that can be supplied, consult your local NEC sales representative.

Remark

×××

denotes the ROM code number.

µ

PD78056F, 78058F

78K/0 SERIES PRODUCT DEVELOPMENT

These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names.

78K/0 series

Products in mass production

Products under development

Y subseries products are compatible with I 2 C bus.

100-pin

100-pin

100-pin

100-pin

80-pin

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

42/44pin

Control

µ

PD78075B

µ

PD78078

µ

PD78070A

µ

µ

µ

µ

PD780058

PD78058F

PD78054

PD780034

µ

PD780024

µ

PD78014H

µ

PD78018F

µ

PD78014

µ

PD780001

µ

PD78002

µ

PD78083

µ

PD78075BY

µ

PD78078Y

µ

PD78070AY

µ

PD780018AY

µ

PD780058Y

Note

µ

PD78058FY

µ

PD78054Y

µ

PD780034Y

µ

PD780024Y

µ

PD78018FY

µ

PD78014Y

µ

PD78002Y Basic subseries for control

On-chip UART, capable of operating at a low voltage (1.8 V)

64-pin

64-pin

64-pin

Inverter Control

µ

PD780988

µ

PD780964

µ

PD780924 On-chip inverter control circuit and UART, EMI noise reduction version

100-pin

100-pin

80-pin

80-pin

FIP

TM

drive

µ

PD780208

µ

PD780228

µ

PD78044H

µ

PD78044F

Basic subseries for driving FIP, Display output total: 34

100-pin

100-pin

100-pin

LCD drive

µ

PD780308

µ

PD78064B

µ

PD78064

µ

PD780308Y

µ

PD78064Y

Subseries for driving LCDs, On-chip UART

80-pin

80-pin

80-pin

64-pin

IEBus

TM

supported

µ

PD78098B

µ

PD78098

Meter control

µ

PD780973

LV

µ

PD78P0914

Note Under planning

EMI noise reduction version of the

µ

PD78098

The IEBus contorller was added to the

µ

PD78098

On-chip the controller /driver for automobile meter drive

On-chip PWM output, LV digital code decoder, Hsync counter

3

4

µ

PD78056F, 78058F

The major functional differences among the subseries are shown below.

Subseries

Function ROM Timer 8-bit 10-bit 8-bit Serial Interface

Capacity 8-bit 16-bit Watch WDT A/D A/D D/A

I/O V

DD

MIN. External

Value Expansion

Control

µ

PD78075B 32 K-40 K 4ch 1ch

µ

PD78078 48 K-60 K

µ

PD78070A ––

µ

PD780058 24 K-60 K 2ch

1ch 1ch 8ch –– 2ch 3ch (UART: 1ch)

3ch (time-division

UART: 1ch)

µ

PD78058F 48 K-60 K

µ

PD78054 16 K-60 K

µ

PD780034 8 K-32 K

µ

PD780024

––

8ch

8ch

––

––

3ch (UART: 1ch)

3ch (UART: 1ch, time-division 3-wire

: 1ch)

µ

PD78014H

µ

PD78018F 8 K-60 K

µ

PD78014 8 K-32 K

µ

PD780001 8 K

µ

PD78002

µ

PD78083

8 K-16 K

–– ––

1ch

––

––

8ch

2ch

1ch

1ch (UART: 1ch)

Inverter

µ

PD780988 32 K-60 K 3ch

Note 1

–– control

µ

PD780964 8 K-32 K

Note 2

FIP

µ

PD780924

µ

PD780208 32 K-60 K 2ch 1ch 1ch

1ch

1ch

––

8ch

8ch

8ch

––

––

––

––

3ch (UART: 2ch)

2ch (UART : 2ch)

2ch drive

LCD

µ

PD780228 48 K-60 K 3ch ––

µ

PD78044H 32 K-48 K 2ch 1ch

µ

PD78044F 16 K-40 K

µ

PD780308 48 K-60 K 2ch 1ch

––

1ch

1ch 1ch 8ch –– ––

1ch

2 ch

3ch (time-division

UART: 1ch drive

µ

PD78064B 32 K

µ

PD78064 16 K-32 K

IEBus

µ

PD78098B 40 K-60 K 2ch 1ch supported

µ

PD78098

Meter

32 K-60 K

µ

PD780973 24 K-32 K 3ch 1ch control

LV

µ

PD78P0914 32 K 6ch ––

1ch

1ch

––

1ch

1ch

1ch

8ch

5ch

8ch

––

––

––

2ch

––

––

2ch (UART: 1ch)

3ch (UART: 1ch)

2ch (UAR: 1ch)

2ch

88 1.8 V Available

61

68

69

51 1.8 V

53

39

2.7 V

2.0 V

2.7 V

––

53 Available

33 1.8 V ––

47 4.0 V Available

2.7 V

74

72

68

2.7 V

1.8 V

2.7 V

4.5 V

2.7 V

––

57 2.0 V ––

69 2.7 V Available

56 4.5 V ––

54 4.5 V Available

Notes 1. 16-bit timer : 2 channel

10-bit timer : 1 channel

2. 10-bit timer : 1 channel

µ

PD78056F, 78058F

OVERVIEW OF FUNCTION

Product Name

Item

Internal memory

ROM

High-speed RAM

Buffer RAM

Expanded RAM

Memory space

General registers

Minimum instruction execution time When main system clock selected

When subsystem clock selected

Instruction set

I/O ports

A/D converter

D/A converter

Serial interface

Timer

Timer output

Clock output

Buzzer output

Vectoredinterrupt source

Test input

Supply voltage

Operating ambient temperature

Package

Maskable

Non-maskable

Software

µ

PD78056F

µ

PD78058F

48 Kbytes

1024 bytes

60 Kbytes

32 bytes

None 1024 Kbytes

64 Kbytes

8 bits

×

32 registers (8 bits

×

8 registers

×

4 banks)

On-chip instruction execution time cycle modification function

0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (at 5.0-MHz operation)

122

µ s (at 32.768-kHz operation)

• 16-bit operation

• Multiplication/division (8 bits

×

8 bits,16 bits

÷

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD correction, etc.

Total

• CMOS input

: 69

: 0 2

• CMOS I/O : 63

• N-ch open-drain I/O

• 8-bit resolution

×

8 channels

• 8-bit resolution

×

2 channels

: 0 4

• 3-wire serial I/O/SBI/2-wire serial I/O/I 2 C bus mode selectable: 1 channel

• 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive

function): 1 channel

• 3-wire serial I/O/UART mode selectable: 1 channel

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 2 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

3 (14-bit PWM output

×

1)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

5.0 MHz (main system clock: at 5.0-MHz operation)

32.768 kHz (subsystem clock: at 32.768-kHz operation)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (main system clock: at 5.0-MHz operation)

Internal : 13, external : 7

Internal : 1

1

Internal : 1, external : 1

V

DD

= 2.7 to 6.0 V

T

A

= – 40 to + 85

°

C

• 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

• 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

Note

Note

µ

PD78058F only

5

6

µ

PD78056F, 78058F

CONTENTS

1.

PIN CONFIGURATION (TOP VIEW) .............................................................................................. 7

2.

BLOCK DIAGRAM ......................................................................................................................... 9

3 PIN FUNCTIONS .......................................................................................................................... 10

3.1

Port Pins ............................................................................................................................... 10

3.2

Non-port Pins ........................................................................................................................ 12

3.3

Pin I/O Circuits and Recommended Connection of Unused Pins ................................. 14

4.

MEMORY SPACE ............................................................................................................................ 18

5.

PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 19

5.1

Ports ....................................................................................................................................... 19

5.2

Clock Generator .................................................................................................................... 20

5.3

Timer/Event Counter ............................................................................................................ 20

5.4

Clock Output Control Circuit .............................................................................................. 23

5.5

Buzzer Output Control Circuit ............................................................................................ 23

5.6

A/D Converter ........................................................................................................................ 24

5.7

D/A Converter ........................................................................................................................ 25

5.8

Serial Interfaces .................................................................................................................... 25

5.9

Real-Time Output Port Functions ....................................................................................... 27

6.

INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................... 28

6.1

Interrupt Functions ............................................................................................................. 28

6.2

Test Functions ...................................................................................................................... 32

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS .......................................................................... 33

8.

STANDBY FUNCTION .................................................................................................................... 33

9.

RESET FUNCTION .......................................................................................................................... 33

10. INSTRUCTION SET ......................................................................................................................... 34

11. ELECTRICAL SPECIFICATIONS ................................................................................................... 37

12. PACKAGE DRAWINGS .................................................................................................................. 63

13. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 66

APPENDIX A. DEVELOPMENT TOOLS ........................................................................................... 68

APPENDIX B. RELATED DOCUMENTS .......................................................................................... 70

µ

PD78056F, 78058F

1.

PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14

×

14, resin thickness 2.7 mm)

µ

PD78056FGC-

×××

-3B9

µ

PD78058FGC-

×××

-3B9

• 80-pin plastic QFP (14

×

14, resign thickness 1.4 mm)

µ

PD78056FGC-

×××

-8BT

µ

PD78058FGC-

×××

-8BT

• 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

µ

PD78058FGK-

×××

-BE9

P15/ANI5

P16/ANI6

P17/ANI7

AV

SS

P130/ANO0

P131/ANO1

AV

REF1

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P40/AD0

P41/AD1

11

12

13

8

9

10

6

7

4

5

2

3

1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

59

58

57

56

55

54

50

49

48

53

52

51

14

15

16

17

18

19

43

42

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

47

46

45

44

RESET

P127/RTP7

P126/RTP6

P125/RTP5

P124/RTP4

P123/RTP3

P122/RTP2

P121/RTP1

P120/RTP0

P37

P36/BUZ

P35/PCL

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P67/ASTB

P66/WAIT

P65/WR

Cautions 1. Connect directly the Internally Connected (IC) pin to V

SS

.

2. The AV

DD

pin functions as both an A/D converter power supply and a port power supply. When the

µ

PD78056F and 78058F are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

DD pin to another power supply which has the same potential as V

DD

.

3. The AV

SS

pin functions as both an A/D and D/A converter ground and as a port ground. When the

µ

PD78056F and 78058F are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

SS

pin to a ground line other than V

SS

.

7

8

A8 to A15

AD0 to AD7

ANI0 to ANI7

ANO0, ANO1

: Address Bus

: Address/Data Bus

: Analog Input

: Analog Output

ASCK

ASTB

: Asynchronous Serial Clock

: Address Strobe

AV

DD

: Analog Power Supply

AV

REF0

, AV

REF1

: Analog Reference Voltage

AV

SS

BUSY

BUZ

IC

: Analog Ground

: Busy

: Buzzer Clock

: Internally Connected

INTP0 to INTP6 : Interrupt from Peripherals

P00 to P07 : Port0

P10 to P17

P20 to P27

: Port1

: Port2

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

P120 to P127

: Port3

: Port4

: Port5

: Port6

: Port7

: Port12

µ

PD78056F, 78058F

P130, P131

PCL

RD

RESET

: Port13

: Programmable Clock

: Read Strobe

: Reset

RTP0 to RTP7 : Real-Time Output Port

RxD : Receive Data

SB0, SB1 : Serial Bus

SCK0 to SCK2 : Serial Clock

SI0 to SI2

SO0 to SO2

STB

TI00, TI01

TI1, TI2,

TO0 to TO2

TxD

V

DD

: Serial Input

: Serial Output

: Strobe

: Timer Input

: Timer Input

: Timer Output

: Transmit Data

: Power Supply

V

SS

WAIT

WR

X1, X2

XT1, XT2

: Ground

: Wait

: Write Strobe

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

µ

PD78056F, 78058F

2.

BLOCK DIAGRAM

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/

EVENT COUNTER 1

8-bit TIMER/

EVENT COUNTER 2

WATCHDOG TIMER

WATCH TIMER

SERIAL

INTERFACE 0

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/RxD/P70

SO2/TxD/P71

SCK2/ASCK/P72

ANI0/P10 to

ANI7/P17

AV

REF0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

ANO0/P130,

ANO1/P131

AV

REF1

INTP0/P00 to

INTP6/P06

BUZ/P36

PCL/P35

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

78K/0

CPU CORE

ROM

RAM

V

DD

V

SS

AV

DD

AV

SS

IC

Remark The internal ROM and RAM capacity depends on the product.

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT12

PORT13

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

SYSTEM

CONTROL

P00

P01 to P06

T07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P72

P120 to P127

P130, P131

RTP0/P120 to

RTP7/P127

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

X1

X2

XT1/P07

XT2

9

µ

PD78056F, 78058F

3.

PIN FUNCTIONS

3.1

Port Pins (1/2)

Pin Name

P00

P01

P02

P03

P04

P05

P06

P07

Note 1

P10 to P17

I/O

Input

Input/ output

Input

Input/ output

P34

P35

P36

P37

P30

P31

P32

P33

P24

P25

P26

P27

P20

P21

P22

P23

P40 to P47

Input/ output

Input/ output

Input/ output

Port 0

8-bit I/O port

Function

After

Reset

Input Input only

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Alternate

Function

INTP0/TI00

INTP1/TI01

INTP2

INTP3

INTP4

INTP5

INTP6

XT1

ANI0 to ANI7

Input only

Port 1

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Note 2

Port 2

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Input

Input

Port 3

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

TI2

PCL

BUZ

TO0

TO1

TO2

TI1

SI1

SO1

SCK1

STB

BUSY

SI0/SB0

SO0/SB1

SCK0

Port 4

8-bit input/output port.

Input/output can be specified in 8-bit unit.

When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.

Input

AD0 to AD7

Notes 1. When using the P07/XT1 pins as an input port, set 1 in bit 6 (FRC) of the processor clock control register.

On-chip feedback resistor of the subsystem clock oscillator should not be used.

2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, use of the on-chip pullup resistor is cancelled automatically.

10

µ

PD78056F, 78058F

3.1

Port Pins (2/2)

Pin Name

P50 to P57

I/O

Input/ output

P64

P65

P66

P67

P60

P61

P62

P63

P70

P71

P72

Input/ output

Input/ output

P120 to P127 Input/ output

P130, P131

Input/ output

Function

After

Reset

Input

Alternate

Function

A8 to A15 Port 5

8-bit input/output port.

LED can be driven directly.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 6

8-bit input/outport port. Input/output can be specified bit-wise.

N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Input

Port 7

3-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Input

Port 12

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

RD

WR

WAIT

ASTB

SI2/RxD

SO2/TxD

SCK2/ASCK

RTP0 to RTP7

Port 13

2-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

ANO0, ANO1

Caution For pins which also function as port pins, do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept (except for LCD segment output alternate-function pin).

(1) Rewrite the output latch which the pin is used as a port pin.

(2) Change the output level of the pin used as an output pin, even if it is not used as a port pin.

11

µ

PD78056F, 78058F

SI1

SI2

SO0

SO1

SO2

SB0

SB1

SDA0

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

SI0

Input

Input

Output

Input

/output

SDA1

SCK0

SCK1

SCK2

STB

BUSY

RxD

TxD

Input

/output

Output

Input

Input

ASCK

TI00

TI01

TI1

Output

Input

Input

TI2

TO0

Output

TO1

TO2

PCL

Output

BUZ

Output

RTP0 to RTP7 Output

3.2

Non-port Pins (1/2)

Pin Name

AD0 to AD7

I/O

Input

/output

Function

External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified.

Serial interface serial data input.

Serial interface serial data output.

Serial interface serial data input/output.

Serial interface serial clock input/ output

Serial interface automatic transmit/receive strobe output.

Serial interface automatic transmit/receive busy input.

Asynchronous serial interface serial data input.

Asynchronous serial interface serial data output.

Asynchronous serial interface serial clock input.

External count clock input to the 16-bit timer (TM0)

Capture trigger signal input to the capture register (CR00)

External count clock input to the 8-bit timer (TM1)

External count clock input to the 8-bit timer (TM2)

16-bit timer (TM0) output (alternate function as 14-bit PWM output)

8-bit timer (TM1) output

8-bit timer (TM2)

Clock output (for main system clock, subsystem clock trimming).

Buzzer output.

Real-time output port by which data is output in synchronization with a trigger.

Low-order address/data bus at external memory expansion.

Input

Input

Input

Input

Input

Input

After

Reset

Input

Input

Input

Input

Input

Input

Input

Input

Input

Alternate

Function

P26/SO0

P27

P22

P72/ASCK

P23

P24

P70/SI2

P71/SO2

P72/SCK2

P00/INTP0

P01/INTP1

P33

P34

P30

P31

P32

P35

P36

P120 to P127

P20

P70/RxD

P26/SB1

P21

P71/TxD

P25/SI0

P26/SO0

P25/SI0

P00/TI00

P01/TI01

P02

P03

P04

P05

P06

P25/SB0

Input P40 to P47

12

µ

PD78056F, 78058F

3.2

Non-port Pins (2/2)

Pin Name

A8 to A15

RD

WR

WAIT

ASTB

I/O

Output

Output

Input

Output

ANI0 to ANI7

ANO0, ANO1

AV

REF0

AV

REF1

AV

DD

AV

SS

RESET

X1

X2

XT1

XT2

V

DD

V

SS

IC

Input

Input

Output

Input

Input

Input

Input

Function

High-order address bus at external memory expansion.

External memory read operation strobe signal output.

External memory write operation strobe signal output.

After

Reset

Input

Input

Wait insertion at external memory access.

Strobe output which latches the address information output at port 4 to access external memory.

A/D converter analog input.

D/A converter analog output.

A/D converter reference voltage input.

D/A converter reference voltage input.

A/D converter analog power supply (shared with the port power supply)

A/D and D/A converter ground potential (shared with the port ground potential)

System reset input.

Main system clock oscillation crystal connection.

Input

Input

Subsystem clock oscillation crystal connection.

Positive power supply (except for port).

Ground potential (except for port).

Internally connected. Connect directly to V

SS

.

Input

Input

Input

Alternate

Function

P50 to P57

P64

P65

P66

P67

P10 to P17

P130, P131

P07

Cautions 1.

The AV

DD

pin functions as both an A/D converter power supply and a port power supply. When

the

µ

PD78056F and 78058F are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

DD

pin to another power supply which has the same potential as V

DD

.

2.

The AV

SS

pin functions as both an A/D converter and D/A converter ground and as a port ground. When the

µ

PD78056F and 78058F are used in applications where the noise generated inside the microcontroller needs to be reduced, connect the AV

SS

pin to a ground line other than

V

SS

.

13

µ

PD78056F, 78058F

3.3

Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, see Figure 3-1.

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60 to P63

P64/RD

P65/WR

P66/WAIT

P67/ASTB

Pin Name

P00/INTP0/TI00

P01/INTP1/TI01

P02/INTP2

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

P07/XT1

P10/ANI0 to P17/ANI7

Table 3-1. Input/Output Circuit Type of Each Pin (1/2)

Input/output

Circuit Type

2

8-D

I/O

Input

Input/output

Recommended Connection when not Used

Connect to V

SS

.

Independently connect to V

SS

through resistor.

16

11-C

Input

Input/output

Connect to V

DD

.

Independently connect to V

DD

or V

SS

through resistor.

8-D

5-J

8-D

5-J

8-D

10-C

5-J

8-D

5-J

5-O

5-J

13-I

5-J

Independently connect to V

DD

through resistor.

Independently connect to V

DD

or V

SS

through resistor.

Independently connect to V

DD

through resistor.

Independently connect to V

DD

or V

SS

through resistor.

14

Pin Name

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P120/RTP0 to

P127/RTP7

P130/ANO0 ,

P131/ANO1

RESET

XT2

AV

REF0

AV

REF1

AV

DD

AV

SS

IC

µ

PD78056F, 78058F

Table 3-1. Input/Output Circuit Type of Each Pin (2/2)

Input/output

Circuit Type

8-D

5-J

8-D

5-J

I/O

Input/ output

Recommended Connection when not Used

Independently connect to V

DD

or V

SS

through resistor.

12-B

2

16

Input

Independently connect to V

SS

through resistor.

Leave open.

Connect to V

SS

.

Connect to V

DD

.

Connect to another power supply which has the same potential as V

DD

.

Connect to another ground line which has the same potential as V

SS

.

Connect directly to V

SS

.

15

16

µ

PD78056F, 78058F

Type 2

IN

Schmitt-Triggered Input with Hysteresis Characteristic

Type 5-J pullup enable data output disable input enable

Type 5-O pullup enable data output disable

Figure 3-1. Pin Input/Output Circuits (1/2)

Type 8-D

AV

DD pullup enable data output disable

Type 10-C pullup enable

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS data open drain output disable

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

AV

DD

AV

DD

P-ch

P-ch

IN/OUT

N-ch

AV

SS

Type 11-C pullup enable data

AV

DD

AV

DD

P-ch

P-ch

IN/OUT output disable

Comparator

+

-

P-ch

N-ch

AV

SS

AV

SS

N-ch

V

REF

(Threshold Voltage) input enable

µ

PD78056F, 78058F

Figure 3-1. Pin Input/Output Circuits (2/2)

Type 12-B

AV

DD pullup enable

P-ch

AV

DD data

P-ch

IN/OUT output disable input enable

AV

SS

N-ch

Analog Output

Voltage

P-ch

N-ch

AV

SS

Type 13-I data output disable

Mask

Option

AV

DD

IN/OUT

N-ch

AV

SS

AV

DD

RD

P-ch

Type 16

XT1 feed back cut-off

P-ch

XT2

Middle-High Voltage Input Buffer

17

µ

PD78056F, 78058F

4.

MEMORY SPACE

Figure 4-1 shows the memory map of the

µ

PD78056F,78058F.

Figure 4-1. Memory Map

Data Memory

Space

FB00H

FAFFH

FAE0H

FADFH

FAC0H

FABFH

FA80H

FA7FH

FFFFH

Special Function Registers

(SFR) 256

×

8 bits

FF00H

FEFFH

FEE0H

FEDFH

General Registers

32

×

8 bits

Internal High-Speed

RAM

1024

×

8 bits

Use Prohibited

Buffer RAM 32

×

8 bits

Use Prohibited

External Memory

Program Memory

Space nnnnH + 1 nnnnH

Internal ROM

Note 3

0000H

FA7FH

F800H

F7FFH

Use Prohibited

Internal Expanded RAM

1024

×

8 bits

F400H

F3FFH

Use Prohibited

Note 2

F000H nnnnH

1000H

0FFFH

Program Area

CALLF Entry Area

0800H

07FFH

Program Area

0080H

007FH

CALLT Table Area

0040H

003FH

Vector Table Area

0000H

Note 1

Notes 1.

µ

PD78058F only

2. When the external device expansion function is used with the

µ

PD78058F, set the internal ROM capacity to 56 Kbytes or less using the memory size switching register (IMS).

3. The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the table below).

Target Product

µ

PD78056F

µ

PD78058F

Internal ROM Last Address nnnnH

BFFFH

EFFFH

18

µ

PD78056F, 78058F

5.

PERIPHERAL HARDWARE FUNCTION FEATURES

5.1

Ports

The following 3 types of I/O ports are available.

• CMOS input (P00, P07)

• CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13)

• N-ch open-drain input/output (P60 to P63)

Total

Table 5-1. Port Functions

Name

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 12

Port 13

Pin Name

P00, P07

P01 to P06

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P63

P64 to P67

P70 to P72

P120 to P127

P130, P131

Function

Dedicated input port pins

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable in 8-bit units.

When used as input port pins, on-chip pull-up resistor can be used by software.

Test input flag (KRIF) is set to 1 by falling edge detection.

Input/output port pins. Input/output specifiable bit-wise.

When used as input port pins, on-chip pull-up resistor can be used by software.

LED direct drive capability.

N-channel open-drain input/output port pins. Input/output specifiable bit-wise.

On-chip pull-up resistor can be used by mask option.

LED direct drive capability.

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

Input/output port pins. Input/output specifiable bit-wise.

When used as input/output port pins, on-chip pull-up resistor can be used by software.

: 2

: 63

: 4

: 69

19

µ

PD78056F, 78058F

5.2

Clock Generator

Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable.

The minimum instruction execution time can also be changed.

• 0.4

µ s/0.8

µ s/1.6

µ s/3.2

µ s/6.4

µ s/12.8

µ s (main system clock: at 5.0-MHz operation)

• 122

µ s (subsystem clock: at 32.768-kHz operation)

Figure 5-1. Clock Generator Block Diagram

XT1/P07

XT2

X1

X2

Subsystem

Clock

Oscillator f

XT

1

2

Main System

Clock

Oscillator f

X

STOP

Divider f

X

2

Selector f

XX f

XX

2

Prescaler f

XX

2

2 f

XX

2

3 f

XX f

XT

2

4

2

Selector

Prescaler

Standby

Control

Circuit

Circuit

To INTP0

Sampling Clock

Watch Timer, Clock

Output Function

Clock to Peripheral

Hardware

Wait Control

CPU Clock

(f

CPU

)

5.3

Timer/Event Counter

5 timer/event counter channels are incorporated.

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter

• Watch timer

• Watchdog timer

: 2 channels

: 1 channel

: 1 channel

Table 5-2. Operation of Timer/Event Counter

16-Bit Timer/Event Counter

8-Bit Timer/Event Counter Watch Timer Watchdog Timer

Operation mode

Interval timer

External event counter

Function

Timer output

PWM output

Pulse width measurement

Square wave output

One-shot pulse output

Interrupt request

Test input

1 channel

1 channel

1 output

1 output

2 input

1 output

1 output

2

2 channels

2 channels

2 outputs

2 outputs

2

1 channel

1

1 input

1 channel

1

20

µ

PD78056F, 78058F

Figure 5-2. 16-Bit Timer/Event Counter Block Diagram

Internal Bus

TI01/P01/INTP1

Selector

16-Bit Capture/

Compare Register

(CR00)

Watch Timer

Output

2f

XX f

XX f

XX

/2 f

XX

/2

2

TI00/P00/INTP0

Match

PWM pulse

Output

Control

Circuit

Edge

Detction

Circuit

Selector

16-Bit Timer Register

(TM0)

Clear

Match

Selector

16-Bit Capture/

Compare Register

(CR01)

INTP1

INTTM00

Output Control

Circuit

TO0/P30

INTTM01

INTP0

Internal Bus

Figure 5-3. 8-Bit Timer/Event Counter Block Diagram

Internal Bus f xx

/2-f xx

/2

9 f xx

/2

11

TI1/P33 f xx

/2-f xx

/2

9 f xx

/2

11

TI2/P34

8-Bit Compare

Register (CR10)

Match

8-Bit Compare

Register (CR20)

Match

Selector

8-Bit Timer

Register 1 (TM1)

Clear

Selector

8-Bit Timer

Register 2 (TM2)

Clear

Selector

Selector

Internal Bus

INTTM1

Selector

Output

Control

Circuit

TO2/P32

INTTM2

Output

Control

Circuit

TO1/P31

21

µ

PD78056F, 78058F

f

XX

/2

7 f

XT

Selector f w

Figure 5-4. Watch Timer Block Diagram

Prescaler

Selector 5-Bit Counter f

2 w

14

Selector

INTWT f w

2 13 f w

2

4 f w

2

5 f w

2

6 f w

2

7 f

2 w

8 f w

2

9

Selector

INTTM3

To 16-Bit Timer/

Event Counter

Figure 5-5. Watchdog Timer Block Diagram

f xx

2

3

Prescaler f xx

2

4 f xx

2

5 f xx

2

6 f xx

2

7 f xx

2

8 f xx

2

9 f xx

2

11

Selector 8-Bit Counter

INTWDT

Maskable

Interrupt Request

Control

Circuit

RESET

INTWDT

Non-Maskable

Interrupt Request

22

µ

PD78056F, 78058F

5.4

Clock Output Control Circuit

Clock with the following frequencies can be output as clock output.

• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: at

5.0-MHz operation)

• 32.768 kHz (subsystem clock: at 32.768-kHz operation)

Figure 5-6. Clock Output Control Block Diagram

f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XT

Selector

Synchronization

Circuit

Output Control

Circuit

PCL/P35

5.5

Buzzer Output Control Circuit

Clock with the following frequencies can be output as buzzer output.

• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock: at 5.0-MHz operation)

Figure 5-7. Buzzer Output Control Circuit Block Diagram

f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Selector

Output Control

Circuit

BUZ/P36

23

µ

PD78056F, 78058F

5.6

A/D Converter

An A/D converter of 8-bit resolution

×

8 channels is incorporated.

The following two types of A/D conversion operation start-up methods are available.

• Hardware start

• Software start

Figure 5-8. A/D Converter Block Diagram

Series Resistor String

Sample & Hold Circuit

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Selector

AV

SS

Voltage Comparator

Successive Approximation

Register (SAR)

Tap

Selector

INTP3/P03

Edge

Detection

Circuit

Control

Circuit

A/D Conversion

Result Register (ADCR)

Internal Bus

AV

DD

AV

REF0

AV

SS

INTAD

INTP3

24

µ

PD78056F, 78058F

5.7

D/A Converter

A D/A converter of 8-bit resolution

×

2 channels is available.

The conversion method is the R-2R resistor ladder method.

Figure 5-9. D/A Converter Block Diagram

AV

REF1

ANOn

Selector

AV

SS

D/A Conversion Value Set Register n

(DACSn)

Internal Bus

DACSn

Write

INTTM

X

DAMm

D/A Converter

Mode Register n = 0, 1 m = 4, 5 x = 1, 2

5.8

Serial Interfaces

3 channels of the clocked serial interface are incorporated.

• Serial interface channel 0

• Serial interface channel 1

• Serial interface channel 2

Table 5-3. Types and Functions of Serial Interface

Function

3-wire serial I/O mode

3-wire serial I/O mode with automatic transmission/reception function

SBI (serial bus interface) mode

2-wire serial I/O mode

Asynchronous serial interface

(UART) mode

Serial Interface Channel 0 Serial Interface Channel 1

(MSB/LSB first switchable) (MSB/LSB first switchable)

Serial Interface Channel 2

(MSB/LSB first switchable)

(MSB/LSB first switchable)

(MSB first)

(MSB first)

(Dedicated baud rate generator incorporated)

25

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

µ

PD78056F, 78058F

Figure 5-10. Serial Interface Channel 0 Block Diagram

Internal Bus

Selector

Selector

Serial I/O Shift

Register 0 (SIO0)

Output

Latch

Bus Release/Command

Acknowledge

Detection Circuit

Serial Clock Counter

Serial Clock

Control Circuit

Busy/Acknowledge

Output Circuit

Interrupt

Request

Signal

Generator

Selector

INTCSI0 f

XX

/2-f

XX

/2

8

TO2

SI1/P20

SO1/P21

STB/P23

BUSY/P24

SCK1/P22

Figure 5-11. Serial Interface Channel 1 Block Diagram

Internal Bus

Automatic Data Transmit/

Receive Address Pointer

(ADTP)

Buffer RAM

Automatic Data

Transmit/Receive

Interval Specification

Register (ADTI)

Match

Handshake

Control

Circuit

Serial I/O Shift Register 1 (SIO1)

5-Bit Counter

Serial Counter

Serial Clock Control Circuit

Interrupt Request

Signal Generator

Selector

INTCSI1 f

XX

/2-f

XX

/2

8

TO2

26

µ

PD78056F, 78058F

Figure 5-12. Serial Interface Channel 2 Block Diagram

Internal Bus

Receive Buffer Register

(RXB/SIO2)

Direction Control Circuit

Direction Control Circuit

Transmit Shift Register

(TXS/SIO2)

RxD/SI2/P70

TxD/SO2/P71

Receive Shift Register

(RXS)

Transmit Control Circuit

INTST

ASCK/SCK2/P72

Receive Control Circuit

INTSER

INTSR/INTCSI2

SCK Output

Control Circuit

Baud Rate

Generator f

XX

-f

XX

/2

10

5.9

Real-Time Output Port Functions

Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output to off-chip. This is a real-time output function. Pins to output to off-chip are called real-time output ports.

By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of stepping motors, etc.

Figure 5-13. Real-Time Output Port Block Diagram

Internal Bus

INTP2

INTTM1

INTTM2

Output Trigger

Control Circuit

Real-Time Output

Buffer Register

Higher 4 Bits

(RTBH)

Real-Time Output

Buffer Register

Higher 4 Bits

(RTBL)

Output Latch

P127

P120

Real-Time Output Port Mode

Register (RTPM)

27

µ

PD78056F, 78058F

6.

INTERRUPT FUNCTIONS AND TEST FUNCTIONS

6.1

Interrupt Functions

There are 22 interrupt functions of 3 different kinds, as shown below.

• Non-maskable : 1

• Maskable : 20

• Software : 1

Table 6-1. Interrupt Source List (1/2)

Interrupt Type

Non-maskable

Maskable

8

9

5

6

7

3

4

1

2

10

Note 1

Default

Priority

–––

Interrupt Source

Name

INTWDT

Trigger

Watchdog timer overflow

(watchdog timer mode 1 selected)

0

11

12

Internal/

External

Internal

INTWDT

Watchdog timer overflow

(interval timer mode selected)

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

INTCSI0

INTCSI1

INTSER

INTSR

Pin input edge detection External

End of serial interface channel 0 transfer

End of serial interface channel 1 transfer

Internal

Generation of serial interface channel

2 UART receive error

End of serial interface channel 2 UART reception

INTCSI2

INTST

End of serial interface channel 2 3-wire transfer

End of serial interface channel 2 UART transmission

Vector Table

Address

Basic

Configuration

Type

Note 2

0004H (A)

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

001CH

(B)

(C)

(D)

(B)

Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.

28

µ

PD78056F, 78058F

Interrupt Type

Maskable

Software

Table 6-1. Interrupt Source List (2/2)

Note 1

Default

Priority

13

14

15

16

Interrupt Source

Name Trigger

INTTM3 Reference time interval signal from watch timer

INTTM00

Generation of match signal of 16-bit timer register and capture/compare register (CR00)

INTTM01

Generation of match signal of 16-bit timer register and capture/compare register (CR01)

INTTM1 Generation of match signal of 8-bit timer/event counter 1

Internal/

External

Internal

Vector Table

Address

Basic

Configuration

Type

Note 2

001EH (B)

0020H

0022H

0024H

17

18

INTTM2 Generation of match signal of 8-bit timer/ event counter 2

End of conversion by A/D converter

INTAD

BRK

BRK instruction execution

0026H

0028H

003EH

(E)

Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.

29

Figure 6-1. Interrupt Function Basic Configuration (1/2)

(A) Internal non-maskable interrupt

Interrupt

Request

Priority Control

Circuit

Internal Bus

Vector Table

Address

Generator

Standby Release

Signal

µ

PD78056F, 78058F

(B) Internal maskable interrupt

Interrupt

Request

IF

MK

Internal Bus

IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(C) External maskable interrupt (INTP0)

Internal Bus

Interrupt

Request

Sampling Clock

Select Register

(SCS)

External Interrupt

Mode Register

(INTM0)

Sampling

Clock

Edge

Detection

Circuit

IF

MK IE

PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

30

µ

PD78056F, 78058F

Figure 6-1. Interrupt Function Basic Configuration (2/2)

(D) External maskable interrupt (except INTP0)

Interrupt

Request

External Interrupt

Mode Register

(INTM0, INTM1)

Edge Detection

Circuit

IF

Internal Bus

MK IE PR ISP

Priority Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(E) Software interrupt

Internal Bus

Interrupt

Request

IF : Interrupt request flag

IE : Interrupt enable flag

ISP : In-service priority flag

MK : Interrupt mask flag

PR : Priority specification flag

Priority Control

Circuit

Vector Table

Address

Generator

31

µ

PD78056F, 78058F

6.2

Test Functions

There are two test functions as shown in Table 6-2.

Table 6-2. Test Input Source List

Name

INTWT

INTPT4

Test Input Source

Trigger

Watch timer overflow

Port 4 falling edge detection

Figure 6-2. Test Function Basic Configuration

Internal Bus

MK

Test Input

IF

Standby Release

Signal

IF : Test input flag

MK : Test mask flag

Internal/External

Internal

External

32

µ

PD78056F, 78058F

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS

The external device expansion functions connect external devices to areas other than the internal ROM, RAM and

SFR. Ports 4 to 6 are used for external device connection.

8.

STANDBY FUNCTION

There are the following two standby functions to reduce the system power consumption.

• HALT mode : The CPU operating clock is stopped.

The average consumption current can be reduced by intermittent operation in combination with the normal operating mode.

• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock.

Figure 8-1. Stand-by Function

Main System

Clock Operation

Interrupt

Request

STOP

Instruction

Interrupt

Request

STOP Mode

(Main system clock oscillation stopped)

CSS = 1

CSS = 0

HALT

Instruction

HALT Mode

(Clock supply to CPU is stopped, oscillation)

Subsystem Clock

Operation

Note

HALT

Instruction

Interrupt

Request

HALT Mode

Note

(Clock supply to CPU is stopped, oscillation)

Note

The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set bit 7 (MCC) in the processor clock control register (PCC) to stop the main system clock. The STOP instruction cannot be used.

Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.

Remark

CSS : bit 4 in the PCC

9.

RESET FUNCTION

There are the following two reset methods.

External reset input by RESET pin

Internal reset by watchdog time runaway time detection

33

µ

PD78056F, 78058F

10. INSTRUCTION SET

(1) 8-bit instructions

MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,

ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Second

Operand

First

Operand

A

#byte

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

A r MOV

B, C sfr saddr

MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

!addr16

PSW MOV

MOV

MOV

MOV

MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP r

Note

sfr saddr !addr16

PSW [DE] [HL]

[HL + Byte]

[HL + B]

$addr16

[HL + C]

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

XCH

MOV MOV

XCH XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR OR

XOR

CMP

XOR

CMP

MOV MOV MOV MOV

XCH XCH

XOR

CMP

XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR OR

XOR

CMP

1

ROR

ROL

RORC

ROLC

None

INC

DEC

DBNZ

DBNZ INC

DEC

PUSH

POP

[DE]

[HL]

MOV

MOV ROR4

ROL4

[HL + Byte]

[HL + B]

[HL + C]

X

C

Note Except r = A

MOV

MULU

DIVUW

34

µ

PD78056F, 78058F

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second Operand

First Operand

AX rp

#word

ADDW

SUBW

CMPW

MOVW sfrp saddrp

!addr16

SP

MOVW

MOVW

MOVW

AX

MOVW

Note

MOVW

MOVW

MOVW

MOVW rp

Note

MOVW

XCHW

Note Only when rp = BC, DE or HL sfrp

MOVW saddrp

MOVW

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second Operand

First Operand

A.bit

A.bit

sfr.bit

saddr.bit

PSW.bit

!addr16

MOVW

[HL].bit

CY

MOV1 sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

MOV1

MOV1

MOV1

SP

MOVW

None

INCW, DECW

PUSH, POP

$addr16

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

None

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

(4) Call instruction/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second Operand

First Operand

Basic instruction

BR

AX

Compound instruction

!addr16

CALL

BR

!addr11

CALLF

[addr5]

CALLT

$addr16

BR, BC, BNC

BZ, BNZ

BT, BF

BTCLR

DBNZ

35

36

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

µ

PD78056F, 78058F

µ

PD78056F, 78058F

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

(T

A

= 25

°

C)

Parameter

Supply voltage

Input voltage

Output voltage

Low level output current

Operating ambient temperature

I

Symbol

V

DD

AV

DD

AV

REF0

AV

REF1

AV

SS

V

I1

V

V

T

I2

O

Analog input voltage V

AN

High level output current

I

OH

OL

A

Note

Test Conditions Rating Unit

P00 to P07, P10 to P17,P20 to P27, P30 toP37, P40 to P47,

–0.3 to + 7.0

–0.3 to V

DD

+ 0.3

–0.3 to V

DD

+ 0.3

–0.3 to V

DD

+ 0.3

–0.3 to + 0.3

–0.3 to V

DD

+ 0.3

P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130,

P131, X1, X2, XT2 RESET

P60 to P63 N-ch Open-drain

P10 to P17 Analog input pin

1 pin

P01 to P06, P30-P37, P56, P57, P60 to P67, P120 to P127 total

P10 to P17, P20 to P27, P40 to P47, P50 to P55,

P70 to P72, P130, P131 total

1 pin Peak value

Effective value

–0.3 to +16

–0.3 to V

DD

+ 0.3

AV

SS

–0.3 to AV

REF0

+ 0.3

–10

–15

–15

30

15

P50 to P55 total

P56, P57, P60 to P63 total

Peak value

Effective value

Peak value

Effective value

P10 to P17, P20 to P27, P40 to P47, Peak value

P70 to P72, P130, P131 total Effective value

P01 to P06, P30 to P37, P64 to P67, Peak value

P120 to P127 total Effective value

100

70

100

70

50

20

50

20

–40 to +85

V

V

V mA mA mA mA mA mA mA mA mA

°

C mA mA mA mA

V

V

V

V

V

V

Storage temperature

T stg

–65 to +150

°

C

Note The effective value should be calculated as follows: [Effective value] = [Peak value]

×

√ duty

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.

37

µ

PD78056F, 78058F

Main System Clock Oscillation Circuit Characteristics (T

A

= –40 to 85

°

C, V

DD

= 2.7 to 6.0 V)

Resonator

Ceramic resonator

Crystal resonator

External clock

Recommended

Circuit

IC XT2 XT1

R1

C4 C3

X2 X1 IC

C2 C1

X2

µ

PD74HCU04

X1

Parameter

Oscillator frequency (f

X

)

Note 1

Test Conditions

V

DD

= Oscillator voltage range

Oscillation stabilization time

Note 2

After V

DD

reaches oscillator voltage range MIN.

MIN.

1.0

Oscillator frequency (f

X

)

Note 1

Oscillation stabilization time

Note 2

V

DD

= 4.5 to 6.0 V

1.0

X1 input frequency (f

X

)

Note 1

X1 input high/low level width

(t

XH

, t

XL

)

1.0

85

TYP.

MAX.

Unit

5.0

4

5.0

10

30

5.0

500

MHz ms

MHz ms

MHz ns

Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS

.

• Do not ground wiring to a ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.

38

µ

PD78056F, 78058F

Subsystem Clock Oscillation Circuit Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Resonator Recommended Circuit

Crystal resonator

IC XT2 XT1

R1

C4 C3

Parameter

Oscillator frequency (f

XT

)

Note 1

Test Conditions

Oscillation stabilization time

Note 2

V

DD

= 4.5 to 6.0 V

External clock

XT2 XT1

XT1 input frequency (f

XT

)

Note 1

XT1 input high-/low-level width

(t

XTH

, t

XTL

)

MIN.

TYP.

MAX.

Unit kHz 32 32.768

35

1.2

32

2

10

100 s kHz

5

15

µ s

Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time.

2. Time required to stabilize oscillation after V

DD

reaches oscillator voltage MIN.

Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS

.

• Do not ground wiring to a ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock oscillator.

Particular care is therefore required with the wiring method when the subsystem clock is used.

39

µ

PD78056F, 78058F

Capacitance (T

A

= 25

°

C

,

V

DD

= V

SS

= 0 V)

Parameter Symbol

Input capacitance

C

IN

Test Conditions f = 1 MHz

Measured pins returned to 0 V.

I/O capacitance

C

IO f = 1 MHz P01 to P06, P10 to P17,

Measured pins returned P20 to P27, P30 to P37, to 0 V.

P40 to P47, P50 to P57,

P64 to P67, P70 to P72,

P120 to P127, P130, P131

P60 to P63

MIN.

TYP.

MAX.

15

Unit pF

15 pF

20 pF

Remark

The characteristics of the alternate-function pins are the same as those of the port pins unless otherwise specified.

40

µ

PD78056F, 78058F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Input voltage, high

Input voltage, low

Output voltage, high

Output voltage, low

Input leakage current, high

Symbol

V

IH1

V

IH2

V

IH3

V

IH4

V

IH5

V

IL1

V

IL2

V

IL3

V

IL4

V

IL5

V

OH

V

OL1

V

OL2

V

OL3

I

LIH1

I

LIH2

I

LIH3

Test Conditions MIN.

P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, 0.7 V

DD

P50 to P57, P64 to P67, P71, P120 to P127, P130, P131

P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72,

0.8 V

DD

RESET

P60 to P63 (N-ch Open-drain)

X1, X2

XT1/P07, XT2 V

DD

= 4.5 to 6.0 V

0.7 V

V

DD

DD

–0.5

0.8 V

DD

0.9 V

DD

0 P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47,

P50 to P57, P64 to P67, P71, P120 to P127, P130, P131

P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72,

RESET

P60 to P63 V

DD

= 4.5 to 6.0 V

0

X1, X2

XT1/P07, XT2 V

DD

= 4.5 to 6.0 V

0

0

0

0

0

V

DD

–1.0

V

DD

–0.5

V

DD

= 4.5 to 6.0 V, I

OH

= –1mA

I

OH

= –100

µ

A

P50 to P57, P60 to P63 V

DD

= 4.5 to 6.0 V,

I

OL

= 15 mA

P01 to P06, P10 to P17, P20 to P27, V

DD

= 4.5 to 6.0 V,

P30 to P37, P40 to P47, P64 to P67, I

OL

= 1.6 mA

P70 to P72, P120 to P127,

P130, P131

SB0, SB1, SCK0 V

DD

= 4.5 to 6.0 V,

N-ch open-drain at pull-up time(R = 1 k

)

I

OL

= 400

µ

A

V

IN

= V

DD

V

IN

= 15 V

P00 to P06, P10 to P17, P20 to

P27, P30 to P37, P40 to P47,

P50 to P57, P60 to P67, P70 to

P72, P120 to P127, P130,

P131 RESET

X1, X2, XT1/P07, XT2

P60 to P63

TYP.

MAX.

Unit

V

DD

V

0.4

V

V

DD

15

DD

V

DD

V

DD

0.3 V

0.2 V

0.3 V

0.2 V

0.4

0.1 V

2.0

0.4

0.2 V

0.5

3

20

80

DD

DD

DD

DD

0.2 V

DD

DD

DD

µ

µ

µ

V

V

V

V

V

V

V

V

V

V

A

A

A

V

V

V

V

V

V

V

V

Remark

The characteristics of alternate-function pins and a port pin are the same unless specified otherwise.

41

µ

PD78056F, 78058F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Input leakage current, low

Symbol

I

LIL1

I

LIL2

I

LIL3

I

LOH

V

IN

= 0 V

V

OUT

= V

DD

Test Conditions

P00 to P06, P10 to P17, P20 to P27,

P30 to P37, P40 to P47, P50 to P57,

P64 to P67, P70 to P72, P120 to

P127, P130, P131, RESET

X1, X2, XT1/P07, XT2

P60 to P63

Output leakage current, high

Output leakage current, low

Mask option pull-up resistor

Software pullup resistor

I

LOL

R

1

R

2

V

OUT

= 0 V

V

IN

= 0 V, P60 to P63

V

IN

= 0 V, P01 to P06, P10 to V

DD

= 4.5 V to 6.0 V

P17, P20 to P27, P30 to P37,

P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to

P127, P130, P131

MIN.

20

15

20

TYP.

40

40

MAX.

–3

–3

90

90

500

Unit

µ

A

–20

–3

Note

3

µ

A

µ

A

µ

A

µ

A k

Ω k

Ω k

Note

When the pull-up resistor is not included in P60 to P63 (specified by a mask option), a –200

µ

A (MAX.) lowlevel input leakage current flows only at the 1.5 clock interval (no wait) when the read instruction to port 6

(PM6) and port mode register (PM6) is executed. At times other than this 1.5 interval, a –3

µ

A (MAX.) current flows.

Remark

The characteristics of alternate-function pins and port pins are the same unless specified otherwise.

42

µ

PD78056F, 78058F

DC Characteristics (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Power supply current

Note 1

Symbol

I

DD1

I

I

I

I

I

DD2

DD3

DD4

DD5

DD6

Test Conditions

5.0-MHz crystal oscillation operating mode

(f

XX

= 2.5 MHz)

Note 2

V

V

DD

DD

= 5.0 V

= 3.0 V

±

±

10%

10%

Note 5

Note 6

5.0-MHz crystal oscillation operating mode

(f

XX

= 5.0 MHz)

Note 3

5.0-MHz crystal oscillation

HALT mode

(f

XX

= 2.5 MHz)

Note 2

5.0-MHz crystal oscillation

HALT mode

(f

XX

= 5.0 MHz)

Note 3

V

DD

= 5.0 V

±

10%

Note 5

V

DD

= 3.0 V

±

10%

Note 6

V

V

DD

DD

= 5.0 V

= 3.0 V

±

±

10%

10%

32.768-kHz crystal oscillation operating mode

Note 4

32.768-kHz crystal oscillation

HALT mode

XT1 = V

When feedback resistor is used

XT1 = V

DD

DD

Note 4

STOP mode

STOP mode

When feedback resistor is not used

V

DD

= 5.0 V

±

10%

V

DD

= 3.0 V

±

10%

V

DD

= 5.0 V

±

10%

V

DD

= 3.0 V

±

10%

V

DD

= 5.0 V

±

10%

V

DD

= 3.0 V

±

10%

V

DD

= 5.0 V

±

10%

V

DD

= 3.0 V

±

10%

V

DD

= 5.0 V

±

10%

V

DD

= 3.0 V

±

10%

1.4

0.5

1.6

0.65

60

32

25

5

1

0.5

0.1

0.05

MIN.

TYP.

MAX.

Unit

4 12 mA

0.6

1.8

mA

6.5

0.8

19.5

2.4

mA mA mA mA mA mA

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

4.2

1.5

4.8

1.95

120

64

55

15

30

10

30

10

Notes 1. Flows through the V

DD

and AV

DD

pins. Does not include the current which flows through the A/D converter,

D/A converter, and on-chip pull-up resistor.

2. f xx

= f x

/2 operation (when oscillation mode selection register (OSMS) is set to 00H)

3. f

XX

= f

X

operation (when the OSMS is set to 01H)

4. When the main system clock is stopped

5. High-speed mode operation (when a processor clock control register (PCC) is set to 00H)

6. Low-speed mode operation (when the PCC is set to 04H)

Remarks 1.

f

XX

: Main system clock frequency (f

X

or f

X

/2)

2.

f

X

: Main system clock oscillator frequency

43

µ

PD78056F, 78058F

AC CHARACTERISTICS

(1) Basic Operation

(T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

Parameter

Cycle time

(Min. instruction execution time)

TI01 input high-/ low-level width t

T

Symbol

CY

TIH01

, t

TIL01

Operating on main system clock

Test Conditions f

XX

= f

X

/2

Note 1

f

XX

= f

X

Note 2

V

DD

= 4.5 to 6.0 V

TI00 input high-/ t

TIH00

, t

TIL00

V

DD

= 4.5 to 6.0 V low-level width

Operating on subsystem clock

MIN.

0.8

0.4

0.8

40

2/f sam

+0.1

Note 3

2/f sam

+0.2

Note 3

10

TI1, TI2 input frequency

TI1, TI2 input high-/low-level width t f

TI1

TIH1

, t

TIL1

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

0

0

100

1.8

Interrupt request input high-/low

-level width

RESET low-level width t t

INTH

RSL

, t

INTL

INTP0

INTP1 to INTP6, KR0 to KR7

V

DD

= 4.5 to 6.0 V 2/f sam

+0.1

Note 3

2/f sam

+0.2

Note 3

10

10

TYP.

122

MAX.

64

32

32

125

4

275

Unit

µ s

µ s

µ s

µ s

µ s

µ s

µ s

Notes 1. When oscillation mode selection register is set to 00H

2. When oscillation mode selection register is set to 01H

3. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of f sam is possible between f

XX

/2

N

, f

XX

/32, f

XX

/64 and f

XX

/128 (when N= 0 to 4).

Remarks 1.

f

XX

: Main system clock frequency (f

X

or f

X

/2)

2.

f

X

: Main system clock oscillation frequency

MHz kHz ns

µ s

µ s

µ s

µ s

µ s

44

T

CY

vs V

DD

(at f

XX

= f

X

/2

main system clock operation)

60

µ

PD78056F, 78058F

T

CY

vs V

DD

(at f

XX

= f

X main system clock operation)

60

10

Operation Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5

Supply Voltage V

DD

[V]

6

10

Operation Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5

Supply Voltage V

DD

[V]

6

45

µ

PD78056F, 78058F

(2) Read/Write Operation

(a) When MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to + 85

°

C, V

DD

= 4.5 to 6.0 V)

WAIT

Parameter

ASTB high-level width

Address setup time

Address hold time

Data input time from address

Data input time from RD

Read data hold time

RD low-level width

input time from RD

WAIT

input time from WR

WAIT low-level width

Write data setup time

Write data hold time

WR low-level width

RD

delay time from ASTB

WR

delay time from ASTB

ASTB

delay time from

RD

in external fetch

Address hold time from

RD

in external fetch

Write data output time from RD

Write data output time from WR

Address hold time from WR

RD

delay time from WAIT

WR

delay time from WAIT

↑ t

WDS t

WDH t

WRL t

ASTRD t

ASTWR t

RDAST t

RDH t

RDL1 t

RDL2 t

RDWT1 t

RDWT2 t

WRWT t

WTL

Symbol Test Conditions t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDD1 t

RDD2 t t t t

RDADH

RDWD

RDWD t

WRADH t

WTRD

WTWR

MIN.

0.85t

CY

– 50

0.85t

CY

– 50

50

0

(2+2n)t

CY

–60

(2.85+2n)t

CY

–60

(1.15+2n)t

CY

(2.85+2n)t

CY

–100

20

(2.85+2n)t

CY

–60

25

0.85t

CY

+ 20

0.85t

CY

– 10

0.85t

CY

– 50

40

0

0.85t

CY

1.15t

CY

+ 40

1.15t

CY

+ 30

MAX.

(2.85+2n)t

CY

–80

(4+2n)t

CY

–100

(2+2n)t

CY

–100

(2.85+2n)t

CY

–100

0.85t

CY

–50

2t

CY

–60

2t

CY

–60

(2+2n)t

CY

1.15t

CY

+ 20

1.15t

CY

+ 50

50

1.15t

CY

+ 40

3.15t

CY

+ 40

3.15t

CY

+ 30

Remarks 1.

MCS: Oscillation mode selection register (OSMS) bit 0

2.

PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0

3.

t

CY

= T

CY

/4

4.

n indicates the number of waits.

ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

46

µ

PD78056F, 78058F

(b) Except when MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to + 85

°

C, V

DD

= 2.7 to 6.0 V)

MAX.

Parameter

ASTB high-level width

Address setup time

Address hold time

Data input time from address

Data input time from RD

Read data hold time

RD low-level width

WAIT

input time from RD

WAIT

input time from WR

WAIT low-level width

Write data setup time

Write data hold time

WR low-level width

RD

delay time from ASTB

WR

delay time from ASTB

ASTB

delay time from

RD

in external fetch

Address hold time from

RD

in external fetch

Write data output time from RD

Write data output time from WR

Address hold time from WR

RD

delay time from WAIT

WR

delay time from WAIT

↑ t

WRWT t

WTL t

WDS t

WDH t

WRL t

ASTRD t

ASTWR t

RDAST t

RDD1 t

RDD2 t

RDH t

RDL1 t

RDL2 t

RDWT1 t

RDWT2

Symbol Test Conditions t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDADH t

RDWD t

WRWD t

WRADH t

WTRD t

WTWR

MIN.

t

CY

– 80 t

CY

– 80

0.4t

CY

– 10

0

(1.4+2n)t

CY

–20

(2.4+2n)t

CY

–20

(1+2n)t

CY

(2.4+2n)t

CY

–60

20

(2.4+2n)t

CY

–20

0.4t

CY

–30

1.4t

CY

–30

t

CY

–10 t

CY

– 50

0.4t

CY

– 20

0 t

CY

0.6t

CY

+ 180

0.6t

CY

+ 120

(3+2n)t

CY

–160

(4+2n)t

CY

–200

(1.4+2n)t

CY

–70

(2.4+2n)t

CY

–70 t

CY

–100

2t

CY

–100

2t

CY

–100

(2+2n)t

CY t

CY

+ 20 t

CY

+ 50

60 t

CY

+ 60

2.6t

CY

+ 180

2.6t

CY

+ 120

Remarks 1.

MCS: Oscillation mode selection register (OSMS) bit 0

2.

PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0

3.

t

CY

= T

CY

/4

4.

n indicates the number of waits.

ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

47

µ

PD78056F, 78058F

(3) Serial Interface (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V)

(a) Serial interface channel 0

(i) 3-wire serial I/O mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time t

Symbol

KCY1

V

DD

Test Conditions

= 4.5 to 6.0 V

SCK0 high-/low-level width

SI0 setup time

(to SCK0

)

SI0 hold time

(from SCK0

)

SO0 output delay time from SCK0

↓ t

KH1

, t

KL1 t

SIK1 t

KSI1

V

V

DD

DD

= 4.5 to 6.0 V

= 4.5 to 6.0 V t

KSO1

C = 100 pF

Note

MIN.

800

1600 t

KCY1

/2–50 t

KCY1

/2–100

100

150

400

Note

C is the load capacitance of the SCK0 and SO0 output lines.

TYP.

MAX.

300

Unit ns ns ns ns ns ns ns ns

(ii) 3-wire serial I/O mode (SCK0... External clock input)

Parameter

SCK0 cycle time

SCK0 high-/low-level width

SI0 setup time

(to SCK0

)

SI0 hold time

(from SCK0

)

SO0 output delay time from SCK0

SCK0 rise, fall time

Symbol t

KCY2 t

KH2

, t

KL2 t

SIK2 t

KSI2

Test Conditions

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V t

KSO2 C = 100 pF

Note

MIN.

800

1600

400

800

100

400 t

R2

, t

F2

When using external device expansion function

When not using external device expansion function

Note

C is the load capacitance of the SO0 output line.

TYP.

MAX.

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

48

µ

PD78056F, 78058F

(iii) SBI mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

Symbol t

KCY3

SCK0 high-/low-level width t

KH3, t

KL3 t

SIK3

SB0, SB1 setup time

(to SCK0

)

SB0, SB1 hold time

(from SCK0

↑)

SB0, SB1 output delay time from SCK0

↓ t t

KSI3

KSO3

SB0, SB1

from SCK0

SCK0

from SB0, SB1

SB0, SB1 high-level width

SB0, SB1 low-level width t

SBL t

KSB t

SBK t

SBH

Test Conditions

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V 0

0 t

KCY3 t

KCY3 t

KCY3 t

KCY3

MIN.

800

3200 t

KCY3

/2–50 t

KCY3

/2–150

100

300 t

KCY3

/2

TYP.

MAX.

250

1000

Note

R and C are the load resistacne and load capacitance of the SCK0, SB0, and SB1 output lines.

ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns

49

µ

PD78056F, 78058F

(iv) SBI mode (SCK0... External clock input)

Parameter

SCK0 cycle time

Symbol t

KCY4

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK0 high-/low-level width t

KH4 t

KL4 t

SIK4

SB0, SB1 setup time

(to SCK0

)

SB0, SB1 hold time

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t t

KSI4

KSO4

SB0, SB1

from SCK0

SCK0

from SB0, SB1

SB0, SB1 high-level width

SB0, SB1 low-level width

SCK0 rise, fall time t t

KSB t

SBK t

SBH

SBL

t

R4

, t

F4

V

V

DD

DD

= 4.5 to 6.0 V

= 4.5 to 6.0 V

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

When using external device expansion fanction

When not using external device expansion function

0

0 t

KCY4 t

KCY4 t

KCY4 t

KCY4

MIN.

800

3200

400

1600

100

300 t

KCY4

/2

TYP.

Note

R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.

MAX.

300

1000

160

1000 ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns

50

µ

PD78056F, 78058F

(v) 2-wire serial I/O mode (SCK0... Internal clock output)

Parameter

SCK0 cycle time

SCK0 high-level width

SCK0 low-level width

Symbol t

KCY5 t

KH5 t

KL5

SB0, SB1 setup time

(to SCK0

) t

SIK5

SB0, SB1 hold time

(from SCK0

)

SB0, SB1 output delay time from SCK0

↓ t

KSI5 t

KSO5

Test Conditions

R = 1 k

,

C = 100 pF

Note

MIN.

1600 t

KCY5

/2–160

V

DD

= 4.5 to 6.0 V t

KCY5

/2–50

t

KCY5

/2–100

V

DD

= 4.5 to 6.0 V 300

350

600

0

TYP.

MAX.

300

Note

R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.

(vi) 2-wire serial I/O mode (SCK0... External clock input)

Parameter

SCK0 cycle time

SCK0 high-level width

SCK0 low-level width

SB0, SB1 setup time

(to SCK0

)

SB0, SB1 hold time

(from SCK0

)

SB0, SB1 output delay time from SCK0

SCK0 rise, fall time

Symbol t

KCY6 t

KH6 t

KL6 t

SIK6 t t t

KSI6

KSO6

R6 t

F6

,

Test Conditions

R = 1 k

,

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

When using external device expansion function

When not using external device expansion function

MIN.

1600

650

800

100 t

KCY6

/2

0

0

TYP.

Note

R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.

MAX.

300

500

160

1000 ns ns ns ns

Unit ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns

51

µ

PD78056F, 78058F

(b) Serial interface channel 1

(i) 3-wire serial I/O mode (SCK1...Internal clock output)

Parameter

SCK1 cycle time

Symbol t

KCY7

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK1 high-/low-level width

SI1 setup time (to SCK1

)

SI1 hold time (from SCK1

)

SO1 output delay time from SCK1

↓ t

KH7, t

KL7 t

SIK7

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V t

KSI7 t

KSO7

C = 100 pF

Note

Note

C is the load capacitance of the SCK1 and SO1 output lines.

MIN.

800

1600

t

KCY7

/2–50 t

KCY7

/2–100

100

150

400

TYP.

MAX.

300

Unit ns ns ns ns ns ns ns ns

(ii) 3-wire serial I/O mode (SCK1...External clock input)

Parameter

SCK1 cycle time

Symbol t

KCY8

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK1 high-/low-level width

SI1 setup time (to SCK1

)

SI1 hold time (from SCK1

)

SO1 output delay time from SCK1

SCK1 rise, fall time t

KH8, t

KL8 t

SIK8 t

KSI8 t

KSO8 t

R8

, t

F8

V

DD

= 4.5 to 6.0 V

C = 100 pF

Note

When using external device expansion function

When not using external device expansion function

Note

C is the load capacitance of the SO1 output line.

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

52

µ

PD78056F, 78058F

(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)

Parameter

SCK1 cycle time

SCK1 high-/low-level width

SI1 setup time (to SCK1

)

Symbol t

KCY9

Test Conditions

V

DD

= 4.5 to 6.0 V t

KH9 t

KL9 t

SIK9

SI1 hold time (from SCK1

)

SO1 output delay time from SCK1

STB

from SCK1

Strobe signal high-level width

Busy signal setup time (to busy signal detection timing)

Busy signal hold time (to busy signal detection timing)

SCK1

↓ from busy inactive t

KSI9 t

KSO9 t

SBD t

SBW t

BYS t

BYH t

SPS

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V

C = 100 pF

Note

V

DD

= 4.5 to 6.0 V

MIN.

800

1600

t

KCY9

/2–50 t

KCY9

/2–100

100

150

400

TYP.

t

KCY9

/2–100 t

KCY9

–30

100

100

150

MAX.

300 t

KCY9

/2+100 t

KCY9

+30

2t

KCY9

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note

C is the load capacitance of the SCK1 and SO1 output lines.

(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)

Parameter

SCK1 cycle time

Symbol t

KC Y10

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK1 high-/low-level width

SI1 setup time (to SCK1

)

SI1 hold time (from SCK1

)

SO1 output delay time from SCK1

SCK1 rise, fall time t

KH10, t

KL10 t

SIK10 t

KSI10 t

KSO10 t

R10

, t

F10

V

DD

= 4.5 to 6.0 V

C = 100 pF

Note

When using external device expansion function

When not using external device expansion function

Note

C is the load capacitance of the SO1 output line.

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160

1000

Unit ns ns ns ns ns ns ns ns ns

53

µ

PD78056F, 78058F

(c) Serial interface channel 2

(i) 3-wire serial I/O mode (SCK2...Internal clock output)

Parameter

SCK2 cycle time

Symbol t

KCY11

Test Conditions

V

DD

= 4.5 to 6.0 V

SCK2 high-/low-level width

SI2 setup time (to SCK2

)

SI2 hold time (to SCK2

)

SO2 output delay time from SCK2

↓ t

KH11, t

KL11 t

SIK11

V

DD

= 4.5 to 6.0 V

V

DD

=

4.5 to 6.0 V t

KSI11 t

KSO11

C = 100 pF

Note

Note

C is the load capacitance of the SCK2 and SO2 output lines.

(ii) UART mode (Dedicated baud rate generator output)

Parameter

Transfer rate

Symbol Test Conditions

V

DD

= 4.5 to 6.0 V

MIN.

800

1600

t

KCY11

/2–50

t

KCY11

/2–100

100

150

400

TYP.

MAX.

300

MIN.

TYP.

MAX.

78125

39063

Unit bps bps

Unit ns ns ns ns ns ns ns ns

(iii) UART mode (External clock input)

Parameter

ASCK cycle time

ASCK high-/low-level width

Transfer rate

ASCK rise, fall time

Symbol t

KCY12

Test Conditions

V

DD

= 4.5 to 6.0 V t

KH12

, t

KL12

V

DD

= 4.5 to 6.0 V

V

DD

= 4.5 to 6.0 V t

R12

, t

F12

V

DD

= 4.5 to 6.0 V, when not using external device expansion function

MIN.

800

1600

400

800

TYP.

MAX.

39063

19531

1000

160

Unit ns ns ns ns bps bps ns ns

54

AC Timing Test Point (Excluding X1, XT1 Input)

0.8 V

DD

0.2 V

DD

Test Points

0.8 V

DD

0.2 V

DD

µ

PD78056F, 78058F

Clock Timing

t

XL

1/f

X t

XH

X1 Input

V

DD

-0.5 V

0.4 V t

XTL

1/f

XT t

XTH

XT1 Input

V

IH5

(MIN.)

V

IL5

(MAX.)

TI Timing

t

TIL00

, t

TIL01 t

TIH00

, t

TIH01

TI00, TI01 t

TIL1

1/f

TI t

TIH1

TI1, TI2

55

Read/Write Operation

External Fetch (No Wait) :

A8 to A15

AD0 to AD7

Higher 8-Bit Address

Lower 8-Bit

Address t

ADS t

ASTH t

ADH t

ADD1

Hi-z

Instruction

Code t

RDD1 t

RDADH t

RDAST

ASTB

RD t

ASTRD t

RDL1 t

RDH

External Fetch (Wait Insertion) :

A8 to A15

AD0 to AD7

Lower 8-Bit

Address t

ADS t

ASTH t

ADH

ASTB

Higher 8-Bit Address t

ADD1

Hi-z t

RDD1

Instruction

Code t

RDADH t

RDAST

µ

PD78056F, 78058F

RD

WAIT t

RDWT1 t

ASTRD t

RDL1 t

WTL t

WTRD t

RDH

56

µ

PD78056F, 78058F

External Data Access (No Wait) :

A8 to A15

AD0 to AD7

Lower

8-Bit

Address t

ADS t

ASTH

ASTB t

ADH t

ADD2

Hi-z t

RDD2

Higher 8-Bit Address

Read Data t

RDH

Hi-z

RD

WR t

ASTRD t

RDL2 t

ASTWR

Write Data

Hi-z t

RDWD t

WRWD t

WDS t

WRL t

WDH t

WRADH

External Data Access (Wait Insertion) :

A8 to A15

AD0 to AD7

Lower

8-Bit

Address t

ADS t

ASTH

ASTB t

ADH t

ADD2

Hi-z t

RDD2 t

ASTRD

RD t

RDL2

Higher 8-Bit Address

Read Data t

RDH

Hi-z

WR t

ASTWR

Write Data

Hi-z t

RDWD t

WRWD t

WDS t

WRL t

WDH t

WRADH

WAIT t

RDWT2 t

WTL t

WTRD t

WRWT t

WTL t

WTWR

57

µ

PD78056F, 78058F

Serial Transfer Timing

3-wire Serial I/O Mode : t

KLm t

Rn t

KCYm t

KHm t

Fn

SCK0 to SCK2

SI0 to SI2 t

KSOm

SO0 to SO2 m = 1, 2, 7, 8, 11 n = 2, 8

SBI Mode (Bus Release Signal Transfer) :

t

SIKm t

KSIm

Input Data

Output Data t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4

SCK0 t

KSB t

SBL t

SBH t

SBK t

SIK3,4 t

KSI3, 4

SB0, SB1 t

KSO3,4

SBI Mode (Command Signal Transfer) :

SCK0 t

KSB t

SBK t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4 t

SIK3,4 t

KSI3,4

SB0, SB1

58

t

KSO3,4

µ

PD78056F, 78058F

2-wire Serial I/O Mode :

SCK0

SB0, SB1 t

KSO5,6 t

KL5,6 t

R6 t

KCY5,6 t

KH5,6 t

F6 t

SIK5,6 t

KSI5,6

3-wire Serial I/O Mode with Automatic Transmit/Receive Function :

SO1

D2 D1 D0

SI1

D2 t

SIK9,10 t

KSO9,10

SCK1

STB

D1 D0 t

KH9,10 t

KSI9,10 t

F10 t

KL9,10 t

KCY9,10 t

R10 t

SBD t

SBW

3-wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing)

:

SCK1 7 8 9

Note

10

Note

t

BYS t

BYH

10+n

Note

t

SPS

1

BUSY

(Active high)

Note

The signal is not actually driven low here; it is shown as such to indicate the timing.

UART Mode (External Clock Input) :

t

KL12 t

R12 t

KCY12 t

KH12 t

F12

ASCK

D7

D7

59

µ

PD78056F, 78058F

A/D CONVERTER CHARACTERISTICS (T

A

= –40 to +85

°

C, AV

DD

= V

DD

= 2.7 to 6.0 V, AV

SS

= V

SS

= 0 V)

Parameter

Resolution

Overall error

Note

Conversion time

Sampling time

Analog input voltage

Reference voltage

Resistance between AV

REF0

and AV

SS

Symbol t

CONV t

SAMP

V

IAN

AV

REF0

R

AIREF0

Test Conditions

2.7 V

AV

REF0

AV

DD

MIN.

8

19.1

12/f xx

AV

SS

2.7

4

TYP.

8

14

MAX.

8

0.6

200

AV

REF0

AV

DD

Unit bit

V

V k

%

µ s

µ s

Note

Overroll error excluding quantization error (

±

1/2 LSB). It is indicated as a ratio to the full-scale value.

Caution For pins which also function as port pins (see 3.1 Port Pins), do not perform the following operations during A/D conversion. If these operations are performed, the total error ratings cannot be kept (except for LCD segment output alternate-function pin).

(1) Rewrite the output latch while the pin is used as a port pin.

(2) Change the output level of the pin used as an output pin, even if it is not used as a port pin.

Remarks 1.

f

XX

: Main system clock frequency (f

X

or f

X

/2)

2.

f x

: Main system clock oscillation frequency

D/A CONVERTER CHARACTERISTICS (T

A

= –40 to +85

°

C, V

DD

= 2.7 to 6.0 V, AV

SS

= V

SS

= 0 V)

Resolution

Overall error

Parameter Symbol Test Conditions

Settling time

Output resistance

Analog reference voltage

Resistance between AV

REF1 and AV

SS

R

O

AV

REF1

R

AIREF1

R = 2M

Note 1

R = 4M

Note 1

R = 10M

Note 1

Note 1

4.5 V

AV

REF1

6.0 V

C=30pF

2.7 V

AV

REF1

< 4.5 V

Note 2

DACS0, DACS1 = 55H

Note 2

MIN.

2.0

4

TYP.

10

8

Notes

1. R and C are the load resistance and load capacitance of the D/A converter output pins.

2. Value for D/A converter 1 channel

MAX.

8

1.2

0.8

0.6

10

15

V

DD

Remark

DACS0, DACS1: D/A conversion value setting register 0, 1

Unit bit

%

%

%

µ s

µ s k

V k

60

µ

PD78056F, 78058F

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T

A

= –40 to + 85

°

C)

Parameter

Data retention power supply voltage

Symbol

V

DDDR

Data retention power supply current

I

DDDR

Release signal set time t

SREL

Oscillation stabilization wait time t

WAIT

Test Conditions

V

DDDR

= 1.8 V

Subsystem clock stop and feed-back resistor disconnected

Release by RESET

Release by interrupt request

MIN.

1.8

0

TYP.

MAX.

6.0

0.1

2

17

/fx

Note

10

Unit

V

µ

A

µ s ms ms

Note

In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register, selection of

2 12 /f

XX

and 2 14 /f

XX

to 2 17 /f

XX

is possible.

Remark

f

XX

: Main system clock frequency (f

X

or f

X

/2) f

X

: Main system clock oscillation frequency

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode

Operating Mode

Data Retention Mode

V

DD

V

DDDR t

SREL

STOP Instruction Execution

RESET t

WAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)

HALT Mode

STOP Mode

Operating Mode

Data Retention Mode

V

DD

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)

V

DDDR t

SREL t

WAIT

61

Interrupt Request Input Timing

INTP0 to INTP6

RESET Input Timing

RESET t

INTL t

INTH t

RSL

µ

PD78056F, 78058F

62

µ

PD78056F, 78058F

12. PACKAGE DRAWINGS

µ

PD78056FGC-

×××

-3B9, 78058FGC-

×××

-3B9

80 PIN PLASTIC QFP (14

×

14)

A

B

60

61

41

40 detail of lead end

C D

S

Q

R

80

1

21

20

F

G

J

H I

M

P

K

M

N

L

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

M

N

P

Q

R

S

C

D

F

G

H

I

J

K

L

ITEM MILLIMETERS

A 17.2±0.4

B 14.0±0.2

INCHES

0.677±0.016

14.0±0.2

17.2±0.4

0.825

0.825

0.30±0.10

0.13

0.65 (T.P.)

1.6±0.2

0.8±0.2

0.15

+0.10

–0.05

0.10

2.7

0.1±0.1

5

°

±5

°

3.0 MAX.

0.677±0.016

0.032

0.032

0.005

0.026 (T.P.)

0.063±0.008

0.006

0.004

0.106

+0.004

–0.003

0.004±0.004

5

°

±5

°

0.119 MAX.

S80GC-65-3B9-4

Remark Dimensions and materials of ES product are the same as those of mass-production products.

63

µ

PD78056F, 78058F

µ

PD78056FGC-

×××

-8BT, 78058FGC-

×××

-8BT

80 PIN PLASTIC QFP (14

×

14)

A

B

60

61

41

40

C D

S detail of lead end

R

Q

80

1

21

20

F

P

G

H I

M

J

N

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

L

K

M

M

N

P

Q

R

S

D

F

G

H

J

I

K

L

ITEM MILLIMETERS

A 17.20±0.20

B 14.00±0.20

INCHES

0.677±0.008

+0.009

–0.008

C 14.00±0.20

17.20±0.20

0.825

0.825

0.32±0.06

0.677±0.008

0.032

0.032

0.13

0.65 (T.P.)

1.60±0.20

0.80±0.20

0.005

0.026 (T.P.)

0.063±0.008

0.17

+0.03

–0.07

0.10

1.40±0.10

0.004

0.055±0.004

0.125±0.075

0.005±0.003

3

° +7

–3

°

°

3

° +7

–3

°

°

1.70 MAX.

0.067 MAX.

P80GC-65-8BT

64

µ

PD78056F, 78058F

80 PIN PLASTIC TQFP (FINE PITCH) (12

×

12)

A

B

61

60 41

40 detail of lead end

80

1

G

20

21

H I

M

J

K

N

L

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A 14.0±0.2

B

C

D

F

G

H

I

J

K

L

M

N

P

Q

R

S

12.0±0.2

12.0±0.2

14.0±0.2

1.25

1.25

0.22

+0.05

–0.04

0.10

0.5 (T.P.)

1.0±0.2

0.5±0.2

0.145

+0.055

–0.045

0.10

1.05

0.05±0.05

5°±5°

1.27 MAX.

INCHES

0.049

0.049

0.009±0.002

0.004

0.020 (T.P.)

0.006±0.002

0.004

0.041

0.002±0.002

5°±5°

0.050 MAX.

P80GK-50-BE9-4

Remark Dimensions and materials of ES product are the same as those of mass-production products.

65

µ

PD78056F, 78058F

13. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below.

For detail of recommended soldering conditions, refer to the information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 13-1. Surface Mounting Type Soldering Conditions (1/2)

(1)

µ

PD78056FGC-

×××

-3B9 : 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

µ

PD78058FGC-

×××

-3B9 : 80-pin plastic QFP (14

×

14 mm, resin thickness 2.7 mm)

Soldering

Method

Infrared reflow

VPS

Wave soldering

Partial heating

Soldering Conditions

Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Three times max.

Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Three times max.

Solder bath temperature : 260

°

C max., Duration : 10 sec. max., Number of times: once, Preheating temperature : 120

°

C max. (package surface temperature)

Pin temperature: 300

°

C max. Duration: 3 sec. max. (per pin row)

Recommended

Condition Symbol

IR35-00-3

VP15-00-3

WS60-00-1

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

(2)

µ

PD78056FGC-

×××

-8BT : 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

µ

PD78058FGC-

×××

-8BT : 80-pin plastic QFP (14

×

14 mm, resin thickness 1.4 mm)

Soldering

Method

Infrared reflow

VPS

Wave soldering

Partial heating

Soldering Conditions

Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Twice max.

Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Twice max.

Solder bath temperature : 260

°

C max., Duration : 10 sec. max., Number of times: once, Preheating temperature : 120

°

C max. (package surface temperature)

Pin temperature: 300

°

C max. Duration: 3 sec. max. (per pin row)

Recommended

Condition Symbol

IR35-00-2

VP15-00-2

WS60-00-1

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

66

µ

PD78056F, 78058F

Table 13-1. Surface Mounting Type Soldering Conditions (2/2)

(3)

µ

PD78058FGK-

×××

-BE9: 80-pin plastic TQFP (fine pitch) (12

×

12 mm)

Soldering

Method

Infrared reflow

Soldering Conditions

Package peak temperature: 235

°

C, Duration: 30 sec. max. (at 210

°

C or above),

Number of times: Three times max., Time limit: 7 days

Note

(thereafter 10 hours 125

°

C prebaking required)

Recommended

Condition Symbol

IR35-107-3

VPS

Partial heating

Package peak temperature: 215

°

C, Duration: 40 sec. max. (at 200

°

C or above),

Number of times: Three times max., Time limit: 7 days

Note

(thereafter 10 hours 125

°

C prebaking required)

Pin temperature: 300

°

C max. Duration: 3 sec. max. (per pin row)

VP15-107-3

Note

For the storage period after dry-pack decompression storage conditions are max. 25

°

C, 65 % RH.

Caution Use of more than one soldering method should be avoided (except in the case of partial heating).

67

µ

PD78056F, 78058F

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

µ

PD78058F Subseries.

Language Processing Software

RA78K/0

Notes 1, 2, 3, 4

CC78K/0

Notes 1, 2, 3, 4

DF78054

Notes 1, 2, 3, 4

CC78K/0-L

Notes 1, 2, 3, 4

Assembler package common to 78K/0 Series

C compiler package common to 78K/0 Series

Device file common to

µ

PD78054 Subseries

C compiler library source file common to 78K/0 Series

PROM Writing Tools

PG-1500

PA-78P054GC

PG-1500 controller

Notes 1, 2

Debugging Tools

IE-78000-R

IE-78000-R-A

IE-78000-R-BK

IE-78064-R-EM

Note 8

IE-780308-R-EM

IE-78000-R-SV3

IE-70000-98-IF-B

IE-70000-98N-IF

IE-70000-PC-IF-B

EP-78230GC-R

EP-78054GK-R

EV-9200GC-80

TGK-080SDW

SM78K0

Notes 5, 6, 7

ID78K0

Notes 4, 5, 6, 7

SD78K/0

Notes 1, 2

DF78054

Notes 1, 2, 4, 5, 6, 7

PROM programmer

Programmer adapters connected to PG-1500

PG-1500 control program

In-circuit emulator common to 78K/0 Series

78K/0 Series common to in-circuit emulator (for integrated debugger)

Break board common to 78K/0 Series

Emulation board common to

µ

PD78064 Subseries

Emulation board common to

µ

PD780308 Subseries

Interface adapter and cable when EWS is used as host machine (for IE-78000-R-A)

Interface adapter when PC-9800 series (except notebook type) is used as host machine.

Interface adapter and cable when notebook type PC-9800 series is used as host machine.

Interface adapter when IBM PC/AT

TM and compatibles are used as host machine.

Emulation probe common to

µ

PD78234 Subseries

Emulation probe common to

µ

PD78054 Subseries

Socket to be mounted on the target system board manufactured for 80-pin plastic QFP

(GC-3B9, GC-8BT type)

Adapter to be mounted in the target system board manufactured for 80-pin plastic TQFP

(GK-BE9 type) Product made by TOKYO ELETECH Corporation ((03) 5295-1661).

Contact an NEC dealer regarding the purchase of this product.

System simulator common to 78K/0 Series

Integrated debugger for IE-78000-R-A

IE-78000-R screen debugger

µ

PD78054 Subseries device file

68

µ

PD78056F, 78058F

Real-Time OS

RX78K/0

Notes 1, 2, 3, 4

MX78K0

Notes 1, 2, 3, 4

Real-time OS for 78K/0 Series

Real-time OS for 78K/0 Series

Fuzzy Inference Development Support System

FE9000

Note 1

/ FE9200

Note 6

FT9080

Note 1

/ FT9085

Note 2

FI78K0

Notes 1, 2

FD78K0

Notes 1, 2

Fuzzy knowledge data creation tool

Translator

Fuzzy inference module

Fussy inference debugger

Notes 1. PC-9800 series (MS-DOS TM ) based

2. IBM PC/AT and compatibles (PC DOS

TM

/IBM DOS

TM

/MS-DOS) based

3. HP9000 series 300

TM

(HP-UX

TM

) based

4. HP9000 series 700 TM (HP-UX) based, SPARCstation TM (SunOS TM ) based, EWS4800 series (EWS-UX/

V) based

5. PC-9800 series (MS-DOS + Windows

TM

) based

6. IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based

7. NEWS TM (NEWS-OS TM ) based

8. Maintenance product

Remarks 1. For third party development tools, see 78K/0 Series Selection Guide (U11126E).

2. The RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 are used in combination with the

DF78054.

69

µ

PD78056F, 78058F

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

µ

PD78058F, 78058FY Subseries User’s Manual

µ

PD78056F, 78058F Data Sheet

µ

PD78P058F Data Sheet

78K/0 Series User’s Manual-Instruction

78K/0 Series Instruction Set

78K/0 Series Instruction Table

Document No.

(English)

U12068E

This document

U11796E

U12326E

Document No.

(Japanese)

U12068J

U11795J

U11796J

U12326J

U10904J

U10903J

Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing.

70

µ

PD78056F, 78058F

Development Tool Related Documents (User’s Manual)

RA78K Series Assembler Package

CC78K Series C Compiler

CC78K0 C Compiler

Document Name

RA78K Series Structured Assembler Preprocessor

RA78K0 Assembler Package

CC78K/0 C Compiler Application Note

CC78K Series Library Source File

PG-1500 PROM Programmer

PG-1500 Controller PC-9800 Series (MS-DOS) based

PG-1500 Controller IBM PC Series (PC DOS) based

IE-78000-R

IE-78000-R-A

IE-78000-R-BK

IE-78064-R-EM

IE-780308-R-EM

EP-78230

EP-78054GK-R

SM78K0 System Simulator, Windows based

SM78K Series System Simulator

Operation

Language

Operation

Assembly Language

Structured Assembly Language

Operation

Language

Operation

Language

Programming know-how

EEU-1335

EEU-1291

U10540E

U11376E

U10057E

EEU-1427

EEU-1443

U11362E

EEU-1515

EEU-1468

U10181E

U10092E

Document No.

(English)

EEU-1399

EEU-1404

EEU-1402

U11802E

U11801E

U11789E

EEU-1280

EEU-1284

U11517E

U11518E

EEA-1208

U12322J

U11940J

EEU-704

EEU-5008

U11376J

U10057J

EEU-867

EEU-905

U11362J

EEU-985

EEU-932

U10181J

U10092J

Document No.

(Japanese)

EEU-809

EEU-815

U12323J

U11802J

U11801J

U11789J

EEU-656

EEU-655

U11517J

U11518J

EEA-618

ID78K0 Integrated Debugger, EWS based

ID78K0 Integrated Debugger, PC based

ID78K0 Integrated Debugger, Windows based

SD78K/0 Screen Debugger

PC-9800 Series (MS-DOS) based

SD78K/0 Screen Debugger

IBM PC/AT (PC DOS) based

Reference

External parts user open interface specification

Reference

Reference

Guide

Introduction

Reference

Introduction

Reference

U11539E

U11649E

U10539E

U11279E

U11151J

U11539J

U11649J

EEU-852

U10952J

EEU-5024

U11279J

Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing.

71

µ

PD78056F, 78058F

Embedded Software Documents (User’s Manual)

Document Name

78K/0 Series Real-time OS

78K/0 Series OS MX78K0

Fuzzy Knowledge Data Creation Tool

78K/0, 78K/II, 87AD Series

Fuzzy Inference Development Support System Translator

78K/0 Series Fuzzy Inference Development Support System

Fuzzy Inference Module

78K/0 Series Fuzzy Inference Development Support System

Fuzzy Inference Debugger

Fundamental

Installation

Fundamental

Document No.

(English)

U11537E

U11536E

U12257E

EEU-1438

EEU-1444

EEU-1441

EEU-1458

Document No.

(Japanese)

U11537J

U11536J

U12257J

EEU-829

EEU-862

EEU-858

EEU-921

Other Documents

Document Name

IC Package Manual

Semiconductor Device Mounting Technology Manual

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability/Quality Control System

Electrostatic Discharge (ESD) Test

Guide to Quality Assurance for Semiconductor Devices

Microcomputer Product Series Guide

Document No.

(English)

C10943X

C10535E

C11531E

C10983E

MEI-1202

Document No.

(Japanese)

C10535J

C11531J

C10983J

MEM-539

C11893J

U11416J

Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing.

72

[MEMO]

µ

PD78056F, 78058F

73

74

µ

PD78056F, 78058F

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µ

PD78056F, 78058F

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 800-366-9782

Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 01-504-2787

Fax: 01-504-2860

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

J96. 8

75

µ

PD78056F, 78058F

Purchase of NEC I

2

C components conveys a license under the Philips I

2

C Patent Rights to use these components in an I

2

C system, provided that the system conforms to the I

2

C Standard

Specification as defined by Philips.

FIP is a trademark of NEC Corporation.

IEBus is a trademark of NEC Corporation.

MS-DOS and Windows are either registered trademarks of Microsoft Corporation in the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

HP9000 series 300, HP9000 series, and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NES-OS are trademarks of Sony Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96. 5

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