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[AK4497]
=
Preliminary
=
AK4497
Quality Oriented 32-Bit 2ch DAC
1.
General Description
The AK4497 is a new generation Premium 32-bit 2ch DAC with VELVET SOUND
TM
technology, achieving industry’s leading level low distortion characteristics and wide dynamic range. The AK4497 integrates a newly developed switched capacitor filter “OSR Doubler”, making it capable of supporting wide range signals and achieving low out-of-band noise while realizing low power consumption.
Moreover, the AK4497 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in wide range of applications. The AK4497 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal for a high-resolution audio source playback that are becoming widespread in network audios,
USB-DACs and Car Audio Systems.
Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, Public Audios (PA), IC-Recorders,
Bluetooth Headphones, HD Audio/Voice Conference Systems
2.
Features
THD+N: -115dB
DR, S/N: 127dB (Mono Mode, 130dB)
256 Times Over Sampling
Sampling Rate: 8kHz
768kHz
32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD=6.0/fs,
Ripple:
0.005dB, Attenuation: 100dB
- Short Delay Slow Roll-off, GD=5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low-dispersion Short Delay Filter
- Super Slow Roll-off
2.8MHz, 5.6MHz, 11.2MHz, 22.4MHz DSD Input Support
- Filter1 (fc=39kHz, 2.8MHz mode), Filter2 (fc=76kHz, 2.8MHz mode)
Digital De-emphasis for 32, 44.1, 48kHz sampling
Soft Mute
Digital Attenuator (255 levels and 0.5dB step)
Mono Mode
External Digital Filter Interface
Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I
2
Master Clock
S, DSD
8kHz ~ 32kHz: 1152fs
8kHz ~ 54kHz: 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 64fs or 128fs
~ 768kHz: 64fs
Power Supply:
TVDD=AVDD= 3.3
3.6V (by Internal LDO),
TVDD=AVDD= 1.7
3.6V, DVDD=1.7
1.98V (by external supply),
VDDL/R= 4.75
5.25V
Digital Input Level: CMOS
Package: 64-pin TQFP
Rev. 0.1
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2015/11
[AK4497]
3.
Table of Contents
1.
2.
3.
4.
General Description ........................................................................................................................ 1
Features .......................................................................................................................................... 1
Table of Contents ............................................................................................................................ 2
Block Diagram ................................................................................................................................. 4
5. Pin Configurations and Functions ................................................................................................... 5
■ Pin Configurations .............................................................................................................................. 5
■ Pin Functions ..................................................................................................................................... 6
■ Handling of Unused Pin ..................................................................................................................... 8
6.
7.
Absolute Maximum Ratings ............................................................................................................ 9
Recommended Operating Conditions ............................................................................................ 9
8. Electrical Characteristics .............................................................................................................. 10
■ Analog Characteristics ..................................................................................................................... 10
■ DSD mode ........................................................................................................................................ 11
■ Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) ........................................................................ 12
■ Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz) .................................................... 14
■ Slow Roll-Off Filter Characteristics (fs = 44.1kHz) .......................................................................... 16
■ Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz) ...................................................... 18
■ Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz) ................................................... 20
■ DSD Filter Characteristics ................................................................................................................ 21
■ DC Characteristics ........................................................................................................................... 22
■ Switching Characteristics ................................................................................................................. 23
■ Timing Diagram ................................................................................................................................ 28
9. Functional Descriptions................................................................................................................. 33
■ D/A Conversion Mode ...................................................................................................................... 35
■ D/A Conversion Mode Switching Timing ......................................................................................... 35
■ System Clock ................................................................................................................................... 37
■ Power ON/OFF Sequence in FS Auto Detect Mode (L DOE pin = “H”) ........................................... 42
■ Audio Interface Format .................................................................................................................... 45
■ Digital Filter ...................................................................................................................................... 57
■ De-emphasis Filter (PCM) ............................................................................................................... 58
■ Output Volume (PCM, DSD, EXDF) ................................................................................................ 58
■ Gain Adjustment Function (PCM, DSD, EXDF) ............................................................................... 59
■ Zero Detection (PCM, DSD, EXDF) ................................................................................................. 60
■ L/R Channel Output Signal Select, Phase Inversion Function (PCM, DSD, EXDF) ....................... 61
■ Sound Quality (PCM, DSD, EXDF) .................................................................................................. 62
■ DSD Signal Full Scale (FS) Detection ............................................................................................. 63
■ Soft Mute Operation (PCM, DSD, EXDF) ........................................................................................ 64
■ LDO .................................................................................................................................................. 65
■ Shutdown Switch .............................................................................................................................. 65
■ Over Current Protection for Analog Output Pins ............................................................................. 65
■ Power Up/Down Function ................................................................................................................ 66
■ Synchronize Function (PCM, EXDF) ............................................................................................... 73
■ Register Control Interface ................................................................................................................ 75
■ Register Map .................................................................................................................................... 79
■ Register Definitions .......................................................................................................................... 81
10. Recommended External Circuits .................................................................................................. 91
11. Package ........................................................................................................................................ 95
■Outline Dimensions ........................................................................................................................... 95
■ Material & Lead Finish ..................................................................................................................... 96
■ Marking ............................................................................................................................................. 96
12. Ordering Guide ............................................................................................................................. 97
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[AK4497]
■ Ordering Guide ................................................................................................................................. 97
IMPORTANT NOTICE ............................................................................................................................. 98
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[AK4497]
4.
Block Diagram
PDN
BICK/BCK/DCLK
SDATA/DINL/DSDL
LRCK/DINR/DSDR
TDMO
LDOE
LDO
PCM
Data
Interface
TVDD DVDD DVSS AVDD
SSLOW/WCK
TDM0/DCLK
DEM0/DSDL
GAIN/DSDR
External
DF
Interface
DSD
Data
Interface
Normal path
DSDD bit
“0”
DSD
Filter
DATT
Soft Mute
AVSS
De-emphasis
&
Interpolator
Volume bypass
DSDD bit
“1”
Modulator
SMUTE/CSN
SD/ CCLK/SCL
SLOW/CDTI/SDA
Control
Register
SCF
Vref
SCF
Clock
Divider
MCLK停止検出
Oscillator
IREF
VSSL
VDDL
AOUTLN
AOUTLP
VCML
VREFHL
VREFLL
VREFLR
VREFHR
VCMR
AOUTRP
AOUTRN
VDDR
VSSR
PSN DIF0/
DIF1/
DZFL DZFR
DIF2/
CAD0
TDM1 DCHAIN
INVR ACKS/
CAD1
TESTE HLOAD
/I2C
Block Diagram
MCLK EXTR
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2015/11
■
Pin Configurations
5.
Pin Configurations and Functions
[AK4497]
Rev. 0.1
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2015/11
[AK4497]
■
Pin Functions
No. Pin Name I/O
1 LDOE
Function
I
Internal LDO Enable Pin.
“L”: Disable, “H”: Enable
2 PDN I
Power-Down Mode Pin
When at “L”, the AK4497 is in power-down mode and is held in reset. The
AK4497 must always be reset upon power-up.
BICK I Audio Serial Data Clock Pin in PCM Mode
3
BCK
DCLK
I Audio Serial Data Clock Pin
I DSD Clock Pin in DSD Mode (DSDPATH bit =
“1”)
SDATA
4
DINL
DSDL
LRCK
DINR 5
DSDR
SSLOW
6
WCK
7 TDMO
8
9
10
11
12
13
14 PSN
15
16
17
18
SMUTE
CSN
SD
CCLK
SCL
SLOW
CDTI
SDA
DIF0
DZFL
DIF1
DZFR
DIF2
CAD0
HLOAD
I2C
DEM0
DSDL
GAIN
DSDR
ACKS
CAD1
I Audio Serial Data Input Pin in PCM Mode
I Lch Audio Serial Data Input Pin
I DSD Lch Data Input Pin in DSD Mode(DSDPATH bit =
“1”)
I L/R Clock Pin in PCM Mode
I Rch Audio Serial Data Input Pin
I
DSD Rch Data Input Pin in DSD Mode(DSDPATH bit =
“1”)
I Digital Filter Select Pin in Parallel Control Mode
I Word Clock input pin
O Audio Serial Data Onput in Daisy Chain mode (Internal pull-down pin)
I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
I Chip Select Pin in Serial Control Mode
I Digital Filter Select Pin in Parallel Control Mode
I Control Data Clock Pin in Serial Control Mode
I
I2C=”H”: Control Data Clock Input Pin
I Digital Filter Select Pin in Parallel Control Mode
I Control Data Input Pin in Serial Control Mode
I/O
I2C=”H”: Control Data Input Pin
I Digital Input Format 0 Pin in Parallel Control Mode
O Lch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
I Digital Input Format 1 Pin in Parallel Control Mode
O Rch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
I Digital Input Format 2 Pin in Parallel Control Mode
I Chip Address 0 Pin in Serial Control Mode
I
Parallel or Serial Select Pin (Internal pull-up pin)
“L”: Serial Control Mode, “H”: Parallel Control Mode
I Heavy Load Mode Enable Pin in Parallel Control Mode.
Resister Control Interface Pin in Serial Control Mode.
I De-emphasis Enable 0 Pin in Parallel Control Mode
I DSD Lch Data Input Pin in DSD Mode
(DSDPATH bit =”0”)
I Output Gain Control Pin in Parallel control mode (+2.5dB)
I DSD Rch Input Pin in DSD Mode
(DSDPATH bit =”0”)
I
Auto Setting Mode Select Pin in Parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
I Chip Address 1 Pin in Serial Control Mode
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[AK4497]
No. Pin Name I/O
19
TDM0
DCLK
Function
I
TDM Mode select pin in Parallel control mode.
I
DSD clock Pin in DSD Mode (DSDPATH bit =
“0”)
I
TDM Mode select pin in Parallel control mode.
20 TDM1
21 DCHAIN
22 INVR
23 TESTE
I
I
I
Daisy Chain Mode select pin in Parallel control mode.
Rch output data invert enable pin in Parallel control mode.
Testmode Enable pin. (Internal pull-down pin)
24-26 VREFHR I Rch High Level Voltage Reference Input Pin
27-29 VREFLR I Rch Low Level Voltage Reference Input Pin
30 VCMR I
Right channel Common Voltage Pin,
Normally connected to VREFLR with a 10uF electrolytic cap.
31,32 AOUTRN O Rch Negative Analog Output Pin
33,34 AOUTRP O Rch Positive Analog Output Pin
35-37 VDDR
38-40 VSSR
41-43 VSSL
44-46 VDDL
62
DVDD
- Rch Analog Power Supply Pin
- Analog Ground Pin
- Analog Ground Pin
-
Lch Analog Power Supply Pin .
47,48 AOUTLP O Lch Positive Analog Output Pin
49,50 AOUTLN O Lch Negative Analog Output Pin
51 VCML -
Left channel Common Voltage Pin
Normally connected to VREFLL with a 10uF electrolytic cap.
52-54 VREFLL
55-57 VREFHL
58
59
EXTR
AVDD
I
I
I
-
-
Lch Low Level Voltage Reference Input Pin
Lch High Level Voltage Reference Input Pin
External Resistor Connect Pin
Rext=33kΩ(±1%) toAVSS
(LDOE pin = “H”)
Analog Power Supply Pin, 3.0
3.6V
(LDOE pin = “L”)
Analog Power Supply Pin, 1.7
3.6V
60 AVSS
61 MCLK
- Analog Ground Pin
I Master Clock Input Pin
(LDOE p in = “H”)
O LDO Output Pin,
-
This pin should be connected to DVSS with 1.0µF.
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7
1.98V
63
DVSS - Digital Ground Pin
64 TVDD
-
-
(LDOE pin = “H”)
Digital Power Supply Pin, 3.0
3.6V
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7
3.6V
Note 1. All input pins except internal pull-up/down pins must not be left floating.
Note 2. The AK4497 must be reset by PDN pin after changing Parallel/Serial mode by the PSN pin.
Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings.
Rev. 0.1
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■
Handling of Unused Pin
Unused I/O pins must be connected appropriately.
(1) Parallel Mode (PCM mode only)
Classification Pin Name
Analog
Digital
Setting
AOUTLP, AOUTLN Open
AOUTRP, AOUTRN Open
I2C, TESTE Connect to DVSS
(2) Serial Mode
1. PCM Mode
Classification Pin Name
Analog
Digital
Setting
AOUTLP, AOUTLN Open
AOUTRP, AOUTRN Open
TESTE Connect to DVSS
2. DSD Mode
Classification Pin Name
Analog
AOUTLP, AOUTLN
AOUTRP, AOUTRN
Digital
BICK, SDATA, LRCK, WCK, TDM1,
DCHAIN, INVR, TESTE
Setting
Open
Open
Connect to DVSS
Pull-up and Pull-down pins List
Classification Pin Name Setting pull-up pin (typ=100k
Ω)
PSN Connect to TVDD pull-down pin (typ=100k
Ω)
TDMO, DZFL, DZFR, TESTE Connect to DVSS
[AK4497]
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[AK4497]
6.
Absolute Maximum Ratings
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4 )
Parameter Symbol
Power
Supplies:
Digital I/O
Digital Core
Analog
Analog
|AVSS
TVDD
DVDD
AVDD
VDDL/R
GND
Min.
0.3
0.3
0.3
0.3
-
Max.
4.0
2.5
4.0
6.0
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Temperature (Power applied)
Storage Temperature
IIN
VIND
Ta
Tstg
-
0.3
40
65
0.3
10
TVDD+0.3
85
150
Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Unit
mA
V
C
C
V
V
V
V
V
7.
Recommended Operating Conditions
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4 )
Parameter Symbol
■ LDOE pin= “L”
Power Supplies
Voltage Reference
Digital I/O
Analog
Digital Core
Analog
■ LDOE pin= “H”
Digital I/O
Analog
Analog
“H” voltage reference
“L” voltage reference
TVDD
AVDD
DVDD
VDDL/R
TVDD
AVDD
VDDL/R
VREFHL/R
VREFLL/R
Min.
DVDD
DVDD
1.7
4.75
3.0
3.0
4.75
VDDL/R-0.5
-
Typ.
1.8
1.8
1.8
5.0
3.3
Max.
3.6
3.6
1.98
5.25
3.6
Unit
V
V
V
V
V
3.3
5.0
-
VSSL/R
3.6
5.25
VDDL/R
-
V
V
V
V
Note 4. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD, VDDL/R and DVDD is not critical.
Note 7. The analog output voltage scales with the voltage of (VREFH
VREFL).
AOUT (typ.@0dB) = (AOUT+)
(AOUT
) =
2.8Vpp
(VREFHL/R
VREFLL/R)/5.
* TVDD must be powered up befor or at the same time of DVDD when the LDOE pin =
“L”.
* The internal LDO outputs DVDD (1.8V) when the LDOE pin =
“H”. The power-up sequence between
VDDL/R and TVDD or VDDL/R and AVDD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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[AK4497]
8.
Electrical Characteristics
■
Analog Characteristics
(Ta=25
C; LDOE=L, AVDD=TVDD=DVDD=3.3V; AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; R
L
1k
; BICK=64fs; Signal Frequency =
1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure
72 ; unless otherwise specified.)
Parameter Min. Typ. Max. Unit
Resolution
Dynamic Characteristics (Note 8)
THD+N fs=44.1kHz
BW=20kHz fs=96kHz
BW=40kHz
0dBFS
60dBFS
0dBFS
60dBFS fs=192kHz
BW=40kHz
BW=80kHz
0dBFS
60dBFS
60dBFS
Dynamic Range (
60dBFS with A-weighted)( Note 9 , Note 11 )
S/N (A-weighted) ( Note 10 , Note 11 )
S/N (Mono mode, A-weighted) ( Note 11 )
Interchannel Isolation (1kHz)
-
-
-
-
-
122
122
125
110
-
-115
-64
-113
-61
-110
-61
-58
127
127
130
120
32
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
-
-
-
Bits
DC Accuracy
Interchannel Gain Mismatch
Output Voltage (GC[2:0]=000)
Load Resistance (HLOAD=H)
-
-
2.65
3.55
-
120
-
0.15
2.8
3.75
-
-
0.3
20
2.95
3.95
-
25 dB ppm/
C
Vpp k
pF
Note 8. Measured by Audio Precision System Two. Averaging mode.
Note 9. Figure 72 External LPF Circuit Example. 101dB at 16bit data and 118dB at 20bit data.
External LPF Circuit Example. S/N does not depend on the input data size.
Note 11. SC[1:0] bits =
“00” or “01”
Note 12. The voltage on (VREFH
VREFL) is held +5V externally.
Note 13. Full scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R
VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)
(AOUT
) =
2.8Vpp
(VREFHL/R
VREFLL/R)/5.
Note 14. Regarding Load Resistance, AC load is 1k
(min) with a DC cut capacitor. DC load is 1.5k ohm
(min) without a DC cut capacitor . The load resistance value is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load must be minimized.
dB dB dB dB dB dB dB dB dB dB dB
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[AK4497]
(Ta=25
C; AVDD=TVDD=3.3V, DVDD=1.8V(@LDOE=
“L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; Internal OPAMP GBW=30MHz (SC[1:0] bit=”00”); 2Vrms output mode
(GC[2:0] bit=
“000” or GAIN= “L”); Heavy load drive mode=off(HLOAD bit= “0” or HLOAD= “L”); unless otherwise specified.)
Power Supplies
Parameter
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R(total)
VREFHL/R
AVDD
TVDD
LDOE=
“H”
LDOE=
“L” fs= 44.1kHz fs= 96kHz fs = 192kHz
DVDD
LDOE=
“L” fs= 44.1kHz fs= 96kHz fs = 192kHz
Total Idd per channel (HLOAD=
“H”)
・fs=44.1kHz
TVDD+AVDD+VDDL/R+DVDD
Min.
-
-
-
-
Typ.
64
1
1
8
13
20
1
8
13
20
45
10
Max.
mA/ch
A
Unit
mA mA mA mA mA mA mA mA mA mA
Note 15. In the power down mode. The PSN, DEM0 pin = DVDD, and all other digital input pins including clock pins (MCLK, BICK and LRCK) are held to DVSS.
Note 16. The DVDD pin becomes an output pin when the LDOE pin =
“H”.
■
DSD mode
(Ta=25
C; LDOE=L, AVDD=TVDD=3.3V, DVDD=1.8V; AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Signal Frequency = 1kHz; Measurement bandwidth = 20Hz
~ 20kHz; External Circuit; unless otherwise specified.)
Parameter
Resolution
Dynamic Characteristics
Min.
-
Typ.
-
Max.
32
Unit
Bits
THD+N DSD dataStream: 2.8224MHz 0dBFS
DSD dataStream: 5.6448MHz 0dBFS
DSD dataStream: 11.2896MHz 0dBFS
S/N
(A-weighted,
DSD dataStream: 2.8224MHz Digital
“0”
DSD dataStream: 5.6448MHz Digital
“0”
Normal path)
DSD dataStream: 11.2896MHz
Digital
“0”
-
-
-
-
-
-
-115
-115
-115
127
127
127
-
-
-
-
-
- dB dB dB dB dB dB
DC Accuracy
Output Voltage (Normal path) (
Output Voltage (Volume Bypass) (
2.65
2.6
2.8
2.5
2.95 Vpp
2.63 Vpp
Note 17. Analog characteristics are not guaranteed when the DSD dataStream is 22.5782MHz.
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[AK4497]
■
Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Symbol Min. Typ. Max. Unit Parameter
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
PB
-
PB
SB
PR
SA
GD
0
-
0
24.1
100
-
22.05
29.2
20.0
-
20.0
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
20.0kHz - +0.1/-0.2 - dB
Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
PB
PB
SB
PR
SA
GD
0
-
0
52.5
100
-
48.0
29.2
43.5
-
43.5
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
40.0kHz - +0.1/-0.6 - dB
Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
105
100
-
96.0
29.2
87.0
-
87.0
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
80.0kHz - +0.1/-2.0 - dB
Note 18. Frequency response refers to the output level (0dB) of a 1kHz, 0dB sine wave input.
Note 19. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@
0.01dB),
SB=0.546×fs.
Note 20. The first step of the Interpolator. This is a passband gain amplitude of the 4 times oversampling filter.
Note 21. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
Rev. 0.1
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2015/11
[AK4497]
Figure 1. Sharp Roll-off Filter Frequency Response
Rev. 0.1
Figure 2. Sharp Roll-off Filter Passband Ripple
- 13 -
2015/11
[AK4497]
■
Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Symbol Min. Typ. Max. Unit Parameter
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
24.1
100
-
22.05
6.25
20.0
-
20.0
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
20.0kHz - +0.1/ TBD - dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
52.5
100
-
48.0
6.25
43.5
-
43.5
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
40.0kHz - +0.1/ TBD - dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
105
100
-
96.0
6.25
87.0
-
87.0
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
80.0kHz - +0.1/ TBD - dB
Note 22. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@
0.01dB),
SB=0.546×fs.
Rev. 0.1
- 14 -
2015/11
[AK4497]
Figure 3. Short delay Sharp Roll-off Filter Frequency Response
Rev. 0.1
Figure 4. Short delay Sharp Roll-off Filter Passband Ripple
- 15 -
2015/11
[AK4497]
■
Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Symbol Min. Typ. Max. Unit Parameter
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
PB
-
PB
SB
PR
SA
GD
0
-
0
39.1
94
-
18.2
6.63
4.4
-
4.4
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
20.0kHz - +0.1/TBD - dB
Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
PB
PB
SB
PR
SA
GD
0
-
0
85.0
94
-
39.6
6.63
9.5
-
9.5
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
40.0kHz - +0.1/ TBD - dB
Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“1”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
171
94
-
79.2
6.63
19.1
-
19.1
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
80.0kHz - +0.1/ TBD -
Note 23. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@
0.01dB), SB = 0.8889 × fs. dB
Rev. 0.1
- 16 -
2015/11
[AK4497]
Figure 5. Slow Roll-off Filter Frequency Response
Rev. 0.1
Figure 6. Slow Roll-off Filter Passband Ripple
- 17 -
2015/11
[AK4497]
■
Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Symbol Min. Typ. Max. Unit Parameter
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
24.1
100
-
22.05
6.25
20.0
-
20.0
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
20.0kHz - +0.1/ TBD - dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
52.5
100
-
48.0
6.25
43.5
-
43.5
0.005
- kHz kHz kHz kHz dB dB
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
40.0kHz - +0.1/ TBD - dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD= TVDD=3.0
3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.01dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
-
-
PB
SB
PR
SA
GD
0
-
0
105
100
-
96.0
6.25
87.0
-
87.0
0.005
-
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
80.0kHz - +0.1/ TBD -
Note 24. The passband and stopband frequencies scale with fs. For example, PB = 0.4535 × fs
(@
0.01dB), SB = 0.546 × fs. kHz kHz kHz kHz dB dB
1/fs dB
Rev. 0.1
- 18 -
2015/11
[AK4497]
Figure 7. Short Delay Slow Roll-off Filter Frequency Response
Figure 8. Short Delay Slow Roll-off Filter Passband Ripple
Rev. 0.1
- 19 -
2015/11
[AK4497]
■
Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V; Normal Speed Mode
DEM=OFF; SD bit pr SD pin
=“1”, SLOW bit or SLOW pin=“0”, SSLOW bit or SSLOW pin =”0”)
Parameter
Digital Filter
Frequency Response
0.05dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
Group Delay Distortion
Symbol
PB
-
PB
SB
PR
SA
GD
ΔGD
Min.
0
-
0
25.7
80
-
Typ.
22.5
10.0
±0.035
Max.
18.4
-
18.4
0.05
-
Unit
kHz kHz kHz kHz dB dB
1/fs
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
20.0kHz - +0.1/-0.2 - dB
Low-dispersion Short Delay Filter Characteristics (fs = 96kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V; Double Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter
Digital Filter
Frequency Response
Stopband Attenuation ( Note 19 )
Group Delay
Group Delay Distortion
0.05dB
6.0dB
Symbol
PB
PB
SB
PR
SA
GD
ΔGD
Min.
0
-
0
55.9
80
-
Typ.
49.0
10.0
±0.035
Max.
40.1
-
40.1
0.05
-
Unit
kHz kHz kHz kHz dB dB
1/fs
1/fs
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
40.0kHz - +0.1/ -0.6 - dB
Low-dispersion Short Delay Filter Characteristics (fs = 192kHz)
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0”, SLOW bit=“0”)
Parameter Symbol Min. Typ. Max. Unit
Digital Filter
Frequency Response
0.05dB
6.0dB
Stopband Attenuation ( Note 19 )
Group Delay
Group Delay Distortion
Digital Filter + SCF ( Note 18 )
Frequency Response: 0
80.0kHz
-
-
PB
SB
PR
SA
GD
ΔGD
0
-
0
112
80
-
-
98.0
10.0
±0.035
+0.1/ -2.0
80.2
-
87.0
0.05
-
- kHz kHz kHz kHz dB dB
1/fs
1/fs dB
Rev. 0.1
- 20 -
2015/11
[AK4497]
■
DSD Filter Characteristics
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V; fs=44.1kHz; D/P
bit=“1”, DSDF bit = “0”, DSDSEL[1:0] bits = “00” (
Parameter Min. Typ. Max. Unit
Digital Filter Response
Frequency Response
20kHz
50kHz
100kHz
-0.77
-5.25
-18.80 dB dB dB
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V; fs=44.1kHz; D/P
bit=“1”, DSDF bit=“1” DSDD bit=“1”, DSDSEL[1:0]= “00” (
Parameter
Digital Filter Response
Min. Typ. Max. Unit
Frequency Response
20kHz
100kHz
150kHz
-0.19
-5.29
-18.91 dB dB dB
Note 25. The peak level of DSD signal should be in the range of 25% ~ 75% duty according to the SACD format book (Scarlet Book).
Note 26. The frequency response refers to the output level of 0dB when a 1kHz 25%~75% duty sine wave is input.
Note 27. The frequency (20k, 100k and 200kHz) will be doubled when the sampling speed is 128fs
(DSDSEL[1:0] bits =
“01”) and it will be quadrupled when the sampling speed is 256fs
(DSDSEL[1:0] bits =
“10”).
Rev. 0.1
- 21 -
2015/11
[AK4497]
■
DC Characteristics
(Ta=-40~85
C; VDDL/R=4.75
5.25V, AVDD=TVDD=3.0
3.6V, DVDD=1.7~1.98V)
Symbol Min. Typ. Parameter
TVDD=1.7
3.0V
High-Level Input Voltage
Low-Level Input Voltage
TVDD=3.0V
3.6V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
VIH
VIL
80%TVDD
-
70%TVDD
-
-
-
-
-
Max.
-
20%TVDD
-
30%TVDD
Unit
High-Level Output Voltage
(TDMO, DZFL, DZFR pins: Iout=-100µA)
Low-Level Output Voltage
(except SDA pin: Iout= 100µA)
(SDA pin, 2.0V
TVDD
3.6V: Iout= 3mA)
(SDA pin, 1.7V
TVDD
2.0V: Iout= 3mA)
VOH
VOL
TVDD
-
0.5 -
-
-
0.5
V
V
Input Leakage Current
VOL
VOL
Iin
-
-
-
-
-
0.4
20%TVDD
10
V
V
A
Note 28. The TESTE pin has internal pull-down and the PSN pin has internal pull-up devices. Therefore the TESTE and PSN pins are not included in this specification.
V
V
V
V
Rev. 0.1
- 22 -
2015/11
[AK4497]
■
Switching Characteristics
(Ta=-40~85
C; VDDL/R=4.75
5.25V, TVDD=AVDD=1.7
3.6V, DVDD=1.7~1.98V, C
L
=20pF)
Parameter Symbol Min. Typ. Max.
Master Clock Timing
Unit
Frequency
Duty Cycle
Minimum Pulse Width fCLK dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
49.152
60
MHz
% nsec nsec
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time fsn fsd fsq fso fsh
Duty fsn fsd fsq tLRH tLRL fsn fsd tLRH tLRL fsn tLRH tLRL
8
54
108
45
8
54
108
1/128fs
1/128fs
8
54
1/256fs
1/256fs
8
1/512fs
1/512fs
384
768
54
108
216
55
54
108
216
54
108
54 kHz kHz kHz kHz kHz
% kHz kHz kHz nsec nsec kHz kHz nsec nsec kHz nsec nsec
Note 29. The MCLK frequency must be changed while the AK4497 is in reset state by setting the PDN pin
=
“L” or RSTN bit = “0”.
Rev. 0.1
- 23 -
2015/11
[AK4497]
(Ta=-40~85
C; VDDL/R=4.75
5.25V, TVDD=AVDD=1.7
3.6V, DVDD=1.7~1.98V, C
L
=20pF, PSNpin=L,
AFSDbit= "1")
Parameter
Master Clock Timing (FS Auto Detect Mode)
Symbol Min. Typ. Max. Unit
Frequency
Duty Cycle
Minimum Pulse Width fCLK dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
49.152
60
MHz
% nsec nsec
LRCK Clock Timing (FS Auto Detect Mode) ( Note 30 )
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode fsn fsd
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle fsq fso fsh
Duty
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time fsn fsd fsq tLRH tLRL fsn fsd tLRH tLRL fsn tLRH tLRL
30
88.2
176.4
45
30
88.2
176.4
1/128fs
1/128fs
30
1/256fs
1/256fs
30
1/512fs
1/512fs
384
768
54
108
216
55
54
108
216
54
108
54 kHz kHz kHz kHz kHz
% kHz kHz kHz nsec ns kHz kHz nsec nsec kHz nsec nsec
Note 30. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when the AK4497 is in Sampling Frequency Auto Detect Mode.
Rev. 0.1
- 24 -
2015/11
Parameter
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “
LRCK Edge to BICK “
SDATA Hold Time
SDATA Setup Time
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “
LRCK Edge to BICK “
SDATA Hold Time
SDATA Setup Time
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “
LRCK Edge to BICK “
TDMO Setup time BICK “
”
TDMO Hold time BICK “
SDATA Hold Time
SDATA Setup Time
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
BICK Pulse Width Low
BICK Pulse Width High
BICK “
LRCK Edge to BICK “
TDMO Setup time BICK “
”
TDMO Hold time BICK “
SDATA Hold Time
SDATA Setup Time
Symbol
tBCK tBCK tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tBCK tBCK tBCKL tBCKH tBLR tLRB tBSS tBSH tSDH tSDS tBCK tBCKL tBCKH tBLR tLRB tBSS tBSH tSDH tSDS
Min.
1/256fsn
1/128fsd
1/64fsq
1/64fso
1/64fsh
9
9
5
5
5
5
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
1/512fsn
14
14
14
14
5
5
5
5
Note 31. BICK rising edge must not occur at the same time as LRCK edge.
Note 32. Daisy Chain Mode, fsd (max) = 96 kHz if
“TVDD < 3.0V”.
Note 33. Daisy Chain Mode, fsn (max) = 48 kHz if
“TVDD < 3.0V”.
Note 34
. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.
Typ. Max.
[AK4497]
Unit
nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec
Rev. 0.1
- 25 -
2015/11
[AK4497]
Parameter
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “
” to WCK Edge
WCK Period
WCK Edge to BCK “
”
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
DINL/R Setup Time
DSD Audio Interface Timing
Symbol
tB tBL tBH tBW tWCK tWB tWCKL tWCKH tDH tDS
Min.
27
10
10
5
1.3
5
54
54
5
5
Typ. Max.
Sampling Frequency
fs 30 48 kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R ( Note 35 )
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R ( Note 35 )
tDCK tDCKL tDCKH tDDD tDCK tDCKL tDCKH tDDD
144
144
20
72
72
10
1/64fs
1/128fs
20
10 nsec nsec nsec nsec nsec nsec nsec nsec
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High tDCK tDCKL tDCKH tDDD
36
36
5
1/256fs
5 nsec nsec nsec nsec
DCLK Edge to DSDL/R ( Note 35 )
(512fs mode, DSDSEL [1:0] bit = “11”)
DCLK Period
DCLK Pulse Width Low tDCK tDCKL 18
1/512fs nsec nsec
DCLK Pulse Width High
DSDL/R Setup Time tDCKH tDDS
18
5 nsec nsec
DSDL/R Hold Time tDDH 5 nsec
Note 35. DSD data transmitting device must meet this time
. “tDDD” is defined from DCLK “↓” until
DSDL/R edge when DCKB bit =
“0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R edge when DCKB bit =
“1”. If the audio data format is in phase modulation mode, “tDDD” is defined from DCLK edge
“↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
Note 36. The AK4497 does not support Phase Modulation Mode in DSD512fs Mode.
Unit
nsec nsec nsec nsec usec nsec nsec nsec nsec nsec
Rev. 0.1
- 26 -
2015/11
[AK4497]
Parameter
Control Interface Timing (3-wire IF mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN
“H” Time
CSN
“
” to CCLK “
”
CCLK “
” to CSN “
”
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling ( Note 37 )
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Power-down & Reset Timing ( Note 38 )
PDN Accept Pulse Width
PDN Reject Pulse Width
Symbol
tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP
Cb tAPD tRPD
Min.
200
80
80
40
40
150
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
150
Typ.
Note 37. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 38. The AK4497 can be reset by bringing the PDN pin “L” to “H” upon power-up.
Note 39. I
2
C -bus is a trademark of NXP B.V.
Max. Unit
nsec nsec nsec nsec nsec nsec nsec nsec
400
-
-
-
1.0
-
-
-
-
0.3
-
50
400
30 kHz usec usec usec usec usec usec usec usec usec usec nsec pF nsec nsec
Rev. 0.1
- 27 -
2015/11
■
Timing Diagram
MCLK
LRCK
BICK
WCK
BCK
[AK4497]
1/fCLK tCLKH tLRH tBCKH tWCKH
1/fs tBCK tCLKL tLRL tWCK tBCKL tB tWCKL tBH tBL
Figure 9. Clock Timing
VIH
VIL dCLK=tCLKH x fCLK, tCLKL x fCLK
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Rev. 0.1
- 28 -
2015/11
[AK4497]
LRCK
VIH
VIL tBLR tLRB
BICK
VIH
VIL tBSS tBSH
TDMO 50%TVDD tSDS tSDH
SDATA
VIH
VIL
Figure 10. Audio Interface Timing (PCM Mode)
WCK
BCK
DINL
DINR
VIH
VIL tBW tWB
VIH
VIL tDS tDH
Figure 11. Audio Interface Timing (External Digital Filter I/F Mode)
VIH
VIL
Rev. 0.1
- 29 -
2015/11
[AK4497]
Rev. 0.1 tDCKL tDCK tDCKH
DCLK
VIH
VIL tDDD
DSDL
DSDR
VIH
VIL tDDD
DSDL
DSDR
VIH
VIL
DSD Audio Interface Timing (DSD64fs, 128fs, 256fs Mode) tDCKL tDCK tDCKH
DCLK
VIH
VIL tDDS tDDH
DSDL
DSDR
VIH
VIL
DCLK
DSD Audio Interface Timing (DSD512fs Mode)
Figure 12
. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”) tDCKL tDCK tDCKH
VIH
VIL tDDD tDDD
DSDL
DSDR
VIH
VIL tDDD tDDD
DSDL
DSDR
VIH
VIL
Figure 13
. Audio Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
- 30 -
2015/11
CSN
CCLK
CDTI
CSN
CCLK
CDTI D3
[AK4497]
VIH
VIL tCSS tCCKL tCCKH tCCK
VIH
VIL
C1 tCDS tCDH
C0 R/W
Figure 14. WRITE Command Input Timing
A4 tCSW
VIH
VIL
VIH
VIL tCSH
VIH
VIL
D2 D1 D0
Figure 15. WRITE Data Input Timing
VIH
VIL
Rev. 0.1
- 31 -
2015/11
SDA tBUF tLOW tR
SCL tHD:STA
Stop Start tHIGH tF tHD:DAT tSU:DAT tSU:STA
Start
Figure 16. I
2
C Bus Mode Timing tAPD tRPD
PDN
Figure 17. Power Down & Reset Timing
[AK4497]
VIH
VIL tSP tSU:STO
Stop
VIH
VIL
VIL
Rev. 0.1
- 32 -
2015/11
[AK4497]
9.
Functional Descriptions
Each function of the AK4497 is controlled by Pins (pin control mode) and Registers (register control
mode) ( Table 1 ). Select the control mode by setting the PSN pin. The AK4497 must be powered down
when changing the PSN pin setting. There is a possibility of malfunction if the device is not powered down when changing the control mode since the previous setting is not initialized. Register settings are invalid in pin control mode, and pin settings are invalid in register control mode.
shows available functions of each control mode and Table 3
shows available functions in
PCM/DSD/EXDF mode.
Table 1. Pin/Register Control Mode Select
PSN pin Control Mode
L
H
Register Control Mode
Pin Control Mode
Function
Table 2. Function List @Pin/Register Control Mode
DSD/EXDF Mode Select
System Clock Setting Select
Audio Format Select
TDM Mode
Digital Filter Select
De-emphasis Filter Select
Digital Attenuator
Zero Detection
Mono Mode
Output signal select
(Monaural, Channel select)
Output signal polarity select
(Invert)
Sound Color Select
DSD Full Scale Detect
Soft Mute
Register Reset
Clock Synchronization Function
Resistor Control
Gain Control
Heavy Load Mode
(Y: Available, -: Not available)
Pin Control Mode
-
Y
Y
Y
Y
Y
-
-
-
-
Y
-
-
Y
Y
-
Y
-
-
Register Control
Mode
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Rev. 0.1
- 33 -
2015/11
[AK4497]
Function
Table 3. Function List of PCM/EXDF/DSD mode @Register Control Mode
Default Add Bit PCM EXDF DSD
PCM/DSD/EXDF Mode Select
System clock setting @DSD mode
System clock setting @EXDF mode
PCM mode
512fs
16fs(fs=44.1kHz)
00H
02H
02H
00H
EXDF
DP
DCKS
ECS
Y
-
-
Y
-
Y
Y
Y
-
Digital Filter select @DSD mode
39kHz filter 09H DSDF - - Y
Digital Filter select @PCM mode
Short delay sharp roll off filter
OFF
Normal Path
32bit MSB
01-02-05H
01H
06H
00H
SD
SLOW
SSLOW
Y
DEM[1:0] Y
DSDD
-
DIF[2:0] Y
-
-
-
-
-
-
Y
-
De-emphasis Response
Path select @ DSD mode
Audio Data Interface Format
@ PCM Mode
Audio Data Interface Format
@ EXDF Mode
TDM Interface Format
Daisy Chain
Attenuation Level
Data Zero Detect Enable
Inverting Enable of DZF
Mono/Stereo mode select
Data Invert mode select
The data selection of L channel and
R channel
Sound Color Select
DSD Mute Function @ Full scale
Detected
Soft Mute Enable
RSTN
Clock Synchronization Function
(Y: Available, N/A: Not available)
32bit LSB
Normal Mode
Normal Mode
0dB
Disable
“H” active
Stereo
OFF
R channel
Off
Disable
Normal
Operation
RST
Enable
00H
0AH
0BH
03-04H
01H
02H
02H
05H
02H
08H
06H
01H
00H
07H
DIF[2:0] -
TDM[1:0] Y
DCHAIN
ATT[7:0]
DZFE
DZFB
MONO
INVL/R
Y
Y
SELLR
SC[2:0]
DDM
SMUTE
RSTN
SYNCE
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
Rev. 0.1
- 34 -
2015/11
[AK4497]
■
D/A Conversion Mode
The AK4497 can perform D/A conversion for either PCM data or DSD data. The DP bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from the #16, #17 and #19 pins if DSDPATH bit =
“0” and DSD data can be input from the #3, #4, and #5 pins if DSDPATH bit = “1”. The AK4497 must be reset by setting RSTN bit =
“0” when PSM/DSD mode is changed by DP bit or when DSD signal input pins are changed by DSDPATH bit. It takes about 2 ~ 3/fs to change the mode. Wait 4/fs or more to change DP or DSDPATH bit setting after setting RSTN bit =
“0”.
When the AK4497 is in pin control mode, PCM mode is only available. External digital filter I/F can be selected by setting DP bit =
“0” and EXDF bit = “1”. When using an external digital filter (EXDF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit controls the modes. When switching internal and external digital filters by EXDF bit, the AK4497 must be reset by RSTN bit. A Digital filter switching takes 2~3k/fs. The AK4497 is in DSD mode when DP bit =
“1” and EXDF bit “1”.
Table 4. PCM/DSD/EXDF Mode Control
Pin Assignment
DP bit EXDF bit
DSDPATH bit
D/A Conv.
Mode
#3 pin #4 pin #5 pin #16 pin #17 pin #19 pin
0
(default)
0
(default)
* PCM BICK SDATA LRCK
Not Use Not Use Not Use
1
1
0
*
*
1
0
(default)
1
*
DSD
Not Use Not Use Not Use
DCLK DSDL DSDR
DSD
EXDF
DCLK DSDL DSDR
Not Use Not Use Not Use
BCK DINL DINR
Not Use Not Use Not Use
(*: Do not care)
■
D/A Conversion Mode Switching Timing
and Figure 19 show switching timing of PCM/EXDF and DSD modes. To prevent noise caused
by excessive input, DSD signal should be input 4/fs after setting RSTN bit =
“0” until the device is completely reset internally when the conversion mode is changed to DSD mode from PCM/ESDF mode.
DSD signal should be stopped 4/fs after setting RSTN bit =
“0”until the device is completely reset internally when the conversion mode is changed to PCM/EXDE from DSD mode.
RSTN bit
4/fs
D/A Mode
PCM or EXDF Mode DSD Mode
0
D/A Data
PCM or EXDF Data DSD Data
Figure 18. D/A Mode Switching Timing (PCM or EXDF to DSD)
Rev. 0.1
- 35 -
2015/11
[AK4497]
RSTN bit
0
D/A Mode
DSD Mode
4/fs
PCM or EXDF Mode
D/A Data
DSD Data
PCM Data
Figure 19. D/A Mode Switching Timing (DSD to PCM or EXDF)
Figure 20 shows switching timing of PCM and EXDF modes. Set EXDF bit 4/fs after setting RSTN bit =
“0” until the device is completely reset internally when changing the conversion mode.
RSTN bit
4/fs
0
D/A Mode
PCM or EXDF Mode PCM or EXDF Mode
D/A Data
PCM or EXDF Data
PCM or EXDF Data
Figure 20. D/A Mode Switching Timing (PCM ⇔ EXDF)
Rev. 0.1
- 36 -
2015/11
[AK4497]
■
System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4497, are MCLK, BICK and LRCK. MCLK should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter, the delta-sigma modulator and SCF.
There are Manual Setting Mode, Auto Setting Mode and Fs Auto Detection mode for MCLK frequency setting. In manual setting mode, MCLK frequency is set automatically but the sampling speed (LRCK
control mode (PSN pin =
“H”), and it is set by DFS[2:0] bits in register control mode (PSN pin = “L”). In register control mode, the AK4497 is in manual setting mode when power-down is released (PDN pin =
“
”).
In auto setting mode
(ACKS pin = “H” or ACKS bit=“1”), sampling speed and MCLK frequency are
detected automatically ( Table 7 ,
Table 10 ) and then the initial master clock is set to the appropriate
In FS auto detect mode (AFSD bit=
“1”), sampling speed is automatically detected (
and the initial master clock is set to the appropriate frequency. In this mode, ACKS bit and DFS[2:0] bits settings are invalid. Fs auto detect mode is not supported by pin control mode.
The AK4497 is automatically placed in power-down state when MCLK is stopped for more than 1us during a normal operation (PDN pin =
“H”), and the analog output becomes Hi-z state. When MCLK is input again, the AK4497 exits power-down state and starts operation. The AK4497 is in power-down mode until MCLK BICK and LRCK are supplied and the analog output is floating state.
Table 5. System Clock Setting Mode @Register Control Mode
AFSD bit ACKS bit
0
0
1
0
1
-
Mode
Manual setting Mode
Auto setting Mode
FS Auto Detect Mode
(default)
Rev. 0.1
- 37 -
2015/11
[AK4497]
(1) Pin Control Mode
(PSN pin = “H”)
1-
1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally ( Table 6 ).
DFS1-0 bit is fixed to
“00”. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)(N/A: Not available)
LRCK fs 128fs 192fs 256fs
MCLK (MHz)
384fs 512fs 768fs 1152fs
BICK
64fs
32.0kHz
44.1kHz
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz
11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz
12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz
1-
2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically ( Table 7 ).
MCLK of corresponded frequency to each sampling speed mode should be input externally ( Table 8 ).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
256fs
128fs
64fs
32fs
1152fs
512fs/256fs 768fs/384fs
384fs
192fs
96fs
48fs
Sampling Speed
Normal (fs
32kHz)
Normal
Double
Quad
Oct
Hex
Table 8. System Clock Example (Auto Setting Mode @Pin Control Mode) (N/A: Not available)
LRCK fs 32fs 48fs 64fs 96fs 128fs
MCLK(MHz)
192fs 256fs
32.0kHz
44.1kHz
48.0kHz
N/A
N/A
N/A
88.2kHz
96.0kHz
N/A
N/A
176.4kHz N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A 22.5792 33.8688
192.0kHz N/A
384kHz N/A
N/A N/A
768kHz 24.576 36.864 N/A
N/A 24.5760 36.8640
N/A 24.576 36.864
N/A
N/A
N/A
N/A
N/A
8.1920 16.3840 24.5760
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688
24.5760 36.8640
N/A
N/A
N/A
N/A
384fs
12.2880
N/A
N/A
N/A
N/A
512fs
N/A
N/A
N/A
N/A
N/A
N/A
768fs
N/A
N/A
N/A
N/A
N/A
N/A
1024fs
32.7680
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz ( Table 9 ).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 9. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin MCLK DR,S/N
Quad
Quad
Oct
Hex
L
H
H
256fs/384fs/512fs/768fs
256fs/384fs
512fs/768fs
127dB
124dB
127dB
Rev. 0.1
- 38 -
2015/11
[AK4497]
(2) Register Control Mode
(PSN pin = “L”)
1-
1. Manual Setting Mode (AFSD bit=”0”, ACKS bit = “0”)
MCLK frequency corresponding to each sampling speed that should be provided externally ( Table 11 ).
The AK4497 is set to Manual Setting Mode at power-up
(PDN pin = “L” →“H”). When DFS2-0 bits are changed, the AK4497 should be reset by RSTN bit.
Table 10. Sampling Speed (Manual Setting Mode @Register Control Mode)
DFS2 DFS1 DFS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Quad Speed Mode
8kHz
54kHz
54kHz
108kHz
(default)
120kHz
216kHz
120kHz
216kHz
Oct Speed Mode 384kHz
Hex Speed Mode
Oct Speed Mode
Hex Speed Mode
768kHz
384kHz
768kHz
Table 11. System Clock Example (Manual Setting Mode @Register Control Mode)
LRCK
Fs 16fs 32fs
MCLK(MHz)
48fs 64fs 96fs 128fs
Sampling
Speed
32.0kHz
N/A
44.1kHz
N/A
48.0kHz
N/A
88.2kHz
N/A
96.0kHz
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
192.0kHz
N/A
384kHz
N/A
N/A N/A N/A N/A
12.288 18.432 24.576 36.864
768kHz 12.288 24.576 36.864 49.152 N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Table 12. System Clock Example (Manual Setting Mode @Register Control Mode)
LRCK fs 192fs 256fs 384fs
MCLK(MHz)
512fs 768fs 1024fs 1152fs
Sampling
Speed
32.0kHz
44.1kHz
48.0kHz
88.2kHz
N/A
N/A
N/A
N/A
8.1920 12.2880 16.3840
11.2896 16.9344 22.5792
12.2880 18.4320 24.5760
22.5792 33.8688 45.1584
96.0kHz
N/A 24.5760 36.8640 49.152
176.4kHz
33.8688 45.1584
192.0kHz
36.8640 49.152
N/A
N/A
N/A
N/A
384kHz
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
24.5760 32.7680 36.8640
33.8688
36.8640
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Rev. 0.1
- 39 -
2015/11
[AK4497]
1-2. Auto Setting Mode (
AFSD bit=
“0”,
ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically ( Table 13 ) and DFS[2:0] bits are
ignored. The MCLK frequency corresponding to each sampling speed should be provided externally
Table 13. Sampling Speed (Auto Setting Mode)
MCLK
1152fs
512fs/256fs 768fs/384fs
256fs 384fs
128fs
64fs
32fs
192fs
96fs
48fs
Sampling Speed
Normal (fs
32kHz)
Normal
Double
Quad
Oct
Hex
Table 14. System Clock Example (Auto Setting Mode)
LRCK fs 32fs 48fs
MCLK(MHz)
64fs 96fs 128fs
Sampling
Speed
32.0kHz
44.1kHz
48.0kHz
88.2kHz
N/A
N/A
N/A
N/A
96.0kHz N/A
176.4kHz N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
192.0kHz N/A
384kHz N/A
N/A
N/A
N/A
768kHz 24.576 36.864 N/A
N/A
24.576 36.864
N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Table 15. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz) fs 192fs 256fs 384fs 512fs 768fs 1152fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
N/A
N/A
N/A
N/A
8.1920 12.2880 16.3840 24.5760 36.8640
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688
96.0kHz
N/A 24.5760 36.8640
176.4kHz
33.8688 N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
192.0kHz
36.8640 N/A
384kHz N/A
N/A
768kHz
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Sampling
Speed
Normal
Double
Quad
Quad
Oct
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate from 8kHz to 96kHz ( Table 13 ).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 16. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS bit MCLK DR,S/N
0
1
1
256fs/384fs/512fs/768fs
256fs/384fs
512fs/768fs
127dB
124dB
127dB
Rev. 0.1
- 40 -
2015/11
[AK4497]
1-3. Sampling Frequency
(FS) Auto Detect Mode (AFSD bit=”1”)
and ACKS bit settings are invalid. The MCLK frequency corresponding to each sampling speed should
be provided externally ( Table 17 , Table 18 ).
Internal operation sequence in FS auto detect mode is shown in
Table 17. System Clock Example @PCM Mode
LRCK
Fs 16fs 32fs
MCLK(MHz)
48fs 64fs 96fs 128fs
Sampling
Speed
32.0kHz
44.1kHz
48.0kHz
N/A
N/A
N/A
88.2kHz
96.0kHz
N/A
N/A
176.4kHz
N/A
192.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
12.288 18.432 24.576 36.864
768kHz 12.288 24.576 36.864 49.152 N/A
N/A
N/A
N/A
N/A
N/A
22.5792
24.5760
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
LRCK
Table 18. System Clock Example @PCM Mode
MCLK(MHz)
Sampling
Speed fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
N/A
N/A
N/A
N/A
8.1920 12.2880 16.3840 24.5760 32.768 36.8640
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688 45.1584
96.0kHz
N/A 24.5760 36.8640 49.152
176.4kHz
33.8688 45.1584 N/A N/A
192.0kHz
36.8640 49.152
384kHz
N/A N/A
768kHz
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Normal
Double
Quad
Quad
Oct
Hex
Rev. 0.1
- 41 -
2015/11
■
Power ON/OFF Sequence in FS Auto Detect Mode (LDOE pin =
“H”)
Power
PDN pin
DVDD pin
Internal PDN
Internal
State
(1)
(2)
Normal Operation (Register Write and DAC Operation are Available)
AFSD bit
AFSD bit =
“0”
AFSD bit =
“0”
AFSD bit =
“1”
(3)
Power up
Internal OSC
Clock In
LRCK
Don
’t care
Internal FS Auto Detect Circuit
(4)
FS Auto Detect mode Enable
[AK4497]
Note:
(1) Power-up AVDD and TVDD and the PDN pin should be
“L” for more than 150ns.
(2) The internal LOD is powered up upon power-up of the AK4497 if the LDOE pin=
“H”. The internal circuit will be powered up in 2ms (max.) after the shutdown switch is ON following internal oscillator count up. When LDOE pin =
“L”, shutdown switch is ON after the AK4497 is powered up. The internal circuit will be powered up in 1us (max.)
(3) The internal oscillator starts operation by setting AFSD bit=
“1”. It takes 10us (max.) until the internal oscillator is stabilized.
(4) FS auto detect mode starts in 8/fs ~ 9/fs after setting AFSD bit=
“1”.
(5) FS auto detect mode ends by setting AFSD bit =
“0” and the internal oscillator will stop operation.
Figure 21. Power-down/up Sequence in FS AutoDetect Mode
Rev. 0.1
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2015/11
[AK4497]
[1] DSD Mode
The AK4497 has a DSD playback function. The external clocks that are required in DSD mode are MCLK and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit ( Table 19 ).
The AK4497 is automatically placed in power-down state when MCLK is stopped during a normal operation (PDN pin =
“H”), and the analog output becomes Hi-z state. When the reset is released (PDN pin =
“L” → “H”), the AK4497 is in power-down state until MCLK and DCLK are input.
Table 19. System Clock (DSD Mode, fs=32kHz, 44.1kHz, 48kHz)
DCKS bit MCLK Frequency DCLK Frequency
0
1
512fs
768fs
64fs/128fs/256fs (default)
64fs/128fs/256fs
The AK4497 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL[1:0] bits ( Table 20 ).
Table 20. DSD data stream select
DSDSEL1 DSDSEL0 fs=32kHz
DSD data stream fs=44.1kHz fs=48kHz
0
0
1
1
0
1
0
1
2.048MHz
4.096MHz
8.192MHz
16.284MHz
2.8224MHz
5.6448MHz
11.2896MHz
22.5792MHz
3.072MHz
6.144MHz
12.288MHz
24.576MHz
(default)
The AK4497 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit ( Table 21 ). When setting DSDD bit =
“1”, the output volume control and zero detect functions are not available.
Table 21. DSD Play Back Path Select
DSDD
0
1
Mode
Normal Path
Volume Bypass
(default)
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2015/11
[AK4497]
[2] External Digital Filter Mode (EXDF mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 22 . ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not detected for more than 1us during a normal operation (PDN pin =
“H”), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4497 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin =
“L” → “H”), the AK4497 is in power-down state until MCLK, BCK and WCK are input.
Table 22. System Clock Example (EXDF mode)
Sampling
Speed[kHz]
MCLK&BCK [MHz]
128fs 192fs 256fs 384fs
WCK
ECS
44.1(30~48)
44.1(30~48)
96(54~96)
96(54~96)
N/A
N/A
N/A
12.28
8
32
N/A
N/A
18.432
48
N/A
32
24.576
32
N/A
N/A
N/A 11.2896
16.9344
48
36.864
48
36.864
96
512fs 768fs
22.5792 33.8688
16fs
32 48 DW
N/A
33.8688
8fs
N/A
N/A
96
N/A
N/A
DW
8fs
DW
4fs
DW
0
1
0
1
(default)
24.576
36.864
192(108~192)
192(108~192)
32
N/A
48
36.864
96
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4fs
DW
2fs
DW
0
1
Rev. 0.1
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2015/11
[AK4497]
■
Audio Interface Format
[1] PCM mode
(i) Input Data Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and
BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs.
Normal Mode (TDM[1:0] bits =
“00” or TDM1-0 pins = “LL”)
2ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in
of BICK. Mode 6 can be used for 24-bit, 20-bit and 16-bit MSB justified formats by zeroing the unused
LSBs.
TDM128 Mode (TDM[1:0] bits =
“01” or TDM1-0 pins = “LH”)
4ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM256 Mode (TDM[1:0] bits
=“10” or TDM1-0 pins =“HL”)
8ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM512 Mode (TDM[1:0] bits =
“11” or TDM1-0 pins = “HH”)
16ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
Rev. 0.1
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2015/11
[AK4497]
Mode
Normal
TDM128
0
1
2
3
4
5
6
7
8
9
10
Table 23. Audio Interface Format
TDM1 TDM0 DIF2 DIF1 DIF0 SDATA Format
0 0
0
0
0
0
0
0
1
1
0 16-bit LSB justified
1
0 24-bit MSB justified
1
20-bit LSB justified
LRCK BICK
H/L
32fs
H/L
40fs
16-bit I
2
S Compatible L/H 32fs
24-bit I
2
S Compatible
H/L
L/H
48fs
48fs
1
1
1
1
0
0
1
1
0 24-bit LSB justified H/L
48fs
1
0
32-bit LSB justified
32-bit MSB justified
H/L
64fs
H/L
64fs
1 32-bit I
2
S Compatible L/H
64fs
0 0 0 (16-bit LSB justified) H/L 128fs
0 1
0
0
0
1
0
1
1
0
1 (20-bit LSB justified) H/L 128fs
0 24-bit MSB justified H/L 128fs
1 24-bit I
2
S Compatible L/H 128fs
0 24-bit LSB justified H/L 128fs
11
12
1
1
0
1
1 32-bit LSB justified H/L 128fs
0 32-bit MSB justified H/L 128fs
1 32-bit I
2
S Compatible L/H 128fs
TDM256
TDM512
13
14
15
16
17
18
19
20
21
22
23
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0 (16-bit LSB justified) H/L 256fs
1
1
1
0 24-bit MSB justified
1 24-bit I
2
1
(20-bit LSB justified)
0 24-bit MSB justified
1 24-bit I
2
1 32-bit I
2
S Compatible
0 24-bit LSB justified
32-bit LSB justified
0 32-bit MSB justified
S Compatible
(20-bit LSB justified)
S Compatible
0 24-bit LSB justified
32-bit LSB justified
H/L
L/H
H/L
L/H
256fs
H/L 256fs
L/H
H/L
H/L
H/L 256fs
0 (16-bit LSB justified) H/L 512fs
H/L 512fs
H/L
H/L
256fs
256fs
256fs
256fs
512fs
512fs
512fs
512fs
24
25
1
1
1
1
0 32-bit MSB justified
1 32-bit I
2
S Compatible
H/L 512fs
L/H 512fs
Note 40. BICK more than setting bit must be input to each channel. In the LRCK column,
“H/L” indicates that L channel data can be input when LRCK is
“H” and R channel data can be input when
LRCK is
“L”. “L/H” indicates L channel data can be input when LRCK is “L” and R channel data can be input when LRCK is
“H”.
Rev. 0.1
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2015/11
[AK4497]
LRCK
BICK
(32fs)
SDATA
Mode 0
BICK
(64fs)
SDATA
Mode 0
0 1
15 14
0 1
Don
’t care
15:MSB, 0:LSB
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17 31 0 1
15 14 0 Don
’t care
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17 31 0 1
Lch Data
Figure 22. Mode 0 Timing
Rch Data
15 14 0
LRCK
BICK
(64fs)
SDATA
Mode 1
0 1
SDATA
Mode 4
8 9 10 11 12 31 0 1 8 9 10 11 12
Don
’t care
19:MSB, 0:LSB
19 0 Don
’t care
19
Don
’t care
23:MSB, 0:LSB
23 22 21 20 19 0 Don
’t care
23 22 21 20 19
Lch Data
Figure 23. Mode 1, 4 Timing
Rch Data
31 0 1
0
0
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK
(64fs)
SDATA
23 22 23 22
23:MSB, 0:LSB
1 0 Don
’t care
23 22 1 0 Don
’t care
Lch Data
Figure 24. Mode 2 Timing
Rch Data
Rev. 0.1
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2015/11
[AK4497]
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK
(64fs)
SDATA
23 22
23:MSB, 0:LSB
1 0
Don
’t care
23 22
Lch Data
Figure 25. Mode 3 Timing
LRCK
BICK(128fs)
0 1 2
SDATA
0 1 2
BICK(64fs)
SDATA
31 30
20 21 22
12 13 14
20 19 18
32 33
31
23 24
1 0
31 0 1 2
9 8
63 0 1 2
1 0 31 30
1 0 Don
’t care
Rch Data
20 21 22
12 13 14
20 19 18
32 33
9 8
23
63 0 1
31
23 24
1 0
31 0 1
1 0 31
Lch Data Rch Data
31: MSB, 0:LSB
Figure 26. Mode 5 Timing
LRCK
BICK(128fs)
0 1 2
SDATA
20 21 22 32 33
31 30
0 1 2
12 11 10
12 13 14
0
23 24
63 0 1 2 20 21 22 32 33
31 30
31 0 1 2
12 11 10
12 13 14
0
23 24
BICK(64fs)
SDATA
31 30 20 19 18 9 8 1 0 31 30 20 19 18 9 8
63 0 1
31
31 0 1
1 0 31
31: MSB, 0:LSB
Lch Data
Figure 27. Mode 6 Timing
Rch Data
Rev. 0.1
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2015/11
LRCK
BICK(128fs)
0 1 2
SDATA
20 21 22 33 34
31
0 1 2
13 12 11
12 13 14
0
24 25
BICK(64fs)
SDATA
63 0 1 2 20 21 22 33 34
31
31 0 1 2
13 12 11
12 13 14
0
24 25
0 31 21 20 19 9 8
31: MSB, 0:LSB
Lch Data
2 1 0 31
Figure 28. Mode 7 Timing
128 BICK
21 20 19 9 8
Rch Data
LRCK
[AK4497]
63 0 1
31 0 1
2 1 0
BICK(128fs)
SDATA
Mode8
23
22
SDATA
Mode11,12
31 30
0 23 22
0
31 30
0
0
23 22
31 30
L1
32 BICK
R1
32 BICK 32 BICK 32 BICK
LRCK
BICK(128fs)
SDATA
Mode9
SDATA
Mode13
23 22
31 30
L1
32 BICK
0
Figure 29. Mode 8/11/12 Timing
128 BICK
23 22
0
31 30
R1
32 BICK
0
0
32 BICK 32 BICK
23
31 30
Figure 30. Mode 9/13 Timing
Rev. 0.1
- 49 -
2015/11
[AK4497]
LRCK
BICK(128fs)
SDATA
128 BICK
23
22
L1
32 BICK
0
23
22 0
R1
32 BICK 32 BICK
Figure 31. Mode 10 Timing
32 BICK
23
LRCK
BICK (256fs)
SDATA
Mode14
SDATA
Mode17,18
23 22 0 23 22 0
256 BICK
23 22
LRCK
BICK (256fs)
SDATA
Mode15
SDATA
Mode19
31 30
L1
32 BICK
0 31 30 0
R1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 32. Mode 14/17/18 Timing
31 30
256 BICK
23 0 23 0 23
31 30
L1
32 BICK
0 31 30 0
R1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 33. Mode 15/19 Timing
256 BICK
31
LRCK
BICK(256fs)
SDATA
23 22
L1
32 BICK
0 23 22 0
R1
32 BICK 32 BICK 32 BICK 32 BICK
Figure 34. Mode 16 Timing
32 BICK
32 BICK 32 BICK
23
Rev. 0.1
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2015/11
[AK4497]
LRCK
512BICK
BICK(512fs)
SDATA
Mode8
SDATA
Mode11,12
23 22 0 23 22
2
0 23
31 22 0 31 22 0
L1 R1
32 BICK
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
31
Figure 35. Mode 20/23/24 Timing
512BICK
LRCK
BICK(512fs)
SDATA
Mode21
SDATA
Mode25
23 22 0 23 22
2
0 23
31 22 0 31 22 0
L1 R1
32 BICK
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
31
Figure 36. Mode 21/25 Timing
512BICK
LRCK
BICK(512fs)
SDATA
Mode22
23 22 0 23 22 0
L1
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
23
Figure 37. Mode 22 Timing
Rev. 0.1
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2015/11
[AK4497]
(ii) Data Slot Selection Function
can be selected by SDS[2:0] bits as shown in Table 24 .
LRCK
SDATA L1 R1
LRCK
SDATA L1
Figure 38. Data Slot in Normal Mode
128 BICK
R1 L2 R2
Figure 39. Data Slot in TDM128 Mode
LRCK
SDATA
256 BICK
L1 R1 L2 R2 L3 R3 L4 R4
Figure 40. Data Slot in TDM256 Mode
LRCK
SDATA
512 BICK
L1 R1 L2 R2
L3 R3 L4 R4 L5
R5 L6 R6 L7 R7 L8 R8
Figure 41. Data Slot in TDM512 Mode
Rev. 0.1
- 52 -
2015/11
Normal
TDM128
TDM256
TDM512
1
1
(*: Do not care)
0
1
1
0
0
0
*
*
*
*
SDS2 SDS1
Table 24. Data Select
SDS0
Lch
DAC
Rch
* * * L1 R1
*
*
*
*
0
1
L1
L2
R1
R2
1
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
L1
L2
L3
L4
L5
L6
L7
L8
L1
L2
L3
L4
R1
R2
R3
R4
R5
R6
R7
R8
R1
R2
R3
R4
[AK4497]
Rev. 0.1
- 53 -
2015/11
[AK4497]
(iii) Daisy Chain
The AK4497 supports cascading of multiple devices by daisy chain connection in TDM512/256 mode
(TDM[1:0] bits =
“10”, “11”). DCHAIN bit or DCHAIN pin controls Daisy Chain mode (
bits setting will be invalid in Daisy Chain mode.
Table 25 Daisy Chain Control
DCHAIN bit
DCHAIN pin
Mode TDMO
0
1
Normal
Daisy Chain
“L”
Data output
(default)
(1) TDM512 Mode
Figure 42 shows daisy chain connection in TDM512 mode (TDM[1:0] bits =
“11”). 16ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA pin of the first AK4497.
shows data input/output example of daisy chain in TDM512 mode. The second AK4497 receives L8 and R8 data as DAC inputs and outputs the data by shifting 2ch from the TDMO pin. The first
AK4497 receives L7 and R7 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497
’s must be the same.
TDMO
First
AK4497
SDATA
TDMO
Second
AK4497
SDATA
DSP
Figure 42. Daisy Chain (TDM512 Mode)
LRCK
SDATA
TDMO
512 BICK
L1 R1 L2 R2 L3 R3 L4 R4
L5
R5 L6 R6 L7 R7 L8 R8
Second AK4497
L8 R8 L1
R1 L2
R2 L3 R3 L4 R4 L5 R5 L6 R6
L7 R7
First AK4497
Figure 43. Daisy Chain (TDM512 Mode)
Rev. 0.1
- 54 -
2015/11
[AK4497]
(2) TDM256 Mode
Figure 42 shows daisy chain connection in TDM256 mode (TDM[1:0] bits =
“10”). 8ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA pin of the first AK4497.
shows data input/output example of daisy chain in TDM256 mode. The second AK4497 receives L4 and R4 data as DAC inputs and outputs the data from the TDMO pin by shifting 2ch. The first
AK4497 receives L3 and R3 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497
’s must be the same.
256 BICK
LRCK
SDATA L1 R1 L2 R2 L3 R3 L4 R4
Second AK4497
TDMO
L4 R4 L1 R1 L2 R2 L3 R3
First AK4497
Figure 44. Daisy Chain (TDM256 Mode)
[2] DSD Mode
In DSD mode, L channel data and R channel data must be input to the DSDL pin and the DSDR pin, respectively by synchronizing to DCLK. Input pins can be selected by DSDPATH bit. When DSDPATH bit
=
“0”, the TDM0 pin, the DEM pin and the GAIN pin become DCLK, DSDL and DSDR input pins, respectively. When DSDPATH bit =
“1”, the BICK pin, the SDATA pin and the LRCK pin become DCLK,
DSDL and DSDR input pins, respectively.
In case of DSD mode, the settings of DIF2-0 pins and DIF[2:0] bits are ignored. The frequency of DCLK is selected between 64fs, 128fs and 256fs by DSDSEL[1:0] bits. Phase modulation function is not available in 512fs mode (DSDSEL[1:0] bits =
“11”).
DCLK
(64fs,128fs,256fs,512fs)
DCKB bit=
”1”
DCLK
(64fs,128fs,256fs,512fs)
DCKB bit=
”0”
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D1
D2
D2
D2
D3
D3
Figure 45. DSD Mode Timing
Rev. 0.1
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2015/11
[AK4497]
[3] External Digital Filter Mode (EXDF mode)
The audio data is input by BCK and WCK from the DINL and DINR pins. Three formats are available
( Table 26 ) by DIF2-0 bits setting. The data is latched on the rising edge of BCK. The BCK and MCLK
clocks must not burst.
Table 26. Audio Interface Format (EXDF mode) (N/A: Not available)
Mode DIF2 DIF1 DIF0 Input Format
3
4
5
6
7
0
1
2
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
16-bit LSB justified
N/A
16-bit LSB justified
N/A
24-bit LSB justified
32-bit LSB justified
24-bit LSB justified (default)
32-bit LSB justified
1/16fs or 1/8fs or 1/4fs or 1/2fs
WCK
0 1
BCK
DINL or
DINR
31 30
0 1
BCK
DINL or
DINR
Don
’t care
0 1
BCK
DINL or
DINR
Don
’t care
8 9 10 11
24
23 22 21 20 17 16 15 14
5 6 7 8
Don
’t care
13 14 15 16
Don
’t care
31
16 17
47 48 49
Don
’t care
23 24 25
6 5 4 3 2 1 0
65 92 93 94
95 0 1
31
26 27 28 29 30 31 0 1
Figure 46. EXDF Mode Timing
3
2 1
0 Don
’t care
44 45 46
47 0 1
3
2 1
0
Don
’t care
Rev. 0.1
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2015/11
[AK4497]
■
Digital Filter
Six types of digital filter in PCM mode and two types of digital filter in DSD mode are available in the
AK4497 for sound color selection of music playback.
In PCM mode, digital filter can be selected by the SD, SLOW and SSLOW pins if the AK4497 is in pin control mode, and digital filter can be selected by SD, SLOW and SSLOW bits in register control mode
In register control mode, programmable digital filter can be available by setting SSLOW bit =
“1” and SD bit =
“1”. In this case, Low dispersion short delay filter is available if SLOW bit = “0” and the coefficient can be changed if SLOW bit =
“1”.
Table 27. Digital Filter Setting
SSLOW
0
0
0
0
1
1
SD
0
0
1
1
0
0
SLOW
0
1
0
1
0
1
Mode
Sharp roll-off filter
Slow roll-off filter
Short delay sharp roll off filter
Short delay slow roll off filter
Super Slow roll Off filter
Super Slow roll Off filter
(default)
1 1 X
Low dispersion Shot delay filter /
Programmable FIR filter
Note 41. SSLOW=1, SD=1, SLOW=0: Low dispersion Short delay filter
SSLOW=1, SD=1, SLOW=1: Programmable FIR filter (only for register control mode)
In DSD mode, the cutoff frequency of digital filter can be switched by DSDF bit.
shows the cutoff frequency of fs = 44.1kHz. The cutoff frequency tracks the sampling frequency (fs). Do not set GS[2:0] bits to
“100” when DSDD bit = “0” and DSDF bit = “1”. Otherwise a pop noise may occur.
Table 28. DSD Filter Select
Cut Off Frequency @fs=44.1kHz
DSDF bit
0
1
DSD64fs DSD128fs DSD256fs DSD512fs
39kHz
76kHz
78kHz
152kHz
156kHz
304kHz
312kHz
608kHz
(default)
Rev. 0.1
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2015/11
[AK4497]
■
De-emphasis Filter (PCM)
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled by DEM1-0 pins or DEM1-0 bits. When DSD mode or EXDF mode, DEM1-0 bits are ignored. The setting value is held even if PCM, DSD and EXDF mode is switched.
Table 29. De-emphasis Control
DEM1 DEM0 Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF (default)
48kHz
32kHz
■
Output Volume (PCM, DSD, EXDF)
The AK4497 includes channel independent digital output volumes (ATTL/R) with 256 levels at 0.5dB step including MUTE. When changing output levels, it is executed in soft transition thus no switching noise occurs during these transitions. It can attenuate the input data from 0dB to -127dB and mute when assuming the output signal level is 0dB when ATTL/R[7:0] bits = FFH.
Table 30. Attenuation level of Digital Attenuator
ATTL/R[7:0]bits
(register 03-04H)
Attenuation Level
FFH
FEH
FDH
:
:
02H
01H
00H
+0dB
-0.5dB
-1.0dB
:
:
-126.5dB
-127.0dB
MUTE (-
∞)
(default)
levels between Mode0-3, it is executed in soft transition thus no switching noise occurs during these transitions. Register setting values will be kept even switching the PCM and DSD modes.
Table 31. Transition Time between Set Values of ATT[7:0] bits
Mode ATS1 ATS0
EXDF bit=”0”,
DP bit=”0”
ATT speed
EXDF bit=”1”
DP bit=”0”
DP bi t=”1”
0
1
2
3
0
0
1
1
0
1
0
1
4080/fs
2040/fs
510/fs
255/fs
4080*WCK Cycle
2040*WCK Cycle
510*WCK Cycle
255*WCK Cycle
4080/(2*fs)
2040/(2*fs)
510/(2*fs)
255/(2*fs)
(default)
It takes 4080/fs (92.5ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE) in Mode 0. The attenuation level is initialized to FFH (0dB) by setting the PDN pin =
“L”.
If the volume is changed during reset period, the output volume will become a setting value after releasing the reset. It will change to a setting value immediately if the volume is changed within 5/fs after releasing reset.
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Gain Adjustment Function (PCM, DSD, EXDF)
The AK4497 has the gain adjustment function. The analog output amplitude can be adjusted by GC[2:0] bits or the GAIN pin.
Table 32. Output Level between Set Values of GC[2:0] bits
GC[2] GC[1] GC[0]
AOUTLP/LN/RP/RN Output Level
PCM
DSD:
Normal Path
DSD:
Volume
Bypass
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.8Vpp
2.8Vpp
2.5Vpp
2.5Vpp
3.75Vpp
3.75Vpp
2.5Vpp
2.5Vpp
2.8Vpp
2.5Vpp
2.5Vpp
2.5Vpp
3.75Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
(default)
Table 33. Output Level between Set Values of GAIN pin
GAIN
AOUTLP/LN/RP/RN
Output Level
0
1
2.8Vpp
3.75Vpp
Note 42. DSDF bit must be set to
“0” if GC[2:0] bits are set to “100” when using DSD Normal Path. Click noise may occur if DSDF bit is set to
“0”.
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Zero Detection (PCM, DSD, EXDF)
The AK4497 has a channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, the DZF pin of each channel outputs zero detection flag independently. The DZFL/R pin outputs zero detection flag if the input data is continuously zeros for
16384 LRCK cycles in DSD 512fs mode (DP bit =
“1” and DSDSEL[1:0] bits = “11”). Polarity of the detection flag of the DZFL/R pin can be selected by DZFB bit. The DZFL/R pin goes
“H” for zero detection when DZFB bit =
“0”, the DZFL/R pin goes “L” when DZFB bit = “1”.
When DZFB bit =
“0”, the DZFL/R pin immediately returns to “L” if the input data of each channel is not zero after going to
“H”. If the RSTN bit is “0”, the DZF pins of both L and R channels go to “H”. The DZFL/R pin returns to “L” in 4 ~ 5/fs after the input data of each channel becomes “1” when RSTN bit is set to “1”.
If
DZFM bit is set to “1” while DZFB bit = “0”, the DZF pins of both L and R channels go to “H” only when the input data for both channels are continuously zeros for 8192 LRCK cycles (16384 LRCK cycles in
DSD 512fs mode). The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always “L”. The zero detect function is also disabled when Volume Bypass is selected in DSD mode (refer to p42).
Table 34. Zero Detect Select.
DZFE DZFB RSTN Data DZF-pin
0
1
0
1
0
1
-
-
0
1
0
1
-
-
- not zero zero detect
- not zero zero detect
L
H
H
L
H
L
H
L
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L/R Channel Output Signal Select, Phase Inversion Function (PCM, DSD, EXDF)
In register control mode, input and output combination of the AK4497 can be changed by MONO bit and
SELLR bit. In addition, the output signal phase can be inverted by INVL bit and INVR bit. These functions are available on all audio formats. In pin control mode, the phase of R channel output can be inverted by setting the INVR pin.
Table 35. Output Select (Register Control)
MONO bit SELLR bit INVL bit INVR bit Lch Out Rch Out
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Lch In
Lch In
Rch In
Rch In Invert
Lch In Invert Rch In
Lch In Invert Rch In Invert
Rch In
Rch In
Lch In
Lch In Invert
Rch In Invert Lch In
Rch In Invert Lch In Invert
Lch In
Lch In
Lch In
Lch In Invert
Lch In Invert Lch In
Lch In Invert Lch In Invert
Rch In
Rch In
Rch In
Rch In Invert
Rch In Invert Rch In
Rch In Invert Rch In Invert
Table 36. Output Select (Pin Control)
INVR pin Lch Out Rch Out
0
1
Lch In Rch In
Lch In Rch In Invert
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Sound Quality (PCM, DSD, EXDF)
Sound quality of the AK4497 can be selected by SC[2:0] bits.
Table 37. Sound Quality Select Mode
SC1 SC0 Sound
0
0
1
1
0
1
0
1
Sound Setting 1
Sound Setting 2
Sound Setting 3
Sound Setting 2
SC2
0
1
Table 38. Sound Quality Select Mode
Sound
Sound Setting 4
Sound Setting 5
(default)
(default)
[AK4497]
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DSD Signal Full Scale (FS) Detection
The AK4497 has independent full scale detection function for each channel for DSD mode.
The AK4497 detects full scale signal when the DSDL/R input data is continuously
“0” (-FS) or “1” (+FS) for
2048 cycles and the detection flag for corresponding channel (DML or DMR bit) becomes
“1”. DML and
DMR bits can be read out at the register address 06H.
When the AK4497 detects full scale signal while DDM bit =
“1”, the analog output is muted in ATT transition period set by ATS[2:0] bits. This transition is executed by soft transition when DSDD bit =
“0”.
The analog output is muted immediately when DSDD bit =
“1”. These settings (ATS[2:0] bits and DSDD bits) are also valid when the AK4497 returns to normal status from full scale detection status.
The recovery timing from full scale detection status is controlled by DMC bit when DDM bit =
“1”. When
DMC bit =
“0”, the AK4497 is automatically recovered and transitions to normal operation by a normal signal input. When DMC bit =
“1”, the AK4497 transitions to normal operation by setting DMRE bit = “1” while normal signal is input. DMRE bit automatically returns to
“0” when the transition is finished. When
DDM bit =
“1”, full scale signal can be detected but the AK4497 does not change to mute status. RSTN bit must be set to
“0” when changing DDM bit setting.
Table 39. DSD Mode and Device Status after Full-Scale Detection (DDM bit=
“1”)
DSDD Mode Full Scale Detection Status Analog Output
0
1
Normal Path
Volume Bypass
DSD Mute
Digital Reset
VCML/R
VCM/L/R
(default)
DSD Data
DSD Data DSD Data (FS or -FS )
DSD Data
DSD Error
(DML or DMRbit)
2048fs
ATT Transition Period
ATT Transition Period
AOUT
(DSDD bit=
“0”)
AOUT
(DSDD bit=
“1”)
Figure 47. Analog Output Waveform in DSD FS Detection (DMC bit=
“0”)
DSD Data
DSD Error
(DML or DMRbit)
DSD Data
2048fs
DSD Data (FS or -FS ) DSD Data
DMRE bit
ATT Transition Period
AOUT
(DSDD bit=
“0”)
ATT Transition Period
Rev. 0.1
AOUT
(DSDD bit=
“1”)
Figure 48. Analog Output Waveform in DSD FS Detection (DMC bit=
“1”)
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Soft Mute Operation (PCM, DSD, EXDF)
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to
“1”, the output signal is attenuated by
during ATT_DATA
ATT transition time from the current ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA
ATT transition time. If the soft mute is cancelled before attenuating
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1) (1)
ATT_Level
Attenuation
(3)
-
(2) GD (2) GD
AOUTL/R
(4)
8192/fs
DZFL/R pin
Notes:
(1) ATT_DATA
ATT transition time. For example, this time is 4080LRCK cycles (1020/fs) at
ATT_DATA=255 in PCM Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating
after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles (16384 LRCK cycles in DSD 512fs mode), the DZF pin for each channel goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.
Figure 49. Soft Mute Function
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LDO
When TVDD = 3.0 ~3.6V, the power for digital core circuit (DVDD) is supplied by the internal LDO by setting the LDOE pin to
“H”.
Table 40 shows the DVDD pin statuses with the PDN and LDOE pins setting.
The internal LDO is powered up by setting the PDN pin from
“L” to “H” (power-down release) and it starts supping 1.8V DVDD. It takes 0.1ms (max.) to power-up the internal LDO.
Table 40. LDO Select Mode
PDN LDOE TVDD DVDD
L L
1.7~3.6V
Hi-z
L H 3.0~3.6V 500ohm Pull Down
H
H
L
H
1.7~3.6V LDO OFF: Supply 1.7 ~ 1.98V to the DVDD pin externally
3.0~3.6V LDO ON: LDO outputs 1.8V.
The AK4497 has error detect function as shown in Table 41 for LDO operation (LDOE pin =
“H”). The internal LDO will be powered down and stop supplying the power to the digital core when an error is detected. In this case, the analog signal output becomes Hi-z state. The AK4497 must be reset by setting the PDN pin =
“L” → “H” to recover from the error detection status.
Table 41. Error Detection
No Error Error Detection Condition
1 Internal Reference Voltage Error Internal reference voltage does not rise.
2 LDO Over Voltage Detection
3 LDO Over Current Detection
LDO voltage exceeds 2.2V.
LDO current is 40mA or less, or 110mA or more.
■
Shutdown Switch
A shutdown switch is placed between the DVSS pin and VSS for the digital core to prevent SIDD leak of
DVDD digital power supply. The on-resistance is maximum 1
Ω and the DVDD leak current will be 2uA at the maximum.
When using LDO (LDOE pin =
“H”), the shutdown switch is ON after counting by internal oscillator following a power-down release (PDN pin
“L” → “H”). It takes 2ms (max.) for the shutdown switch power-up.
When not using LDO (LDOE pin =
“L”), the shutdown switch is ON immediately after a power-down release (PDN pin
“L” → “H”). It takes 1us (max.) for the shutdown switch power-up.
■
Over Current Protection for Analog Output Pins
The AK4497 has channel independent over current detection function for analog output pins
(AOUTLP/LN and AOUTRP/RN pins). This function limits the current not to exceed 120mA when an excessive current over 120mA (min) is detected. It is valid when the AK4497 is in power-on state.
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Power Up/Down Function
The AK4497 is powered down by setting the PDN pin to
“L”. In power-down state, all circuits stop operation and initialized, and the analog output becomes floating (Hi-z) state.
The PDN pin must held “L” for more than 150ns for a certain reset. There is a possibility of malfunctions with the “L” pulse less than
150ns. Power-down is released by setting the PDN pin to
“H” from “L”. In this time IREF and LDO (if
LDOE pin =
“H”) are powered up and the analog output becomes floating (Hi-z) state.
(a) Pin Control Mode (PSN pin =
“H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin =
“H”. The analog circuit starts operation just after supplying all necessary clocks (MCLK, LRCK and BICK) and the
power down/up when using the internal LDO (LDOE pin
“H”). When power up the AK4497 with the LDOE pin =
“H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
（VDDL/R,VREFHL/R）
PDN pin
(1)
DVDD pin
Internal PDN
Internal
State
DAC In
(Digital)
(2)
Normal Operation (DAC Input Available)
Reset
“0”data
GD
(3)
“0”data
GD
(5) DAC Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don
’t care
External
Mute
(5)
(6)
Don
’t care
(4)
Mute ON
Mute ON
Figure 50. Power-down/up Sequence Example (Pin Control Mode, LDOE pin=
“H”)
Notes:
(1) The PDN pin must be held
“L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin =
“H” when the LDOE pin= “H”. The internal circuit will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance. The timing example when not using LDO (LODE pin =
pin=
“L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power supplies should be powered up at the same time, otherwise power up the 3.3V power supplies
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[AK4497]
(AVDD, TVDD) first, 1.8V power supply (DVDD) next and 5V power supplies (VDDL/R,
VREFHL/R) last.
Power
(TVDD,AVDD)
Power
（DVDD）
Power
（VDDL/R,VREFHL/R）
PDN pin
Internal PDN
Internal
State
DAC In
(Digital)
(1)
(2)
Normal Operation (DAC Input Available) Reset
“0”data
GD
(3)
“0”data
GD
(5) DAC Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don
’t care
External
Mute
(5)
(6)
Don
’t care
(4)
Mute ON
Mute ON
Figure 51. Power-down/up Sequence Example (Pin Control Mode, LDOE pin=
“L”)
Notes:
(1) The PDN pin must be held
“L” for more than 150ns after supplying AVDD, TVDD, DVDD and
VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin =
“H” when the LDOE pin= “L”. The internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal.
This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
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[AK4497]
(b) Register Control Mode (PSN pin=
“L”)
A register access becomes available after the PDN pin =
“H”. The analog circuit starts operation by supplying necessary clocks (MCLK, LRCK and BICK for PCM mode, MCLK and DCLK for DSD mode,
MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. The analog output pins output analog common voltages (VCML, VCMR) in this time. Then the AK4497 transitions to normal operation by setting RSTN bit =
“1”. When power up the AK4497 with the LDOE pin =
“H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of
5V power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
（VDDL/R,VREFHL/R）
PDN pin
(1)
DVDD pin
Internal PDN
(2)
RSTN bit
(8)
Internal State
(Resister
(Clock devider)
Power Off
Normal Operation Power Off
(9)
(9)
Internal State
(Digital Core)
DAC In
(Digital)
Power Off Normal Operation
“0”data
GD
(3)
“0”data
GD
Power Off
(5)
DAC Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don
’t care
(5)
Don
’t care
(4)
DZFL/R
(7)
Figure 52. Power-down/up Sequence Example (Resister Control Mode, LDOE pin=
“H”)
Notes:
(1) The PDN pin must be held
“L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin =
“H” when the LDOE pin= “H”. The internal circuit will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
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[AK4497]
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to
“0” and it takes
2~3/fs when changing RSTN bit to
“1”. The system timing example of power up/down when not using LDO (LODE pin =
Figure 53 . When the LDOE pin=
“L”, 1.8V (DVDD), 3.3V
(AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power supplies should be powered up at the same time, otherwise power up the 3.3V power supplies (AVDD, TVDD) first, 1.8V power supply (DVDD) next and 5V power supplies (VDDL/R, VREFHL/R) last.
Power
(TVDD,AVDD)
Power
（DVDD）
Power
(VDDL/R,VREFHL/R)
PDN pin
Internal PDN
(1)
RSTN bit
(8)
Internal State
(Resister
(Clock devider)
Power Off
Normal Operation
Power Off
(9) (9)
Internal State
(Digital Core)
DAC In
(Digital)
Power Off
Normal Operation
“0”data
GD
“0”data
GD
Power Off
(5)
DAC Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don
’t care
(5)
Don
’t care
(4)
DZFL/R
(7)
Figure 53. Power-down/up Sequence Example (Resister Control Mode, LDOE pin=
“H”)
Notes:
(1) The PDN pin must be held
“L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin =
“H” when the LDOE pin= “L”. The internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN s ignal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to
“0” and it takes
2~3/fs when changing RSTN bit to
“1”.
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Power-OFF/Reset Function
Power-off and Reset function of the AK4497 are controlled by PW bit, RSTN bit and MCLK ( Table 42 ).
Table 42. Power Off, Reset Function
Mode
PDN
Pin
MCLK
Supply
PW bit
RSTN bit
DIGITAL
Block
ANALOG
Block
LDO
Register
Analog Output
Power Down
L
－ － －
OFF OFF OFF Hi-Z
MCLK Stop
H
Power OFF
H
Reset H
Normal Operation H
No
Yes
Yes
Yes
－
0
1
1
－
－
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
Hi-Z
Hi-Z
VCML/R
Signal Output
(1) Power ON/OFF by MCLK Clock
The AK4497 detects a clock stop and all circuits including MCLK stop detection circuit, control register and IREF (except LDO when the LDOE pin =
“H”) stop operation if MCLK is not input for 1us (min.) during operation (PDN pin =
“H”). In this case, the analog output goes floating state (Hi-Z). The AK4497 returns to normal operation if PW bit and RSTN bit are
“1” after starting to supply MCLK again. The zero detect function is disabled when MCLK is stopped.
PDN pin
(4)
Internal
State
Normal Operation Power-off Normal Operation
Clock In
MCLK,
MCLK Stop
D/A In
(Digital)
(3)
(1)
(1)
D/A Out
(Analog)
(2) Hi-z
Notes:
(1) The AK4497 detects MCLK stop and becomes power off state when MCLK edge is not detected for
1us (min.) during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting
“0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by the PDN pin or power-on sequence by PW bit are not necessary.
Figure 54. Power ON/OFF by MCLK Clock
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(2) Power ON/OFF by PW bit
All circuits including control register and IREF (except LDO when the LDOE pin =
“H”) stop operation by setting PW bit to
“0”. In this case, control register access is available. The analog output goes to floating
state (Hi-Z). Figure 55 shows power ON/OFF sequence by PW bit.
PW bit
RSTN bit
Internal
State
DAC In
(Digital)
DAC Out
(Analog)
DZFL/DZFR
Normal Operation
(1)
GD
Power-off
“0” data
(3) (2) Hi-z (3)
Normal Operation
GD
(1)
(4)
(5)
Mute ON
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit
= “0”.
(3) Click noise occurs at the edge of PW bit
. This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4497 is power off (PW bit=
“0”). This figure shows the seuqnece when DZFE bit=
“1”, DZFB bit = “0” and DZFM bit= “0”.
(5) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system performance.
External
MUTE
Figure 55. Power ON/OFF Timing Example
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(3) Reset by RSTN bit
Digital circuits except control registers and clock divider are reset by setting RSTN bit to
“0”. In this case, control register settings are held and the analog output becomes VCML/R voltage.
power ON/OFF sequence by RSTN bit.
RSTN bit
3~4/fs (5) 2~3/fs (5)
Internal
RSTN signal
Internal
State
Normal Operation
Digital Block Power-off
Normal Operation
DAC In
(Digital)
“0” data
(1)
GD GD
(1)
(3) (2) (3)
DAC Out
(Analog)
2/fs(4)
DZFL/R
(6)
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is VCOM voltage when RSTN bit
= “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if
“0” data is input.
(4) This figure shows the seuqnece when DZFE bit=
“1”, DZFB bit = “0” and DZFM bit= “0”. The
DZFL/R pin goes
“H” on a falling edge of RSTN bit and goes “L” 2/fs after a rising edge of internal
RSTN bit.
(5) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to
“0” and it takes
2~3/fs when changing RSTN bit to
“1”.
(6) Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 56. Reset Timing Example
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[AK4497]
■
Synchronize Function
(PCM
, EXDF
)
The AK4497 has a function that resets the internal counter to keep the timing of falling edge of the internal clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays between each device can be kept within 4/256fs when using multiple AK4497
’s.
Clock synchronize function becomes valid when input data of both L and R channels are
“0” for 8192 times continuously in PCM mode or EXDF mode, when both L and R channels become
“0” and kept for
8192 times continuously by attenuation or when RSTN bit =
“0”. In PCM mode, the internal counter is synchronized with a rising edged of LRCK (falling edge of LRCK in I2C mode), and it is synchronized with a rising edge of WCK in EXDF mode. In this case, the analog output has the same voltage as VCML/R.
This function is disabled by setting SYNCE bit =
synchronizing sequence when the input data is
“0” for 8192 times continuously.
synchronizing sequence by RSTN bit.
D/A In
(Digital)
SMUTE
(1) (1)
Attenuation
ATT_Level
GD
-
GD GD
(4)
AOUT
(2)
8192/fs
(2)
8192/fs
Both DZFL/R pin
SYNC
Operation (2)
SYNC
Operation (2)
Internal Counter
Reset
(5)
Internal
Data
2~3/fs (3)
Notes:
(1) Regarding ATT Transition time, refer to
“ ■ Output Volume (PCM, DSD, EXDF) ”.
(2) When both L and R channels data are
“0” for 8192 times continuously, the DZFL and DZFR pins become
“H” and the synchronize function is valid.
(3) Internal data is fixed to
“0” forcibly for 2 to 3/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a
“0” data is input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset even if the synchronize function is valid.
Figure 57. Synchronizing Sequenc by Continuous
“0” Data Input for 8192 Times
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[AK4497]
If RSTN bit is set to
“0”, the output signal of the DZFL/DZFR pin becomes “H”. Then, the DAC is reset 3 to
4/fs after the DZFL and the DZFR pins =
“H” and the analog output becomes the same voltage as
VCML/R. The synchronize function becomes valid when both of the DZFL and the DZFR pins output
“H”.
RSTN bit
3~4/fs (4) 2~3/fs (4)
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
D/A In
(Digital) force
”0”
(2)
(3)
GD GD
(3)
(5) (5)
D/A Out
(Analog)
2/fs(4)
Both DZFL/R pin
SYNC Operation (1)
Internal Counter
Reset
Internal
Data
2~3/fs (2)
Note:
(1) The DZFL and the DZFR pins become
“H” by a falling edge of RSTN bit, and becomes “L” 2/fs after a rising edge of internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin =
“H”.
(2) Internal data is fixed to
“0” forcibly for 2 to 3/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to have a no-input period longer than the group delay before writing
“0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN bit. It also takes 2 to 3/fs when rising to change the internal RSTN signal of the LSI. The synchronize function becomes valid immediately when
“0” is written to RSTN bit. Therefore, there is a case that the internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal counter is reset. This noise is output even if a
“0” data is input. Mute the analog output externally if this click noise affects the system performance.
Figure 58. Synchronizing Sequence by RSTN Bit
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[AK4497]
■
Register Control Interface
(1) 3-wire Serial Control Mode
(I2C pin = “L”)
Pins (pin control mode) or registers (register control mode) can control the functions of the AK4497. In pin control mode, the register setting is ignored, and in register control mode the pin settings are ignored.
When the state of the PSN pin is changed, the AK4497 should be powered down by the PDN pin.
Otherwise, malfunctions may occur since previous settings are not initialized. The register control interface is enabled by the
PSN pin = “L”. Internal registers may be written to through 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0),
Read/Write (1bit; fixed to “1”, write only), Register address (MSB first, 5-bits) and Control data (MSB first,
8-bits). The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK.
The writing of data is valid when CSN “
”. The clock speed of CCLK is 5MHz (max).
Setting the PDN pin to “L” resets the registers to their default values. In register control mode, the digital block except control registers and clock divider is reset by setting RSTN bit to
“0”. In this case, the register values are not initialized.
CSN
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 59. Control I/F Timing
* The AK4497 does not support read commands in 3-wire serial control mode.
* When the AK4497 is in power down mode (PDN pin = “L”), writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more during CSN is “L”.
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[AK4497]
(2) I
2
C-bus Control Mode
(I2C pin = “H”)
The AK4497 supports the fast-mode I
2
C-bus (max: 400kHz, Ver 1.0).
(2)-1. WRITE Operations
Figure 60 shows the data transfer sequence for the I
2
C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies the specific device on the bus. The hard-wired input pin (CAD1pins, CAD0 pin) sets these device address
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse ( Figure 67
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4497 and the format is MSB first.
63 ). The AK4497 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition ( Figure 66 ).
The AK4497 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4497 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds
“15H” prior to generating a stop condition, the address counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
START and STOP conditions.
S
T
A
R
T
R/W=
“0”
S
T
O
P
SDA
S
Slave
Address
Sub
Address(n)
Data(n) Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
Figure 60. Data Transfer Sequence at I
2
C Bus Mode
A
C
K
Data(n+x)
A
C
K
P
0 0 1 0 0 CAD1 CAD0 R/W
(CAD0 is set by the pin)
Figure 61. The First Byte
0 0 A1 A0 0 A4 A3 A2
Figure 62. The Second Byte
D7 D6 D5 D4 D3 D2 D1
Figure 63. The Third Byte and After The Third Byte
D0
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[AK4497]
(2)-2. READ Operation
Set the R/W bit = “1” for the READ operation of the AK4497. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds
“15H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data of “00H” will be read out.
The AK4497 supports two basic read operations: Current Address Read and Random Address Read.
(2)-2-1. Current Address Read
The AK4497 has an internal address counter that maintains the address of the last accessed word incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4497 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4497 ceases the transmission.
S
T
A
R
T
R/W=
“1”
S
T
O
P
SDA
S
Slave
Address
Data(n) Data(n+1) Data(n+2) Data(n+x) P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 64. Current Address Read
(2)-2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit
“1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W b it = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit
“1”. The AK4497 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4497 ceases the transmission.
S
T
A
R
T
R/W=
“0”
S
T
A
R
T
R/W=
“1”
S
T
O
P
SDA
S
Slave
Address
Sub
Address(n)
S
Slave
Address
Data(n) Data(n+1) Data(n+x) P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 65. Random Address Read
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[AK4497]
SDA
SCL
S start condition
P stop condition
Figure 66. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
SDA
1
2
Figure 67. Acknowledge (I
2
C Bus) not acknowledge
8 acknowledge
9 clock pulse for acknowledgement
SCL data line stable; data valid change of data allowed
Figure 68. Bit Transfer (I
2
C Bus)
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[AK4497]
■
Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1
01H Control 2
02H Control 3
03H Lch ATT
04H Rch ATT
05H Control4
06H DSD1
07H Control5
08H Sound Control
09H DSD2
0AH Control 7
0BH Control 8
0CH Control 9
0DH Reserved
0EH Reserved
0FH Reserved
10H Reserved
11H Reserved
12H Reserved
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
TDM1
ATS1
0
0
0
0
0
0
0
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
TDM0
ATS0
0
0
0
0
0
0
0
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
SDS1
0
0
0
0
0
0
0
0
AFSD
DFS1
DCKB
ATT4
ATT4
0
DMC
0
0
0
SDS2
SDS0
0
0
0
0
0
0
0
DIF2
DFS0
MONO
ATT3
ATT3
0
DMRE
GC2
HLOAD
0
0
0
0
0
0
0
0
0
0
DIF1
DEM1
DZFB
ATT2
ATT2
RSTPG
0
GC1
SC2
DIF0
DEM0
SELLR
ATT1
ATT1
DFS2
DSDD
GC0
SC1
DSDPATH DSDF
PW 0
0
0
0
DCHAIN
0
0
0
0
0
0
0
0
0
0
0
0
13H Reserved
14H Reserved
15H DFS read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0 0 0 0 ADFS2 ADFS1 ADFS0
Notes:
• In 3-wire serial control mode, the AK4497 does not support read commands.
• The AK4497 supports read command in I
2
C-bus control mode.
• If the address exceeds “15H”, the address counter will “roll over” to “00H” and the next write/read address will be
“00H” by automatic increment function in I2C-Bus mode.
• Data must not be written into 0 bits, TEST bit in “0BH” and registers from “16H” to “1FH”. Malfunctions may occur if data is written to these bits.
• When the PDN pin goes to “L”, the registers are initialized to their default values.
• When RSTN bit is set to “0”, the digital block except control registers and clock divider is reset, and the registers are not initialized to their default values.
• When the state of the PSN pin is changed, the AK4497 should be reset by the PDN pin.
(Note) The AK4497 is register compatible with the AK4490 and the AK4495.
RSTN
SMUTE
SLOW
ATT0
ATT0
SSLOW
DSDSEL0
SYNCE
SC0
DSDSEL1
0
TEST
0
0
0
0
0
0
0
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(Reference) AK4490 Register Map
Addr Register Name
00H Control 1
01H Control 2
02H Control 3
03H Lch ATT
04H Rch ATT
05H Control4
06H DSD1
07H Control5
08H Sound Control
09H DSD2
D7
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
(Reference) AK4495 Register Map
Addr Register Name D7
00H Control 1
01H Control 2
02H Control 3
03H Lch ATT
04H Rch ATT
05H Control4
06H Control5
07H Control6
08H Sound Control
09H Reserved
ACKS
DZFE
DP
ATT7
ATT7
INVL
DDM
0
0
0
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
D6
EXDF
DZFM
0
ATT6
ATT6
INVR
DML
0
0
0
D5
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
D5
ECS
SD
DCKS
ATT5
ATT5
0
DMR
0
0
0
[AK4497]
D4
0
D3
DIF2
D2
DIF1
D1
DIF0
D0
RSTN
DFS1 DFS0 DEM1 DEM0 SMUTE
DCKB MONO DZFB SELLR SLOW
ATT4
ATT4
ATT3
ATT3
ATT2
ATT2
ATT1
ATT1
ATT0
ATT0
0
DMC
0
0
0
0
DMRE
0
0
0
0
0
0
0
0
DFS2
0
SC1
DSDF
DFTHR
DSDD DSDSEL0
SYNCE
SC0
DSDSEL1
D4 D3 D2 D1 D0
0
DFS1
DIF2
DFS0
DCKB MONO
ATT4
ATT4
0
DMC
ATT3
ATT3
DIF1
DEM1
DZFB
ATT2
ATT2
DIF0
DEM0
SELLR
ATT1
ATT1
RSTN
SMUTE
SLOW
ATT0
ATT0
0 0 DFS2 DFTHR
DMRE DSDD1 DSDD0 DSDSEL
0
0
0
0
0
0
0
SC2
0
0
SC1
0
SYNCE
SC0
0
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[AK4497]
■
Register Definitions
Addr Register Name
00H Control 1
R/W
Default
D7
ACKS
R/W
0
D6
EXDF
R/W
0
D5
ECS
R/W
0
D4
AFSD
R/W
0
D3
DIF2
R/W
1
D2
DIF1
R/W
1
D1
DIF0
R/W
0
D0
RSTN
R/W
0
RSTN: Internal Timing Reset
0: Reset. All registers are not initialized. (default)
1: Normal Operation
Writing
“0” to this bit resets the internal timing circuit but register values are not initialized.
DIF[2:0]: Audio Data Interface Modes ( Table 23 )
Initial value is
“110” (Mode 6: 32-bit MSB justified)
AFSD: Sampling Frequency Auto Detect Mode Enable (PCM & EXDF mode only). ( Table 5 )
0: Disable: Manual or Auto Setting Mode (default)
1: Enable: Auto Detect Mode
When AFSD bit =
“1”, DFS[2:0] bits are ignored.
ECS: EXDF mode clock setting ( Table 22 )
0: WCK=768kHz mode (default)
1: WCK=384kHz mode
EXDF: External Digital Filter I/F Mode (Register Control mode only)
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM & EXDF mode only). ( Table 13
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
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[AK4497]
Addr Register Name
01H Control 2
R/W
Default
D7
DZFE
R/W
0
D6
DZFM
R/W
0
D5
SD
R/W
1
D4
DFS1
R/W
0
D3
DFS0
R/W
0
D2
DEM1
R/W
0
D1 D0
DEM0 SMUTE
R/W
1
R/W
0
SMUTE: Soft Mute Enable
0: Normal Operation (default)
1: DAC outputs soft-muted.
DEM[1:0]: De-emphasis Filter Control ( Table 29 )
Initial value is
“01” (OFF).
DFS[1:0]: Sampling Speed Control. ( Table 7
Initial value is
“000” (Normal Speed). Click noise occurs when DFS1-0 bits are changed.
SD: Minimum delay Filter Enable. ( Table 27 )
0: Traditional filter
1: Short delay filter (default)
DZFM: Data Zero Detect Mode
0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both L and R channels go to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles.
DZFE: Data Zero Detect Enable
0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”.
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[AK4497]
Addr Register Name
02H Control 3
R/W
Default
D7
DP
R/W
0
D6
0
R/W
0
D5
DCKS
R/W
0
D4 D3
DCKB MONO
R/W
0
R/W
0
D2
DZFB
R/W
0
SLOW: Slow Roll-off Filter Enable. ( Table 27 )
0: Slow roll-off filter disable (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
L channel output L channel data, Rchannel data output Rchannel data(default)
1: All channel output R channel data, when MONO mode.
L channel output R channel data, Rchannel data output Lchannel data
DZFB: Inverting Enable of DZF. ( Table 34 )
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4497 should be reset by RSTN bit.
D1 D0
SELLR SLOW
R/W
0
R/W
0
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Addr Register Name
03H Lch ATT
04H Rch ATT
R/W
Default
D7
ATT7
ATT7
R/W
1
ATT[7:0]: Attenuation Level
255 levels 0.5dB step + mute
Data Attenuation
FFH 0dB (default)
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-
)
D6
ATT6
ATT6
R/W
1
D5
ATT5
ATT5
R/W
1
D4
ATT4
ATT4
R/W
1
D3
ATT3
ATT3
R/W
1
Addr Register Name
05H Control 4
R/W
Default
D7
INVL
R/W
0
D6
INVR
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
0
R/W
0
SSLOW: Super Slow Roll Off (Digital Filter bypass mode) Enable. ( Table 27 )
0: Disable (default)
1: Enable
DFS2: Sampling Speed Control. ( Table 10 )
RSTPG: Programmable Filter Coefficient Reset
0: Disable (default)
1: Reset Coefficient
INVR: AOUTR Output Phase Inverting
0: Disable (default)
1: Enable
INVL: AOUTL Output Phase Inverting
0: Disable (default)
1: Enable
D2
ATT2
ATT2
R/W
1
[AK4497]
D1
ATT1
ATT1
R/W
1
D0
ATT0
ATT0
R/W
1
D2 D1 D0
RSTPG DFS2 SSLOW
R/W
0
R/W
0
R/W
0
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[AK4497]
Addr Register Name
06H Control 4
R/W
Default
D7
DDM
R/W
0
D6
DML
R
0
D5
DMR
R
0
D4
DMC
R/W
0
D3
DMRE
R/W
0
D2
0
R/W
0
D1 D0
DSDD DSDSEL0
R/W
0
R/W
0
DSDSEL[1:0]: DSD sampling speed control
00: 2.8224MHz
01: 5.6448MHz
10: 11.2896MHz
11: 22.5792MHz
DSDD: DSD play back path control
0: Normal Path (default)
1: Volume Bypass
DMRE: DSD Mute Release
This register is only valid when DDM bit =
“1” and DMC bit = “1”. When the AK4497 mutes
DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit to
“1”.
0: Hold (default)
1: Mute Release
DMC: DSD Mute Control
This register is only valid when DDM bit =
“1”. It selects the mute releasing mode of when the
DSD data level becomes under full-scale after the AK4497 mutes DSD data by DDM bit setting.
0: Auto Return (default)
1: Mute Hold
DMR/DML
This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
(only in I2C mode)
DDM: DSD Data Mute
The AK4497 has an internal mute function that mutes the output when DSD audio data becomes all
“1” or all “0” for 2048 Samples (1/fs). DDM bit controls this function.
0: Disable (default)
1: Enable
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[AK4497]
Addr Register Name
07H Control 5
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
R/W
0
D3
GC2
R/W
0
SYNCE: SYNC Mode Enable
0: SYNC Mode Disable
1: SYNC Mode Enable (default)
GC[2:0]: PCM, DSD mode Gain Control
Table 32. Output Level between Set Values of GC[2:0] bit
GC[2] GC[1] GC[0]
AOUTLP/LN/RP/RN Ouput Level
PCM
DSD:
Normal Path
DSD:
Volume
Bypass
0
0
0
0
1
1
1
1
Addr Register Name
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.8Vpp
2.8Vpp
2.5Vpp
2.5Vpp
3.75Vpp
3.75Vpp
2.5Vpp
2.5Vpp
08H Sound Control
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
SC[2:0]: Sound Control. ( Table 37 , Table 38 )
HLOAD: Heavy Load Mode Enable
0: Heavy Load Mode Disable (default)
1: Heavy Load Mode Enable
D5
0
R/W
0
2.8Vpp
2.5Vpp
2.5Vpp
2.5Vpp
3.75Vpp
2.5Vpp
2.5Vpp
2.5Vpp
D4
0
R/W
0
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
2.5Vpp
D3
HLOAD
R/W
0
D2
GC1
R/W
0
D2
SC2
R/W
0
D1
GC0
R/W
0
(default)
D1
SC1
R/W
0
D0
SYNCE
R/W
1
D0
SC0
R/W
0
Rev. 0.1
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2015/11
[AK4497]
Addr Register Name
09H DSD2
R/W
Default
D7
0
R
0
D6
0
R
0
DSDSEL1: DSD Sampling Speed Control.
DSDF: Cut-off frequency of DSD Filter Control
DSDPATH: DSD Data Input Pin Select
0: #16, 17, 19 (default)
1: #3, 4, 5
DP bit EXDF bit
DSDPATH bit
D/A Conv.
Mode
0
(default)
1
0
(default)
*
1
0
(*: Do not care)
*
1
*
0
(default)
1
*
PCM
DSD
DSD
EXDF
D5
0
R
0
D4
0
R
0
#3 pin #4 pin
D3
0
R
0
D2
0
D1
0
D0
DSDPATH DSDF DSDSEL1
R/W R/W R/W
0
Pin Assignment
#5 pin #16 pin #17 pin #19 pin
BICK SDATA LRCK Not Use Not Use Not Use
Not Use Not Use Not Use DCLK
DCLK
BCK
DSDL
DINL
DSDR
DINR
Not Use
Not Use
DSDL
Not Use
Not Use
DSDR
Not Use
Not Use
Rev. 0.1
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Addr Register Name
0AH Control 7
R/W
Default
D7
TDM1
R/W
0
D6
TDM0
R/W
0
D5
SDS1
R/W
0
PW: Power ON/OFF Control
0: Power Off
1: Power On (default)
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot ( Table 24 )
Default value is
“000”
TDM[1:0]: TDM Mode Select
00: Normal (default)
01: TDM128
10: TDM256
11: TDM512
D4
SDS2
R/W
0
D3
0
R/W
0
[AK4497]
D2
PW
R/W
1
D1
0
R/W
0
D0
0
R/W
0
Rev. 0.1
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2015/11
Addr Register Name
0BH Control 8
R/W
Default
D7
ATS1
R/W
0
D6
ATS0
R/W
0
D5
0
R/W
0
D4
SDS0
R/W
0
D3
0
R/W
0
TEST:
“0” data must be written to Test bit. Otherwise malfunctions may occur.
DCHAIN: Daisy Chain Mode Enable
0: Daisy Chain Mode Disable (default)
1: Daisy Chain Mode Enable
SDS[2:0]: Output Data Slot Selection of Each Channel
0: Normal Operation
1: Changing Data Slot ( Table 24 )
Default value is
“000”.
ATS[1:0]: Transition Time between Set Values of ATT[7:0] bits ( Table 31 )
Default value is
“00”.
Addr Register Name D7 D6 D5 D4 D3
0CH Reserved
0DH Reserved
R/W
Default
0CH: Reserved
0DH: Reserved
0
0
R/W
0
0
0
R/W
0
0
0
R/W
0
0
0
R/W
0
0
0
R/W
0
D2
0
R/W
0
D2
0
0
R/W
0
D1 D0
DCHAIN TEST
R/W
0
R/W
0
D1
0
0
R/W
0
[AK4497]
D0
0
0
R/W
0
Rev. 0.1
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2015/11
[AK4497]
Addr Register Name
0EH Reserved
0FH Reserved
10H Reserved
11H Reserved
R/W
Default
0EH: Reserved
0FH: Reserved
10H: Reserved
11H: Reserved
Addr Register Name
D7
0
0
0
0
R/W
0
D6
0
0
0
0
R/W
0
D5
0
0
0
0
R/W
0
D4
0
0
0
0
R/W
0
D3
0
0
0
0
R/W
0
12H Reserved
13H Reserved
14H Reserved
R/W
Default
12H: Reserved
13H: Reserved
14H: Reserved
Addr Register Name
15H ADFS read
R/W
Default
D7
0
0
0
R
0
D6
0
0
0
R
0
D5
0
0
0
R
0
D4
0
0
0
R
0
D3
0
0
0
R
0
D7
0
R
0
D6
0
R
0
D5
0
R
0
D4
0
R
0
D3
0
R
0
D2
ADFS2
R
0
ADFS[2:0]: Mode Detection Result in FS Auto Detect Mode
ADFS2 ADFS1 ADFS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Quad Speed Mode
Oct Speed Mode
Hex Speed Mode
Oct Speed Mode
Hex Speed Mode
D2
0
0
0
R
0
D2
0
0
0
0
R/W
0
D1
ADFS1
R
0
D1
0
0
0
0
R/W
0
D1
0
0
0
R
0
D0
ADFS0
R
0
D0
0
0
0
0
R/W
0
D0
0
0
0
R
0
Rev. 0.1
- 90 -
2015/11
[AK4497]
DSP
Micro-
Controller
10.
Recommended External Circuits
Digital 3.3V Digital 1.8V
AVDD 3.3V
10u +
0.1u
+ 1u
10u
+
0.1u
33k 470u
+
0.1u
10u
+
1
LDOE
2
PDN
3
BICK/BCK
4
5
6
SDATA/DINL
LRCK/DINR
SSLOW/WCK
TDMO 7
8
SMUTE/CSN
9
SD/CCLK/SCL
10
SLOW/CDTI/SDA
11 DIF0/DZFL
12
DIF1/DZFR
13
DIF2/CAD0
14
PSN
15 HLOAD/I2C
16
DEM0/DSDL
Analog 5.0V
Lch
LPF
Lch
Mute
Lch Out
AOUTLP
48
0.1u 10u
+
AOUTLP
47
VDDL
46
VDDL
45
VDDL
44
VSSL 43
0.1u
VSSL
42
VSSL
41
+
10u
VSSR
N
VSSR
N
40
39
VSSR 38
0.1u
VDDR 37
VDDR
36
VDDR
35
AOUTRP
34
AOUTRP
33
+
10u
+
Electrolytic Capacitor
Ceramic Capacitor
Resistor
Rch
LPF
Rch
Mute
Rch Out
0.1u
+
470u
+
10u
Notes:
-
Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately from the point with low impedance of regulator etc.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog ground should has low impedance as a solid pattern. THD+N characteristics will degrade if there are impedances between each VSS.)
- THD+N characteristics will degrade by high frequency noise of MCLK. Connect a 51
Ω damping resistor to the MCLK pin.
- When AOUT drives a capacitive load, some resistance should be connected in series between
AOUT and the capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 69. Typical Connection Diagram
(AVDD=TVDD=3.3V, VDDL/R=5.0V, LDOE=
“L”, Register Control Mode)
Rev. 0.1
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2015/11
[AK4497]
1.
Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD, DVDD,
VDDL and VDDR. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and DVDD are supplied from digital supply in system. Power lines of VDDL/R should be distributed separately from the point with low impedance of regulator etc. When not using LDO (LDOE pin =
“L”), AVDD and TVDD should be powered up before or at the same time of DVDD. When using LDO (LDOE pin =
“H”), power up sequence between AVDD/TVDD and VDDL/R are not critical. AVSS, DVSS, VSSL and VSSR must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2.
Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the full scale of the analog output range.
The VREFHL/R pin is normally connected to VDD, and the VREFLL/R pin is normally connected to VSS.
VREFHL/R and VREFLL/R should be connected with a 0.1µF ceramic capacitor and a 2200uF electrolytic capacitor as near as possible to the pin to eliminate the effects of high frequency noise.
The VREFH and VREFL pins should be treated to not have noises from other supply pins. If the analog characteristics cannot satisfy the specification by this noise, connect the VREFH to analog 5.0V via a 10
Ω resistor and connect the VREFL pin to the analog ground via a 10
Ω resistor. (A low-pass filter of fc=500Hz will be composed by a 2200uF capacitor and a 10
Ω resistor. This low-pass filter removes signal frequency noise from other power supply pins.)
VCML/R is a common voltage of this chip. No load current may be drawn from the VCML/R pin. All signals, especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4497.
3. Analog Outputs
The analog outputs are full differential outputs. The differential outputs are summed externally, V
AOUT
=
(AOUT+)
(AOUT
) between AOUT+ and AOUT
. If the summing gain is 1, the output range of the setting the GAIN pin =
“L” or GC[2] bit = “0” is 2.8Vpp (typ, VREFHL/R
VREFLL/R = 5V) centered around VCML and VCMR voltages. In this case, the output range after summing will be 5.6V (typ.). The output range of the setting the GAIN pin =
“H” or GC[2] bit = “1” is 3.75Vpp (typ.) centered around VCML and VCMR voltages. In this case, the output range after summing will be 7.5Vpp (typ.). The bias voltage of the external summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (V
AOUT
) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal V
AOUT
is 0V for 00000000H (@32bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond
external LPF circuit with two op-amps. Figure 73 shows an example of external LPF circuit with two
op-amps when MONO bit =
“1”. A resistor that has 0.1% or less absolute error must be used for external
LPFs.
AK4497
300 300
AOUT-
30 6.8n
43n
AOUT+
100
+Vop
10
20n
2
7
6
3
4
-Vop
OPA1611
Analog
Out
130n 100
Figure 70. External LPF Circuit Example 1 (fc = 98kHz(typ), Q=0.667(typ))
Rev. 0.1
- 92 -
2015/11
Rev. 0.1
Table 43. Frequency Response of External LPF Circuit Example 1
Gain(1kHz,typ) 0 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
40kHz
80kHz
-0.07 dB
-0.32 dB
-2.13 dB
AK4497
AOUT-
AOUT+
215
39.2n
33.2
255n
90.9
590
33 3.09n
+Vop
5.1
20n
2
7
6
3
4
-Vop
OPA1611
Analog
Out
Figure 71. External LPF Circuit Example 2 (fc = 104kHz(typ), Q=0.693(typ))
Table 44. Frequency Response of External LPF Circuit Example 2
Gain(1kHz,typ) +8.78 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
40kHz
80kHz
-0.02 dB
-0.15 dB
-1.46 dB
[AK4497]
+15
-15
AK4497
AOUT-
+
100u
22
22
56n
27n
3
2
8
+
-
*
4
1
OPA1612
400
+
10u
0.1u
+
0.1u
10u
Lch
AOUT+
100u
+
22
22
56n
27n
+
10u
0.1u
5
6
8
+
-
4
7
OPA1612
LME49710
400
+
0.1u
10u
Figure 72. External LPF Circuit Example 3 (fc = 186kHz(typ), Q=0.67(typ))
Table 45. Frequency Response of External LPF Circuit Example 3
Gain(1kHz,typ) +9.54 dB
Frequency
Response
(ref:1kHz,typ)
20kHz
40kHz
80kHz
-0.01 dB
-0.06 dB
-0.32 dB
- 93 -
2015/11
[AK4497]
AK4497
AOUTLP
+
100u
44
22
56n
27n
3
2
8
+
-
*
4
1
OPA1612
400
+
10u
0.1u
+
0.1u
10u
+15
-15
AOUTLN
+
100u
44
AOUTRP
100u
+
44
22
56n
27n
+
10u
0.1u
5
6
8
+
-
4
7
OPA1612
LME49710
400
+
0.1u
10u
AOUTRN
100u
+
44
Figure 73. External LPF Circuit Example for mono mode (fc = 186kHz(typ), Q=0.67(typ))
Rev. 0.1
- 94 -
2015/11
■
Outline Dimensions
(HTQFP10×10-64)
64
11.
Package
12.0 ± 0.20
49
1
48
A
[AK4497]
S
16
17
0.50
0.22 ± 0.05
32
0.10
M S A C
10.0 ± 0.20
33
0.10
S
0.60 ± 0.15
Rev. 0.1
(5.95)
- 95 -
2015/11
■
Material & Lead Finish
Package molding compound: Epoxy, Halogen (bromine and chlorine) free
Lead frame material: EFTEC64
Lead frame surface treatment: Solder (Pb free) plate
■
Marking
[AK4497]
64
1
AK4497EQ
XXXXXXX
AKM
1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX (7 digits)
4) Marking Code: AK4497EQ
5) Audio 4 pro Logo
Rev. 0.1
- 96 -
2015/11
[AK4497]
12.
Ordering Guide
■
Ordering Guide
AK4497
40
+85
C (Assuming the exposed pad is connected to the printing board)
64-pin TQFP (0.5mm pitch)
AKD4497 Evaluation Board for AK4497
Rev. 0.1
- 97 -
2015/11
[AK4497]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation
(“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (
“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE
USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the
Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.
Rev. 0.1
- 98 -
2015/11
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