GE Fanuc Series Six Bus Contoller Manual

GE Fanuc Series Six Bus Contoller Manual

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GE Fanuc Automation

Programmable Control Products

.

Series

Six'"

Bus Controller

User’s Manual

GFK-0171B

July, 1991

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GFL-002

WARNINGS, CAUTIONS, AND NOTES AS USED IN THIS PUBLICATION

/ WARNING /

Warning notices are used in this publication to emphasize that hazardous voltages, currents, temperatures, or other conditions that could cause personal injury exist in this equipment or may be associated with its use.

In situations where inattention could cause either personal injury or damage to equipment, a Warning notice is used

CAUTION

Caution notices are used where equipment might be damaged if care is not taken.

NOTE

Notes merely call attention to information that is especklly significant to understanding and operating the equipment.

This document is based on information available at the time of its publication. While efforts have been made to be accurate, the information contained herein does not purport to cover all details or variations in hardware and software, nor to provide for every possible contingency in connection with instalktion, operation, and maintenance. Features may be described herein which are not present in all hardware and software systems. GE Fanuc Automation assumes no obligation of notice to holders of this document with respect to changes subsequently made.

GE Fanuc Automation makes no representation or warranty, expressed, implied, or statutory with respect to, and assumes no responsibility for the accuracy, completeness, sufficiency, or usefulness of the information contained herein. No warranties of merchantability or fimess for purpose shall apply.

The following are trademarks for products of

GE Fanuc Automation

North America, Inc.

Aiaxm Master

CIMPLICITY

CXMPLICITY 9%ADS

CIMPLICITY PowerTRAC

CIhNrAR

GEnet

Genius

Genius PowerTIUC

Helpmate

Logicmaster

Modelmaster

ProLoop

PROMACRO

Series One series Three

Series Five series six series 90

VuMaster

Workmaster

@Copyright 1991

GE

Fanuc Automation North America, inc,

AD Rights Reserved.

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l **

111

Preface

GFK-017 1

This manual explains how to set up and install a Series Six 1~ PLC Bus Controller.

It also provides programming information needed to complete the interface between a Series Six PLC and one or more

GeniusTM I/O communications busses.

Use the

Genius II0 System User’s A4anual (GEK-90486) as your primary reference for information about Genius I/O products. It describes types of systems, system planning, installation, and system components.

Contents of this Manual

This book contains 10 chapters and 2 appendixes. For basic information about the functions of a Bus

Controller in a Series Six PLC system, begin by reading chapter 1. Lists of topics at the end of chapter 1 will help you find additional information.

Chapter 1. Introduction:

Chapter 1 describes Bus Controller types, the serial bus, Bus Controller operation, and system operation.

Chapter 2. Setup and Installation:

Chapter 2 explains how to set the on-board and backplane DIP switches when installing a Bus Controller.

Chapter 3. Using Genius I/O with the Series Six PLC:

Chapter 3 includes information about assigning Reference Numbers, and describes special programming for analog blocks.

Chapter

4.

Automatic Diagnostics and Fault Clearing:

Chapter 4 explains how the Expanded

Functions of the Series Six Plus PLC can automatically capture, display, and clear faults.

Chapter 5. Programming Window Commands:

Chapter 5 explains optional programming to read or write configuration data, read diagnostics, read analog inputs, read a status table address, or switch a

BSM.

Chapter

6.

Datagrams:

Chapter 6 explains optional progr arnming for Datagram and Global Data communications between devices on the bus.

Chapter 7. Global Data:

Chapter 7 explains optional progr amming for Global Data communications.

Chapter 8. Programming for Diagnostics using the Bus Controller Input References:

Chapter 8 describes optional programmin g to obtain diagnostics information from the Bus Controller.

Chapter 9. Programming Commands to I/O Blocks using the Bus Controller Output References:

Chapter 9 describes optional progr amming to clear faults, Pulse Test discrete outputs, or selectively disable outputs.

Chapter

10.

Chapter 10 lists errors that might occur and suggests corrective actions.

Appendix A. Expanded I/O Addressing:

Appendix A shows how Expanded I/O is mapped for with diffferent amounts of memory.

CPUs

Appendix B. Bus Controller Compatibility:

Compares the features of phase A and phase B BUS

Controllers.

Related Publications

For additional information, refer to the following publications:

Logicmuster 6 Sofnvare User’s Manual (GEK-25379).

This book is the primary reference for the

Logicmaster 6 programmin g software. It serves both as a software user’s guide and a programmer’s guide. The first part of the book describes the operating features of the Logicmaster 6 software, such as

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iv Preface

GFK-0171 file-handling, display tables,, and program printout. The second part of the book defines ladder logic instructions for the Series Six and Series Six Plus PLCs.

Series 90-70 Bus Controller User’s Manual (GFK-0398). This manual describes the Series 90-70 Bus

Controller, and explains how to interface a Series

90-70 PLC to a Genius bus.

Series Six Bus Controller data sheet (GFK-0025). This data sheet describes operation, installation, and specifications of the Bus Controller.

Genius I/O PCIM User’s Manual (GF’K-0074). This manual describes the Genius I/O IBM PC Interface

Module (PCIM). The PCIM module is used to interface a [email protected] or CIMSTARTM I industrial computer or an IBM PC/XT/AT industrial computer to the Genius I/O serial bus.

Series FivefM Bus Controller User’s Manual (GFK-0248). This manual explains how to set up a Series

Five PLC Bus Controller and how to interface a Series Five PLC to one or more GeniusTM I/O busses.

In addition, each Genius I/O product has its own data sheet, which includes basic reference information and installation instructions.

Jeanne Grimsby

Technical Writer

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Content

GFK-017 1

CHAPTER 1.

CHAPTER

CHAPTER

CHAPTER

2.

3,

4.

CHAPTER 5.

.

INTRODUCTION

Types of Bus Controller

LEDs

Hand-held Monitor Connector

Bus Wiring Terminals

The Bus

Bus Controller Location

Bus Controller Operation

Completing the Interface

SETUP AND INSTALLATION

Selecting Terminating Impedance

Enabling CPU Shutdown Mode

Setting the Baud Rate

Changing the Bus Controller Device Number

Selecting Expanded I/O Addressing

Disabling Outputs

Bus Controller Reference Number

INTERFACING GENIUS I/O BLOCKS TO THE SERIES

SIX PLC

Assigning Reference Numbers in I/O or Register

Memory

Assigning Reference Numbers in I/O Memory

Analog Input and Output Data

Programming for Analog Inputs

Special Progr amming Required for:

Analog Blocks

High-Speed Counter Blocks

PowerTRAC Blocks

AUTOMATIC DIAGNOSTICS AND FAULT CLEARING

The CPU Configuration Instruction

Expanded Functions Menu

CPU Configuration Setup Menu

Genius Bus Controller Locations Screen

Genius I/O Fault Table Screen

Clearing Faults

Printing a Copy of the Fault Table Screen

PROGRAMMING

WINDOW COMMANDS

Program Instructions

Program Structure

Timing for Window Commands

Idle

Read Configuration

Write Configuration

Read Diagnostics

Read Analog Inputs

Read Status Table Reference

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l-l l-2 l-2 l-2 l-3 l-4

17 lh

2-2

2-3

2-3

2-3

2-3

2-5

2-7

4-1

4-l

4-2

4-7

48

4-10

4110

3-1

3-2

3-6

3-7

3-9

3-9

3-9

3-9

5-l

5-5

5-5

5-7

58

5-12

5-16

5-18

5121

vi

Content

GFK-0171

CHAPTER 5.

PROGRAMMING WINDOW COMMANDS (cant)

Switch BSM

CHAPTER 6.

CHAPTER 7.

DATAGRAMS

Types of Datagrams Supported

Using Datagrams instead of Global Data

Normal or High Priority Datagrams

Programming for Incoming Datagrams

Effects of Datagrams on the Genius I/O Bus

Maximum CPU Sweep Time Increase for Datagrams

Assign Monitor Datagram

Write Device Datagram

Write Point Datagram

Read Device Datagram

GLOBALDATA

Programming to Send Global Data

Example Ladder Logic for Global Data

Programming to Receive Global Data

Maximum CPU Sweep Time Increase for Global Data

Using Global Data to Check CPU Operation

CHAPTER 8.

PROGRAMMING FOR DIAGNOSTICS USING BUS

CONTROLLER INPUT REFERENCES

Bus Controller Input Reference Formats

Monitoring Bus Controller Status

Checking for Bus Errors

Detecting I/O Circuit Faults

Detecting the Loss or Addition of a Block

Detecting Reference Number Conflict

Detecting Execution of a Pulse Test

Detecting a Force Condition on the Bus

Storing Diagnostic Information in CPU Registers

CHAPTER 9. PROGRAMMING COMMANDS TO I/O BLOCKS USING

THE BUS CONTROLLER OUTPUT REFERENCES

Bus Controller Output References

Enabling or Disabling all Outputs from the Bus

Controller

Pulse Testing Outputs

Clearing all Faults on the -Bus

Clearing a Specific Circuit Fault

CHAPTER 10.

APPEND=

A.

TROUBLESHOOTING

How to Begin

Identifying the Problem

Expanded I/O Addressing

Expanded I/O Addressing for 8K and 16K Registers

Expanded I/O Addressing for 1K Registers

Expanded I/O Addressing for 256 Registers

APPENDIX B.

Bus Controller Compatibility

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5-22

7-2

7-3

7-5

7-5

7-5

10-l

10-l

A-1

A-1

A-2

A-2

B-l

9-1

9-3

9-3

9-4

9-4

8-2

8-4

8-6

87

8-10

8-12

8-14

8-15

8:16

6-1

6-2

6-2

6-3

6-4

6-4

6-5

68

6-11

6113

Chapter

1

Introduction

GFK-0171

The Series SW PLC Bus Controller is used to interface a GeniusTM I/O serial bus to the Series Six PLC.

The bus can serve up to 31 other devices including Genius I/O blocks, Hand-held Monitors, and other interface modules.

The bus can provide I/O service to all types of Genius I/O blocks. It can also be used for programmed communications between the Series Six PLC and other devices. The same PLC system may include several busses, interacting with a wide range of I/O devices, as well as other PLCs and host computers.

Types of Bus Controller

Two types of Bus Controller are available: l a Bus Controller with Diagnostics (IC66OCBB902), which automatically sends diagnostic reports from Genius I/O blocks to the CPU. l a Bus Controller without Diagnostics (IC660CBB903), which does not. Diagnostics from the blocks are still available to the Hand-held Monitor when this Bus Controller is used.

Both types of BUS Controller send the CPU diagnostic information about their own operation, and the condition of the bus.

This book describes “phase B” Bus Controllers (IC660CBB902 and CBB903). These enhanced modules are required for: l

A bus which uses any baud rate other than 153.6 Kbaud standard, or which is than 2000 feet. l

A bus that includes RTD blocks or any Genius I/O block that has more than 64 input bits or 64 output bits

. l

Programmed communications from one CPU to another. l

Redundancy (more than one bus to the same group of I/O blocks, more than one CPU that is able to communicate with the same group of blocks, or more than one Bus Controller controlling I/O on the same bus).

Using Phase B Bus Controller with Phase A Products

A complete programmable controller system may include both phase A and phase B

BUS Chxdhs

(IC66OCBB900 and CBB901). Phase B Bus Controllers can be used to replace phase A Bus Control- lers, or be added to a PLC system that already includes phase A Bus Controllers. However, only one phase B Bus Controller can be located on a bus with any Phase A products of any kind For more information about differences between Phase A and Phase B Bus Controllers, see appendix A.

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The Bus Controller is a standard, rack-mounted Series Six PLC module.

0

BOARDOKLED

COMM OK LED

HHM CONNECTCR

Introduction

GFIS-0171

A Bus Controller may be located in the CPU rack or in a regular or High-capacity local I/O rack (that is, a rack communicating with the CPU via a parallel chain). Each Bus Controller draws 20 units of load

(one unit = 300mW) at +5 volts. A phase B Bus Controller does not use +12 volts.

The only limit on the number of Bus Controllers used in a PLC system is the I/O addressing capacity of the CPU.

LEDs

The Bus Controller has two LEDs: l

BOARD OK shows the status of the Bus Controller. l

COMM OK shows the status of the bus.

Hand-held Monitor Connector

The Hand-held Monitor connector on the Bus Controller faceplate provides access to all devices on the bus. All Hand-held Monitor functions except I/O block configuration can be performed with the HHM connected to the Bus Controller. Bus and block operation can be monitored, circuits forced or unforced, outputs Pulse Tested, diagnostic messages displayed, and faults cleared, from a convenient central location.

Bus Wiring Terminals

The upper four terminals on the terminal strip are used for the serial bus and shield wiring connections.

The lowest connector jumpers Shield Out to chassis ground. The remaining connectors are not used.

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Introduction

GFK-017 1

The

Bus

A shielded, twisted pair cable connects the Bus Controller to up to 31 other devices. These may be

Genius I/O blocks, Hand-held Monitors, or other interface modules (Bus Controllers or PCIW). a42564

I

PLC

BUS

CONTROLLER

I

1

COMMUNICATIONS

BUS

HAND-HELD

MONITOR w

I

1 i/O BLOCKS

A bus can serve all types of Genius I/O blocks. Phase A Genius I/O blocks can be located on a bus that meets the restrictions for use with phase A blocks. In a basic I/O control system, one bus may serve up to

30

Genius

I/O

blocks and one Hand-held Monitor. The total number of I/O circuits that can be included on the bus depends on the types of I/O blocks that are used. Genius discrete I/O blocks are available in several different types, with 8 to 32 circuits each. The maximum number of I/O circuits possible on one bus would result from using 30 discrete blocks with 32 I/O circuits each. The total number of discrete circuits would be 960. For applications requiring very fast response times, fewer blocks might be located on a bus, with additional blocks distributed on other busses.

Analog blocks (including the low-level analog RTD blocks) have 6 circuits each. Therefore, the maximum number of analog circuits on one bus is 6 circuits times 30 blocks, or 180. Because of the length of time required to transmit analog data, special progr amming (see chapter 3) will be required if more than 5 analog blocks

are

used on the same bus.

Number of Busses in the System

The

only limit to the number of busses in the system is the I/O addressing capacity of the Series Six

CPU. Different busses in the system can be different lengths, use different cable types, have different

I/O response times, and operate at different baud rates. Each bus in the system is essentially indepen- dent from the others. Care must be taken to ensure that individual busses do not interfere with I/O references assigned to other Genius Bus Controllers, I/O blocks, or conventional I/O modules in the system.

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Introduction

GFK-0171

Bus Controller Location

A Bus Controller can be placed in the CPU rack or in a local I/O rack up to 2000 feet from the CPU.

Multiple Bus Controllers can be placed in one rack. Since each Bus Controller consumes 20 units of I/O power, as many as six Bus Controllers can be placed in a Series Six Plus CPU rack, or ten in a High

Capacity I/O rack.

UPTO

‘G

UPt075OOFEETIUPTO30BLOCKS

UPTO7SOOFER/UPTO3OBLOCKS

Using More than One Bus Controller on an I/O Chain or Channel

Within each I/O chain or channel, there can be more than one bus and Bus Controller, references assigned to the blocks on different busses do not overlap.

as long as

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I

Introduction

ax-017 1

Using I/O Transmitter Modules and Auxiliary I/O Modules

Depending on the I/O addressing used for the system, the Bus Controller may need to be located downstream of an Auxiliary I/O Module, and/or an I/O Transmitter Module, as explained below.

Locating the Bus Controller Downstream of an Auxiliary II0 Module

If the I/O points on a bus will be given program references in the auxiliary I/O table or in “Expanded”

I/O channels 9-F, the Bus Controller must be installed downstream of an Auxiliary I/O module.

Locating the Bus Controller Downstream of an II0 Transmitter h4odule

If the

PLC system uses Expanded (“channelized”)

I/O addressing, channel selection can be made by either the Bus Controller (phase B only) or an I/O Transmitter module. If an I/O channel has Genius I/O only, the Bus Controller can select channelization and no upstream I/O Transmitter module will be permitted.

A BUS Controller set up for channelization must not be located downstream of an I/O Transmitter

Module. It is possible to have Genius I/O blocks cozolled by a Bus Controller set up for channeliza- tion, while conventional I/O modules are also assigned to the same channel. It is important to be sure that the reference numbers assigned to the Genius blocks and I/O modules do not overlap. It is also possible to have several channelized Bus Controllers assigned to the same channel, as long as overlap- ping references are avoided.

Ideally, if a system includes both conventional I/O and Genius I/O blocks, they should not be mixed on the same channel. However, if the two I/O types must share a channel, restricting each to a predeter- mined part of that channel (for example, one half), will help prevent reference conflicts.

Channel

Bus Stream Upstream coxltroikr Main I/O

Aux I/O

Channeiized Transmitter Transmitter

9-F

o-8

or

O-8

Xl0

II0

I.lO yes* yes ** no **

Yes

no no ***

*

**

*** accommodates conventional I/O in the channel, as well as Genius I/O modules. phase

A or phase B Bus Controller

phase

B Bus Controller only

AUX lm

(CHANNEL 0)

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Introduction

GFK-0171

Locating Bus Controllers in Remote I/O Racks

A Bus Controller may also be placed in a Remote I/O rack, but this is not recommended. If the application requires great distance between the CPU and I/O blocks, it is better to use a longer bus between a Bus Controller and the I/O blocks than to place the Bus Controller in a Remote I/O rack.

The cable from the Bus Controller to its I/O blocks can be up to 7500 feet long. At maximum length, the Bus Controller supports up to 15 I/O blocks, providing up to 480 discrete references on the bus. In addition, the Bus Controller can be placed in a high-capacity Local I/O rack up to 2000 feet from the

CPU, giving a total maximum distance from the CPU to the end of the bus of 9500 feet. Such a system provides all of the diagnostics and communications features of Genius I/O.

Placing a Bus Controller in a Remote I/O rack severely limits its capabilities. The Remote I/O

rack

must be hardwired from the Remote I/O Transmitter module to the Remote I/O Receiver module (a modem cannot be used).

Communications between the Remote I/O Transmitter and Remote I/O

Receiver modules are via a serial twisted pair link of t\~o unidirectional data lines (Transmit Data and

Receive Data). This method of I/O update is slower than normal Genius I/O service. Up to 496 total

I/O references can be included in one Remote I/O station. Because of the reduced capacity of the remote I/O communications link, this type of system does not support the use of any communications commands, and is not recommended for fast-acting I/O. In addition, diagnostics may not always reach the CPU. Using Remote I/O also requires more complex logic in the application program.

Operation of Genius II0 in a Remote II0 System

With a Bus Controller in a Remote I/O rack, communications between the Remote I/O Transmitter and

Remote I/O Receiver modules must be set at 57.6 Kbaud. The I/O will be serviced each time the upstream Remote I/O Receiver module performs a partial Series Six I/O sweep. The update rate is affected by asynchronism between the Series Six I/O sweep and the transmission time required for data on the serial link between the Remote I/O Transmitter and Remote I/O Receiver modules. The Remote

I/O Receiver module scans the Bus Controller for current inputs from the Genius I/O blocks. It then transmits input data and the Bus Controller status to the Remote I/O Transmitter module via the serial link until the next programmer window occurs. On the next CPU I/O sweep, these same inputs are read from the Remote I/O Transmitter module into the Series Six Input Status Table.

If an output changes in response to an input or status bit, the earliest the new output will get from the

CPU to the Bus Controller is 1lmS after the next programmer window. See GEK-83537,

Remote II0

Modules, for a discussion of system delay times.

New output states on a given I/O sweep are not guaranteed to be picked up by the Remote I/O

Transmitter for transmission, so care must be taken to ensure that output states of short duration actually get to the output. The Remote I/O Transmitter provides a handshake bit to assist in this. Since faults that are reported for one scan may be missed by the CPU, the application program should periodically issue a Clear All Faults command to the Bus Controller.

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Introduction

GFK-017 1

Bus Controller Operation

All data transfer between the PLC and the devices on a bus is handled by the Bus Controller. The Bus

Controller interfaces two completely separate and asynchronous activities: l the Genius bus scan, a cycle of communications between the devices on a bus (this includes the Bus

Controller itself). l the CPU sweep, the cycle of actions that includes communications between the CPU and the BUS

Controller.

The Bus Controller manages data transfer between these t\~o asynchronous cycles by maintaining two separate on-board RAM memories. One interfaces with the bus and the other (referred to as “shared

RAM”) interfaces with the CPU. The Bus Controller automatically transfers data between these two memories, making data available to the bus or to the CPU when it is needed.

The Genius Bus Scan

A Genius bus scan consists of one complete rotation of a “token” among the devices on the bus.

1 (DEVICE 31) 1

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During a bus scan, the Bus Controller automatically:

PLC

t

. a4256

INPUTS INPUTS

.

1 per sweep

ouTPuTs

1 per sweep

COMMANDS

+,

DIAGNOSTICS

AutomaticalIy, one per sweep (max

)

BUS

CONTROLLER

Automatically, each bus scan

,

OUTPUTS

P

I

-----

Storage t

1

To selected blocks

DlAGiNOSTlCS

I( maximum

Automatically, one per scan

( max )

L -B-w-

COMMANDS

m

I/O

+

BLOCK

1persweepmw

via output table +l per window p A

On CPU logic command

Limit: 1 Datagram per scan

Introduction

GFK-0171

Receives and stores all inputs from the I/O blocks on the bus.

. .

r

Updates outputs, as permitted, on the I/O blocks. With a phase B Bus Controller, transmission or outputs from the CPU can be disabled for one or more blocks on the bus. For all systems, this feature can be used to initialize outputs at startup. For advanced systems with distributed control of outputs, or computer monitoring

of I/O block data, outputs can be disabled to individual blocks. Both phase A and phase B Bus Controllers can disable output updates as described in chapter 5.

A BUS Controller with Diagnostics receives any fault messages issued by devices on the bus, and stores up to 60 in an on-board fault table. The Series Six Plus PLC can be set up to provide its own internal fault table for storage of diagnostic messages, and can access these diagnostic messages automatically. In addition, ladder logic can be added to the program of any Series Six CPU to access diagnostic messages.

Sends any command received from the CPU (for example, Clear Circuit Fault) to the appropriate device.

Bus Scan Time

The amount of time required for one complete rotation of the token to all devices will depend on the baud rate, the number and types of blocks, the number of bus interface modules (Bus Controllers and

PCIMs), and the occurrence of optional Global Data and of programmed messages on that bus.

Bus scan time directly affects: l the response time for servicing I/O on the bus. l the time required for programmed communications to be transmitted on the bus. l the relationship between the bus scan and the CPU sweep time. Because CPU sweep time is probably less flexible, it may be necessary to change I/O block distribution or programmed communications to create a balance.

The Genius II0 System User’s Manual explains bus scan time in detail.

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Introduction

GFK-017 1

The CPU Sweep

The CPU

sweep is the PLC’s regular cycle of operations. During each sweep, the CPU updates inputs and outputs, executes the application program, and communicates with other devices. The CPU sweep is executed independently of the Genius bus scan.

During one CPU sweep, the Bus Controller:

Transfers all discrete inputs and one channel input value (16 bits) per analog (or RTD) block from shared RAM. memory to the CPU Input Status Table.

To update all the inputs on an analog block during a single CPU sweep, the command Read Analog Inputs can be added to the ladder logic program.

Receives current outputs and new commands from the CPU Output Status Table and places them in shared W.

Reports its status and that of the serial bus. A Bus Controller with Diagnostics also reports the status of the I/O blocks and provides one new diagnostic (if any) to the CPU. Diagnostics data is moved to the Input Table, starting at the address set with the backplane DIP switches.

May communicate with the CPU in response to window instructions in the application program. If the program directs DPREQ or WINDOW instructions to a Bus Controller, a communications window to that Bus Controller opens during the ladder logic portion of the sweep. The Bus Controller may also receive messages Tom other devices on the bus. These messages will be returned to the

CPU when the program opens a communications window to the Bus Controller.

CPU SWEEP

.

L

UPDATE

INPUTS

I

LADDER

LOGIC

*

SEND

OUTPUTS

BUS CONTROLLER

a43044

BUS

TOKEN

IN

INPUTS

AND

DIAGNOSTICS

I

-1

i MESSAGES 1

1 I

OUTPUTS

AND

COMMANDS

<=7

BUS

TOKEN

OUT

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l-10

Introduction

GFK-0171

Completing the Interface

The

rest of this

book explains how to install a Bus Controller and describes

programmable features. The tables on the following pages will help

you locate the information you need for: l

Setting up a

Bus

Controller.

l

Setting up the

PLC system. l

Programming for analog I/O. l

Progr amming for diagnostics and fault clearing. l

Prog?ammin g for communications between CPUs.

Each topic is explained in more detail later in the book.

Setting up a Bus Controller

Each Bus Controller in the

system, and the I/O blocks on the bus, must be configured.

FEATURE HOW TO DO IT

Prevent program from sending unwanted outputs Set DIP switch 4 at position U16. to blocks following powerup of the Bus Control- ler.

Indicate whether failure of the Bus Controller’s Use switch 1 at position U3. self test should stop the CPU.

Match the Bus Controller’s baud rate to the other Use switches 2 and 3 at position U3. devices on the bus.

Select a Device Number for the Bus Controller. Use switches 4 through 8 at position U3.

Set up Bus Controller for Expanded I/O scan- Use switches 1-3 at position U59. ning, and select channel.

Select terminating impedance for the Bus Con- For single bus cable, use jumper on Bus Control- troller ler. For redundant cable, use resistor.

Select the Bus Controller reference number. Set backplane DIP switches

Automatic I/O update. Assign I/O (not register) reference numbers to

I/O blocks.

DESCRIBED

IN CHAPTER

2

2

2

2

2

2

2

3

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Introduction l-11

GFK-017 1

Setting up the

PLC

System

The Logicmaster

6

programmin g software

(LM6) is

used to set up Expanded I/O scanning, and the use of automatic Genius I/O diagnostics for the entire PLC system. specify

FEATURE

HOW TO DO IT

Enable/disable Expanded functions.

Enter CPU Configuration instruction as first rung in ladder.

Enable/disable automatic diagnostics.

Enable/disable Expanded I/O scan.

Use LM6 Expanded Functions menu.

Use LM6 Expanded Functions menu.

Specify channel pairs for I/O scanning.

Use LM6 Expanded Functions menu.

Specify channel pairs for diagnostics.

Use LM6 Expanded Functions menu.

Select length of the fault table for automatic

Use LM6 Expanded Functions menu. diagnostics. Default is 8 uncleared faults for system.

Specify locations of Bus Controllers that will

Make selection on LM6 Expanded Functions report diagnostics. menu.

Create internal status table for all I/O points witi

Select Y for “Diagnostic Tables” on LM6 Ex- diagnostics. panded Functions menu.

Assign Bus Controller on 256 bit reference boundaries.

DESCRIBED

IN CHAPTER

4

4

4

4

4

4

4

4

2

Programming for Analog I/O

If there will be analog I/O blocks on a bus, logic must be added to the program to store input values for each analog block. If there are more than 5 analog blocks on the bus, additional logic must be used to assure that all inputs are received by the CPU,

FEATURE

HOW TO DO IT

Copy multiplexed analog inputs fkom block’s in-

Use program logic to read one input per sweep put references. into registers.

Read all inputs fkom an analog block during the

Program Read Analog Inputs command using same CPU sweep.

DPREQ or WINDOW instruction.

Store inputs from moTe than 5 analog blocks on

Program Read Analog Inputs command using the same bus.

DPREQ or WINDOW instruction.

DESCRIBED

IN CHAPTER

3

5

5

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l-12

Introduction

GFK-0171

Additional Programming Capabilities

The

program may also include logic to do the following:

FEATURE

HOW TO DO IT

Pulse Test discrete outputs from program.

Set Bus Controller output reference bit 4.

Read or write configuration data for the Bus

Use DPREQ or WINDOW instruction with a

Controler or a block.

Read or Write Configuration command.

Read the I/O type assignment of any point on the Use DPREQ or WINDOW instruction with a bus .

Read Configuration command to the Bus Con- troller.

Determine whether outputs are disabled to a de- Use DPREQ or WINDOW instruction with a vice on the bus. Read Configuration command to the Bus Con- troller.

Determine error rate on bus, or bus scan time.

Use DPREQ or WINDOW instruction with a

Read Diagnostics command to the Bus Control- ler.

Determine the current fault status of the Bus Use DPREQ or WINDOW instruction with a

Controller or a block.

Read Diagnostics command.

Read the

Status

Table reference of the Bus Con- Use DPREQ or WINDOW instruction with Read troller or a block.

Status Table command.

DESCRIBED

IN CHAPTER

9

5

5

5

5

5

5

Programming for Diagnostics and Fault Clearing

Program logic can be used in addition to, or instead

of, automatic diagnostics to access specific types of information and to send commands to I/O blocks on the bus.

FEATURE HOW TO DO IT

Detect failure of Bus Controller self-test.

Detect bus error condition.

Detect I/O circuit faults.

Detect addition or loss of block.

Monitor Bus Controller input reference bit 1.

Monitor Bus Controller input reference bit 2.

Monitor Bus Controller input reference bit 3.

Monitor Bus Controller input reference bits 4 and 5.

Detect duplicate or overlapping reference num- Monitor Bus Controller input 5 reference bit 6. bers.

Detect execution of a Pulse Test. gram*

Monitor Bus Controller input reference bit 7.

Detect force condition on the bus.

Monitor Bus Controller input reference bit 8.

Create register table to store faults.

See example logic in chapter 5.

Clear all faults on a bus fkom program.

Set Bus Controller output reference bit 2.

Clear fault(s) on a specific circuit fkom the pro-

Set Bus Controller output reference bit 3, use additional references to specify circuit.

DESCRIBED

IN CHAPTER

8

8

8

8

8

8

8

8

9

9

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Introduction

143

ax-017 1

Programming for a Bus with Redundant Interface Modules

If the bus will interface additional Bus Controller or PCIM modules, program logic may be needed for

CPU redundancy, distributed control, or an assigned monitor:

FEATURE HOW TO DO IT

Prevent the Bus Controller from sending outputs Program Write Configuration command to Bus- to one or more devices. Controller using DPREQ or WINDOW instruc- tion,

Disable all outputs from a Bus Controller used Set Bus Controller output reference bit 1. as a monitor.

Set up blocks to issue extra fault reports and

Use DPREQ or WINDOW instruction Assign configuration change messages to an assigned

Monitor Datagram. monitor.

Switch a Bus Switching Module to a specified

Use DPREQ or WINDOW instruction with bus . Switch BSM command.

DESCRIBED

IN CHAPTER

5

9

5

5

Programming for Communication between CPUs:

If the Series Six PLC will send or receive Datagram or Global Data messages on a bus with other Bus

Controllers or PClMs, additional program logic will be needed.

FEATURE HOW TO DO IT

Read or write Global Data address, Global Data

Use DPREQ or WINDOW instruction with a length. Read or Write Configuration command to the

Bus Controller.

Read the Global Data address of another inter-

Use DPREQ or WlNDOW instruction with Read face module on the bus.

Handling

Status Table command.

Global Data: transfer up to 128 bytes Use DPREQ or WINDOW instruction to send of data between CPUs using Global Data, Write Configuration command to Bus Control- ler.

Use Idle DPREQ or WINDOW instruction to transfer Global Data to/from the Series Six CPU.

Send up to 128 bytes of data to a Bus Controller Use DPREQ or WINDOW instruction to send or PClM as a Datagram. Write Device Datagram.

Read up to 128 bytes of data from another CPU Use DPREQ or WINDOW instruction to send on the bus as a Datagram. Read Device Datagram.

In the other CPU, use logic to open communica- tion between the CPU and its bus interface mod- ule,

Set or clear up to 16 individual data bits in Use DPREQ or WINDOW instruction to send another CPU. Write Point Datagmm.

DESCRIBED

IN CHAPTER

5. 7

5

5, 7

7

6

6

6

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Chapter

2

Setup and Installation

GFK-017 1

Before a Bus Controller is installed, its on-board and backplane DIP switches can be set to select the features described below. The board is shipped from the factory with default settings. A discussion of

IMPEDANCE b b

U16

(SWITCHES 4 - 8)

DISABLE ouTPuts

Terminating impedance for the communications

bus. If the Bus Controller is not at the end of the bus, do not change the default switch setting.

CPU shutdown mode. If program execution should continue in the event of Bus Controller failure, do not change this.

Baud rate. The default setting is 153.6 Kbaud. The Bus Controller’s baud rate must match that of the other devices on the bus. Selection of a baud rate is based on cable length and type, and the use of phase A devices on the bus.

Device Number. The default Device Number is 31. Unless there is another bus interface module on the same bus, this number need not be changed.

Expanded I/O addressing.

If the PLC system uses Normal I/O addressing, or if the Bus Controller will be installed downstream of an I/O Transmitter module that will select Expanded I/O addressing, do not change the default setting.

Outputs disabled or enabled when

Bus Controller powers up.

By default, outputs are automati- cally transmitted to the blocks when the Bus Controller powers up with the PLC in the Run/Enable mode. This can be changed to disable outputs at powerup. The program can subsequently enable these outputs.

Refer to the descriptions that follow to determine whether the defaults should be changed. A sample configuration worksheet form is provided at the end of this chapter. A copy of this worksheet can be used to record the configuration of the Bus Controller,

In addition to the on-board switch settings, a Reference Number for the Bus Controller is selected using

DIP switches on the rack backplane.

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Setup and Installation

GFK-0171

Selecting Terminating Impedance

Each Genius communications bus must be terminated at both ends by its characteristic irmedance. A jumper on the Bus Controller is used to select impedance.

III!3

The jumper across JP7 selects no impedance.

150n loon

75 n.

I 2

l o

.a a.

H

1 2

Jp3

JP2

JPl

lo

1 2

JP7

a421 91

This position is correct if

the Bus

Connoller

is not physically installed at the end

of

the

bus. If the

Bus

Controller is at either end of the bus, move the jumper to select 7X2, 1OOQ or 15OsZ terminating impedance. The

Genius II0 Svstem User’s

A4amal explains correct teminating impedance and baud rate for different cable types &d lengths.

Terminating Impedance on a Redundant Bus

A bus that uses two Bus Controllers for redundancy on the same bus requires special planning for termination. If either Bus Controller will be located at the end of such a redundant bus, do not select terminating impedance using the on-board jumper. Instead, install a resistor of correct impedance across the Serial 1 and Serial 2 terminals on the Bus Controller’s faceplate. This will make it possible to keep the bus properly terminated and in operation should removal of the Bus Controller ever be necessary.

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Setup and Installation

GFlL017 1

SWITCH

CPU

Shutdown

1

Baud

Rate

2

3

SETTING

Continue CPU sweep

2% stop CPU sweep

-

153.6 standard x

X

76.8

X

I)

38.4

-

X

153.6 extended

-

-

Device

Nllllber

4

5

6

7

8

X= open/off.

1111111111222222222233

01234567890123456789012345678901

-~~~~~~~~~~~~~~~

-I~~~~L~~I~~~~~mm~~

1.mD~~~I~~~~I.~-~~~~~~

~~~~~~~~~~~~~~~-~xy,_~~I~~

-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x--x

Default is all open.

1

a42190

Enabling CPU Shutdown Mode

Switch 1 of the DIP switch pack at position U3 determines whether Bus Controller failure will stop the

CPU sweep. The default selection is for the CPU sweep to continue. If the CPU sweep should stop because one of the Bus Controllers has failed its self-test, then the program must be able to detect the failure. If the Expanded Functions are enabled (this requires Logicmaster 6 software release 3.0 or later), the CPU will continually check for Bus Controller failure. If an earlier software version is used, the ladder logic program must check for a Bus Controller failure by resetting the Bus Controller OK

Status Bit every CPU sweep. For more information about this status bit, see chapter 5.

Setting the Baud Rate

All devices on a bus (including the Bus Controller and the Hand-held Monitor) must be set up to use the same baud rate. (Other busses connected to the PLC may operate at different baud rates, however). The default baud rate selected for a new Bus Controller is 153.6 Kbaud (standard). This default is provided so that the Bus Controller is compatible with phase A devices.

However, 153.6 Kbaud extended will provide better performance.

Depending on the length of the bus and other factors, it may be desirable or necessary to change this to 153.6 Kbaud extended, 76.8 Kbaud. or 38.4 Kbaud using switches 2 and 3 at position U3. The

Genius I/O System User’s Ahzud gives guidelines for baud rate selection.

Changing the Bus Controller Device Number

Each device on the bus must have a bus address, which is referred to as its Device Number. For a new

Bus Controller, the Device Number 31 is selected by default.

If

there is just one Bus Controller on the

bus, no change is needed. If there will be more than one bus interface module (Bus Controller or PCIM) on the samebus, it is necessary to assign each a different Device Number. Switches 4 through 8 at position U3 select a Device Number. A Bus Controller may use any available Device Number except in

CPU Redundancy mode. In Redundancy mode, the blocks require Bus Controllers at Device Numbers

30 and 31.

Selecting Expanded I/O Addressing

The DIP switches at position U59 select the type of I/O addressing used by the Bus Controller. Do not change the default switch settings if the system uses Normal I/O addressing, or if the Bus Controller will be installed downstream of an I/O Transmitter module which will be selecting an Expanded I/O channel.

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Setup and Installation

GFK-0171

If the system uses Expanded I/O addressing with the channel selected by the Bus Controller, use the switches at position U59 to select Expanded I/O addressing and specify the channel number.

842102

SWITCH

,

SETTING

01234567

Aux9ABCDEF

1

2

3

-X-X-X-X

--xx--xx

--'-xXxX

- X-X=-X-X

- -xx--xx

- ---xxxx

4 set 4 to open for Expanded I/O

I

X’

open/off.

Default is all closed.

J

The Bus Controller must be installed downstream of an Auxiliary II0 Module to address the Auxiliary

II0 chain or Expanded II0 channels 9 through F.

A phase A Bus Controller cannot be used for channel selection, and must be installed downstream of an

I/O Transmitter module in an Expanded I/O system.

Logicmaster

6

Version Number

It is important to know which version of Logicmaster 6 software is being used, because that determines which Expanded I/O channels the CPU scans by default.

Logicmaster 6 software version

4 and later defaults to scanning channels 0 and 8, which correspond to the Main and Auxiliary I/O chains. For Logicmaster 6 version

3.0, the software defaults to the first 4 channels enabled (channels O-3).

The setup of the Bus Controllers must match the channels scanned by the CPU. As an example, suppose the system has one Bus Controller and that it has been installed without changing its DIP switch settings.

That means it is not set up for Expanded addressing. Subsequently, the system is powered up using

Logicmaster 6 software version

3. This software defaults to Expanded I/O Enabled, and scans channels

O-3. Because the Bus Controller has not selected a particular channel, it receives outputs on successive

CPU sweeps as though they were intended for Bus Controllers set up for channels 0, 1, 2, and 3. That means it receives constantly-changing output data from the CPU. To avoid this problem, the application program and the Bus Controller setup must match.

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Setup and Installation

GFK-017 1

Disabling Outputs

The BUS

Controller can be used to disable outputs from the CPU to the blocks.

Disabling

outputs means preventing the transmission of output information to the block(s) from the CPU

(this is determined at the Bus Controller). Disabling outputs is not the same as defaulting outputs.

Defaulting

outputs means automatically setting outputs to a predetermined state if the block ceases to receive CPU communications for 3 bus scans. When to default outputs is determined by the I/O blocks.

If program action causes the CPU to disable outputs while the system is in operation,

any

blocks that stop receiving outputs

as

a result will default their outputs to the appropriate predetermined state. The blocks will also default outputs if CPU communications are lost for any other reason, such as a broken cable.

Can DISABLE blocks and other bus devices

Can DEFAULT outputs to predetermined state if outputs from CPU cease

How Outputs can be Enabled or Disabled

There are three

different ways to disable (or enable) outputs:

First:

second:

Third:

All outputs on a bus can be disabled (or enabled) at powerup by setting a DIP switch at position U16.

This is explained on the next page.

All outputs from the Bus Controller can be disabled and enabled together during system operation.

This might be done in a system with two or more

CPUs on the same bus, where one was used only for data monitoring.

Outputs can be enabled or disabled during system operation on a block-by-block basis by setting and clearing individual Disable Outputs bits. This might be done in a system where two or more CPUs were used for selected control of blocks on the same bus.

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2-6

Setup and Installation

GFK-0171

Disabling Outputs at Powerup

Under certain conditions, it is possible that the Bus Controller may begin transmitting output data before the CPU program has set up the desired output values. Setting a Bus Controller DIP switch (see below) prevents possibly incorrect operation of outputs at powerup. This requires the use of program logic to enable the outputs after correct system operation is assured. To do this:

1. Set Bus Controller DIP switch 4 at position powered up.

U16 to disable outputs when the Bus Controller is

a42103

SWITCH1

SETTING

1-3

4

(Disable Outputs

X

I

Enable_Outputs

I

not used

-

I x = open/off

I

I

2. At a subsequent time, determined as suitable by the application, enable outputs to some or all of the blocks under control of the program.

If switch 4 is open, the Bus Controller will hold off output transmissions until it completes its powerup sequence. If the PLC is stopped because the Bus Controller has powered down (which is typical), it must execute two sweeps in Run Disabled mode. While the PLC is in Run Disabled mode, the

BUS

Controller will continue to withhold output transmissions.

These two sweeps typically permit the

BUS

Controller to be updated with correct outputs for the blocks. However, this does depend on the relative lengths of the PLC sweeps and the Genius bus scans. Switch 4 only determines what happens after the

Bus Controller is powered up. It has no effect if the Bus Controller is in a rack that is powered up and the PLC is powered up later.

Thus, if switch 4 is closed, the Bus Controller will update outputs as soon as its powerup sequence is completed, or as soon as the CPU goes into Run/Enabled mode, whichever is later. With switch 4 open, the onset of output updating is determined by program logic in the PLC.

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Setup and Installation

GFK-017 1

Bus Controller Reference Number

Each Bus Controller in the Series Six PLC system must be assigned a Reference Number by setting the

DIP switches on the rack backplane.

TYPICAL

DIP

The Reference Number assigned to each Bus Controller is a beginning address in the I/O Table where the Bus Controller’s input and output data will be located. This data includes diagnostics and command information.

Be sure each Bus Controller on an I/O chain has a unique Reference Number. Also be sure no Bus

Controller on the Main I/O Chain has the same Reference Number as a Bus Controller on the Auxiliary

I/O Chain. References used by Bus Controllers must not overlap with those of any Genius I/O blocks or of any conventional I/O modules.

References Required (8): Bus Controller without Diagnostics

Assign Reference Numbers for a Bus Controller without Diagnostics on a byte boundary (9, 17, 25 ..$

This type uses 8 references (both inputs and outputs).

-

References Required (48): Bus Controller with Diagnostics

Reference Numbers for Bus Controllers with Diagnostics must be assigned

(unless Diagnostic Tables are enabled as explained below). Because the

BUS first

48 references, the final 16 references in each 64rreference block can be on 64.point boundaries

Controller uses only the assigned for general I/O use.

For some Series Six Plus PLC applications, register memory can be used to store the current diagnostic status of all I/O points on the bus. If DIAGNOSTIC TABLES is selected on the Logicmaster 6 software

CPU Configuration Setup Menu, Bus Controller Reference Numbers must be assigned on 256.reference

(not 64-reference) boundaries. The Bus Controller will use the first 48 references for diagnostics, and will place the current diagnostic status of all I/O points on the bus in the remaining 208 references.

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Setup and Installation

GFK-0171

Bus Controller

Configuration Worksheet

Bus Controller Type:

Bus Controller with diagnostics (IC66OCBB902)

Bus Controller without diagnostics (IC660CBB9Or’

Description/General Information:

.

Location to install this board:

Before installing the board, configure it using the DIP switches and jumpers.

Position U3

:

Switch 1 = CPU Shutdown Mode: continue (default)/ stop .

.

Switches 2 and 3 = Baud Rate: 153.6 Kb standard (default), 153.6 Kb extended, 76.8 Kb,

38.4 Kb

.

Switches

4 through 8 = Device Number: O-31 (default is 31)

Position 59:

Switches 1 through 3 = I/O channel:

Main I/O Chain: channel 0 (default) through 7

.

.

Auxiliary I/O Chain (must be downstream of Auxiliary I/O Module):

Aux I/O table (default) through channel F

.

Switch 4 = Expanded I/O Addressing: no (default)/yes

If yes, enter channel number

.

Position

U16:

Switch

4 = Disable Outputs at powerup: yes (default)/no

Switches 1 through 3 must be OPEN

.

.

Select the terminating impedance using the on-board jumper:

JP7 = none (default)

JPl = 7X2

.

JP2 = lOOs2

.

JP3 = 15OQ

.

Select the Reference Number using the backplane DIP switches:

Reference Number (1 - 993)

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Chapter

3

Interfacing Genius I/O Blocks to the Series Six PLC

GFK-017 1

Each Genius I/O block in a Series Six PLC system must be assigned a Reference Number when the block is configured, using a Hand-held Monitor. The Reference Number is the address in PLC memory reserved for use by the block’s inputs and outputs. This chapter explains:

Assigning Reference Numbers in I/O or Register Memory.

Analog block input and output data formats.

Required programming for analog inputs.

Required programmin g for analog blocks, High-speed Counter Blocks, and PowerTRAC Modules in

I/O memory.

Assigning Reference Numbers in I/O or Register Memory

When a block is configured, either an I/O reference or register reference can be assigned as its Reference

Number. For most applications, I/O blocks should be assigned Reference Numbers in I/O memory.

However, a block might be assigned a register reference to conserve I/O references or to permit more devices to be used on the same bus. When register references are used, allow enough to accommodate both the input data and the output data. Inputs are stored before outputs, and the input data and output data must each begin on a register boundary. For example, if a block with 8 inputs and 8 outputs were assigned to register memory, two registers would be required (one for the inputs and one for the outputs). If the beginning address assigned to the block was R0129, the input data would be occupy the first 8 bits of R0129 and the output data would occupy the first 8 bits of RO130.

When the following blocks are assigned to I/O memory, they may require some special ladder logic to avoid premature access to data in the input table while the Bus Controller is still updating that input data: 4 Input/2 Output Analog Blocks, Current-source Analog Blocks, RTD Input Blocks, Thermocou- ple Blocks, PowerTlUC Blocks. See page 3-9 for more information.

Programming Required for Blocks Assigned to Register Memory

Automatic diagnostics and automatic II0 update are not per$ormed on blocks assigned

to register

references. References in register memory are NOT updated during the I/O scan portion of the sweep.

A window must be opened (using a DPREQ or

WINDOW instruction at the beginning of the sweep), to update I/O points assigned to register memory. An “idle” DPREQ or WINDOW instruction

can

be used. To obtain fault reports from a block assigned to register memory, a Read Diagnostics Datagram must be sent to the block using the Send Datagram command.

The Read Configuration, Write Configuration, Read Diagnostics, and Read Analog Inputs

commands

cannot be send to a block that is assigned a register Reference Number. These functions must be done using Datagrams.

_

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Interfacing Genius I/O Blocks to the Series Six PLC

GFK-017 1

Assigning Reference Numbers in I/O Memory

Reference Numbers can be selected from any available references in a chain (or channel in an Expanded

I/O system). Each Reference Number must begin on an even byte boundary. A byte boundary is a number that alwavs leaves a remainder of 1 when divided by 8 (1, 9, 17 ..J. The references used by each device go up in sequence multiples of 8 references).

(0001,

0002, 0003 . ..)

to the maximum required by the device (always

In an Expanded I/O system, it will probably be most convenient to assign the first references in each channel to the Bus Controller, then assign the I/O blocks to references beginning at 49.

Avoiding Reference Number Conflicts

References assigned to any Genius block must not conflict with or overlap references assigned to other devices anywhere else in the PLC system. This includes other blocks on the same or any other bus, other Bus Controllers, or conventional I/O modules.

In an Expanded I/O system, if multiple Bus Controllers on the same bus are installed directly in the CPU rack and any references assigned to blocks on that bus overlap, a bus fault message will be generated.

However, if the Bus Controllers are on different busses there will be a bus conflict resulting in erroneous

I/O data for the overlapping references.

This problem may be difficult to detect when the system is operating.

If multiple Bus Controllers are installed downstream of an I/O Transmitter module and any references assigned to the I/O blocks on those Bus Controllers overlap, a system parity error may result, and the system may shut down.

I/O References Used by a Block

4 Input/2 Output analog blocks and RTD Input blocks use 24 references in the input table. 4 Input/2

Output analog blocks also use 32 references in the output table. Analog block data format is shown later in this chapter.

The references needed for a discrete block depend on the number of circuits it has, and whether it has all inputs, all outputs, or both. Point 1 on a discrete block occupies the lowest-numbered reference assigned

(which is also the block’s beginning address).

All-inputs discrete blocks, or I/O blocks configured as inputs-only blocks, need one reference in the input table for each circuit on the block.

All-outputs blocks, or blocks configured as outputs-only blocks use references in the output table only.

Discrete blocks with both inputs and outputs will use references in both the Input and Output Tables, beginning at the configured Reference Number. This includes bms configured as combination blocks, even if

the II0 circuits on the block are set

up

as all inputs or all outputs.

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Interfacing Genius I/O Blocks to the Series Six

PLC

GFK-017 1

The

following example shows a non-Expanded I/O system with two Bus Controllers on the same I/O chain.

The

first

Bus Controller is assigned to references 1 through 48. Block 1 on bus 1 is a discrete 8-circuit block with inputs only.

It is assigned to Reference Number 0049, reserving

8 input references

(10049-10056).

Because the block is configured for inputs only,outputs 00049-00056 are not reserved; they can be used by other blocks.

On the same bus, block 2 is a discrete 16.circuit block configured to use outputs only. Reference

Number 0049

can also

be assigned to that block. The block will use 16 references (00049-00064) in the output table.

Depending on the actual I/O mix, some input or output references will not be used for physical devices.

References not used by I/O on a block (such as inputs 10057-10064 in this example) are not available for use by other physical I/O. However, they can be used for logical coils in the progrc

Block 3 on the same bus is a discrete 8-circuit block that uses 5 inputs and 3 outputs. Reference

Number 0065 is assigned to the block. Because it is a combination block, it needs equivalent references in both the input table (10065-10072) and the output table (00065-00072). However, only 5 input references and 3 output references will actually correspond to field devices. The remaining three inputs will contain feedback data from the output circuits and cannot be used for internal program logic.

Block 4 on bus 1 is an input block assigned to 10073-10080. To allow for the addition of blocks to both busses in the future, the second Bus Controller is assigned to I/O references 513-560. The blocks on bus

2 are assigned I/O references from 561 to 993.

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Interfacing Genius I/O Blocks to the Series Six PLC

GFK-0171

First and Last I/O Table References

Reference ranges for blocks with 8, 16, 24, or 32 circuits are listed below.

References Number assignments can be recorded on copies of the Configuration Worksheet on the next page.

F&

Last Reference

Reference 8 16

24 32

008 016 024 032

016 024 032 040

024 032 040 048

032 040 048 056

040 048 056 064

048 056 064 072

056 064 072 080

064 072 080 088

072 080 088 0%

080 088 096 104

088 0% 104 112

0% 104 112 120

104 112 120 128

112 120 128 136

120 128 136 144

128 136 144 152

136 144 152 160

144 152 160 168

152 160 168 176

160 168 176 184

168 176 184 192

176 184 192 200

184 192 200 208

192 200 208 216

200 208 216 224

208 216 224 232

216 224 232 240

224 232 240 248

232 240 248 256

240 248 256 2&i

248 256 264 272

256 264 272 280

264 272 280 288

272 280 288 296

280 288 296 304

288 296 304 312

296 304 312 320

304 312 320 328

312 320 328 336

320 328 336 344

328 336 344 352

336 344 352 360

001 \

009

017

025

033

041

049

057

065

073

081

089

097

105

113

121

289

297

305

313

321

249

257

265

273

281

329

193

201

209

217

225

233

241

129

137

145

153

161

169

177

185

First

Reference 8

Last Reference

16 24 32

489

497

505

513

521

529

537

545

409

417

425

433

441

449

457

465

473

481

617

625

633

641

649

657

665

553

561

569

577

585

593

601

609

337

345

353

361

369

377

385

393

401

344 352 360 368

352 360 368 376

360 368 376 384

368 376 384 392

376 384 392 400

384 392 400 408

392 400 408 416

400 408 416 424

408 416 424 432

416 424 432 440

424 432 440 448

432 440 448 456

440 448 456 464

448 456 464 472

456 464 472 480

464 472 480 488

472 480 488 4%

480 488 496 504

488 496 504 512

4% 504 512 520

504 512 520 528

512 520 528 536

520 528 536 544

528 536 544 552

536 544 552 560

544 552 560 568

552 560 568 576

560 568 576 584

568 576 584 592

576 584 592 600

584 592 600 608

592 600 608 616

600 608 616 624

608 616 624 632

616 624 632 640

624 632 640 648

632 640 648 656

640 648 656 664

648 656 664 672

656 664 672 680

664 672 680 688

672 680 688 6%

Fmt

Last Reference

Reference 8

16

24 32

680 688 6% 704

688 6% 704 712

6% 704 712 720

704 712 720 728

712 720 728 736

720 728 736 744

728 736 744 752

736 744 752 760

744 752 760 768

752 760 768 776

760 768 776 784

768 776 784 792

776 784 792 800

784 792 800 808

792 800 808 816

800 808 816 824

808 816 824 832

816 824 832 840

824 832 840 848

832 840 848 856

840 848 856 864

848 856 864 872

856 864 872 880

864 872 880 888

872 880 888 896

880 888 8% 904

888 896 904 912

896 904 912 920

904 912 920 928

912 920 928 936

920 928 936 944

928 936 944 952

936 944 952 960

944 952 960 968

952 960 968 976

960 968 976 984

968 976 984 992

976 984 992 1000

984 992 1000 xxx

992 1000 xxx xxx

1000 xxx xxx xxx

809

817

825

833

841

849

857

865

745

753

761

769

777

785

793

801

673

681

689

697

705

713

721

729

737

937

945

953

961

969

977

985

993

873

881

889

897

905

913

921

929

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Interfacing Genius I/O Blocks to the Series Six PLC

GFK-017 1

II0 Reference Number Assignment

Configuration Worksheet

Main I/O Chain (corresponds to channel 0)

Auxiliary I/O Chain (corresponds to channelTO

Expanded I/O Channel Number (1-7, 9-F)

Channelization provided by Bus Controller(Y/N)

.

.

3-5

Ref. Start: 001 009 017 025 033 041 049 057 065 073 081 089 097 105 113 121 129 137 145 153 161

End:

008 016 024 032 040 048 056 064 072 080 099 096 104 112 120 128 136 144 152 160 168

\ ,

USED

OUTPUTS

USED

I

1

Ref. Start: 169 177 185 193 201 209 217 225 233 241 249 257 265 273 281 289 297 305 313 321 329

End:

176 184 192 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336

*

USED

OUTPUTS

USED

I

Ref. Start: 337 345 353 361 369 377 385 393 401 409 417 425 433 441 449 457 465 473 481 489 497

End: 344 352 360 368 376 384 392 400 408 416 424 432 440 448 456 464 472 480 488 496 504

\

I

USED

.

OUTPUTS

USED b

Ref. Start: 505 513 521 529 537 545 553 561 569 577 585 593 601 609 617 625 633 641 649 657 665

End= 512 520 528 536 544 552 560 568 576 584 592 600 608 616 624 632 640 648 656 664 672

USED

OUTPUTS

USED r t

A

Ref. Start: 673 681 689 697 705 713 721 729 737 745 753 761 769 777 785 793 801 809 817 825 833

End: 680 688 696 704 712 720 728 736 744 752 760 768 776 784 792 800 808 816 824 832 840

3

USED

OUTPUTS

USED

Ref. Start: 841 849 857 865 973 881 889 897 905 913 921 929 937 945 953 961 969 977 985 993

End:

848 856 864 872 880 888 896 904 912 920 928 936 944 952 960 968 976 984 992 1000 t

,

USED

OUTPUTS

USED

4

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Interfacing Genius I/O Blocks to the Series Six PLC

GFK-0171

Analog Input and Output Data

An analog block (of any type, such as a 4 Input/2 Output Analog block, or an RTD block) uses

24

references in the input table. A 4 Input/2 Output Analog block also uses 32 references in the output table. Analog input data is multiplexed into the input table references, so that data from

only

one of the circuits on the block is presented each sweep. The next input circuit is presented during the following sweep. The number of sweeps required is the same as the number of input circuits on the block.

Analog Output Data

Analog

blocks with 4 inputs and 2 outputs use 32 output references for the two circuits.

32 17 16

1 lsb'msb I& output

2

output 1

Unlike input data (described below), output data is not multiplexed. Data for output 1 is stored in

(relative) references 1-16. Data for output 2 is stored in (relative) references 17-32. Their data formats are identical and are in two’s complement format.

They represent a scaled engineering units value.

Refer to

the Genius

II0 System Uses’s h4anuaZ for information about scaling analog data.

Analog Input Data

During each Genius I/O bus scan, analog blocks send data from all of their input circuits to the Bus

Controller and the Hand-held Monitor. During the CPU sweep, the CPU reads from the Bus Controller the value of one analog circuit per block. This analog value is placed in the block’s input references as shown below.

24 19

I ,T

(0)

not used

- -

Circuit number

(O-3 or O-5)

I

Circuit data

-

References 1-16 store the circuit data. The content of these bits depends on whether the

input is

configured for Normal Input Mode or Alarm Input Mode. (Alarm Input Mode, which is a feature of the

4 Input/2 Output Analog block only, replaces actual circuit data with alarm data).

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Interfacing Genius I/O Blocks to the Series Six PLC

GFK-017 1

In Normal Input Mode, bits 1-16 store the two’s complement engineering units value of a circuit. Bit 1 is the LSB and bit 16 is the MSB.

I_

Engineering units for the circuit indicated

Circuit Number

In Alarm Input Mode, bits 1-2 store the Alarm Input mode data for the circuit. Bit 1 = 1 indicates that the current input value exceeds the programmed Low Alarm limit. Bit 2 = 1 indicates that the current input value exceeds the programmed High Alarm limit. If both bits = 0, no alarm limits have been exceeded.

I

24

Circuit Number

16

w-

’ ’ 1

-

1

zero

High alarm = 1

--

1

Low alarm = 1

Relative references (bits) 17-19 store a number that identifies the circuit on the block. The circuit number is a binary value ranging from 0 (which represents input circuit #I) to 5, depending on the number of inputs on the analog block.

The value remains in the CPU’s input table for only one

CPU sweep. On the next sweep, it is replaced by the value of the next analog input on the block, and the circuit number is changed accordingly.

Programming for Analog Inputs

The input circuit number and circuit value from one analog input per block are automatically placed in the block’s assigned input references each CPU sweep. No ladder logic is required to move the value into the references, although ladder logic is needed to capture this value and place it into a register. This is explained on the next page. DO I/O instructions do not obtain data that is any “fresher” than the data already available, and therefore should not be used for analog inputs.

If faster update of analog inputs is desired, ladder logic can be used to read all of a block’s analog inputs directly into registers in a single CPU sweep.

For information, see the description of Read Analog

Inputs in chapter 5.

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Const

+[ BIT CLEAR

00001

IO257

MATRIX

BUS

CONTRLR

OK

Const

LEN]-

001

Interfacing Genius I/O Blocks to the Series Six PLC

GFK-0171

Transferring Analog Inputs to CPU Registers

Because each analog input value stays in the CPU’s input table for just one CPU sweep, logic should be used to capture analog inputs from these references and move them into registers. Example logic is shown below.

<< RUNG 1 >>

*****************************************************************************

* The rung below moves the input circuit number to a register

(ROOOl).

*

will be used as a pointer in the next rung to demultiplex the four

* analog input circuits and to store the data into a table of four

* registers.

*****************************************************************************

It *

*

*

*

BUS

INPUT

CONTRLR CIRCUIT

OK

+

--

IO257

1

TABLPTR

ANALOG

NUMBER

INPUTS

IO353

ROOOl

MOVE RIGHT 8 BITS l-

<< RUNG 2 >>

( 1

*****************************************************************************

* The Source-to-Table Move instruction below takes the analog input data

* for each of the four input circuits from IO337 through IO352 and then

* stores it into a table starting at register ROOO2.

Register ROOOl

* contains the analog circuit number and is the pointer to one of the

*

*

*

*

* four registers in the table.

Six should be used for an RTD block (LEN=61 .*

*****************************************************************************

BUS

CONTRLR

OK

ANALOG TABLPTR

DATA

ANALOG

IN INPUTS

+ mm

I

IO257

IO337 ROOOl Const

1 [ ---[ SRC-TO-TABLE

LEN]-

004

( 1

<< RUNG 3 >>

*****************************************************************************

* This rung turns off the Bus Controller OK bit at the end of each CPU

*

* sweep so that the Bus Controller can turn it back on.

It is then used in *

* the logic above to enable the analog data to be processed.

If the Bus

*

* Controller OK bit does not come back on the analog data is not processed. *

*****************************************************************************

( 1

Logic is needed to transfer analog inputs only. Analog outputs and discrete inputs and outputs are not multiplexed.

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Interfacing Genius I/O Blocks to the Series Six PLC

3-9

GFK-017 1

Special Programming Required for:

Analog Blocks (all types)

High-Speed Counter Blocks

PowerTRAC Blocks

The application program may need to include logic to extend the programmer window time if the following blocks are assigned to I/O references: l

5 or more analog, RTD, or Thermocouple blocks l

5 or more PowerTRAC blocks (IC660BPMlOO version C or later) l

1 or more High-speed Counter blocks l

1 or more Power Monitor Modules (IC660BPMlOO version B or earlier)

This logic should be located before any logic that ties to access the

input information.

BUS CONTROLLER MEMORY

SHAktv

RAM

. I_. 1-m..

*

a42892

ALL

INPUTS

FROM

ANALOG

BLOCK

TRANSFER OCCURS

DURING l/O SCAN

TRANSFER OF A SINGLE VALUE

OCCURS DURING PROGRAMMER WINDOW

The Bus Controller begins organizing input data from the blocks listed above at the start of the programmer window portion of the CPU sweep, and continues until all the data has been organized. If the program includes DO I/O instructions to obtain the latest data from the block or if the program is very short, program logic should be used to extend the time of the programmer window. This will

allow the

Bus Controller time to complete the task before the I/O update begins.

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340

Interfacing Genius I/O Blocks to the Series Six PLC

GFK-0171

Logic to Extend the Programmer Window

To find the total time needed to update inputs during the programmer window, find the contributions of any analog, RTD, Thermocouple, High-speed Counter, PowerTRAC or Power Monitor Blocks on the bus that are assigned I/O Reference Numbers.

Number of analog, RTD, Thermocouple and

PowerTUC blocks:

Number of High-speed Counters:

Number of Power Monitor Blocks: x 0.057mS = x 0.422mS = x 0.503mS = total = mS mS mS mS

Subtract the programmer window time:

- 0.31lmS mS delay required

To extend the programmer window, add one of the following commands to the program before any I/O update (either normal I/O update or DO I/O instructions): l to extend the programmer window by 1.2mS, direct an extra idle (status = 0) DPREQ or WINDOW instruction to the Bus Controller. l to extend the programmer window by 5mS, program a DPREQ or WINDOW instruction with no Bus

Controller address.

Using the Read Analog Inputs Command

Another way to update inputs from these devices is with a Read Analog Inputs command, which reads values from the Bus Controller’s own RAM: memory (not from shared RAM). This area of memory always contains the latest values from all input circuits on each such device. If the program is required to have the most current values of these inputs as the logic executes, a Read Analog Inputs command should be used instead of a DO I/O instruction. DO I/O reads input values from shared RAM Since the

Bus Controller updates shared RAM only once per CPU sweep, multiple DO I/O instructions in the same program sweep will return the same values each time.

PROGRAM

READ ANALOG a42893

DO I/O b b

SHARED

RAM b

MEMORY

B/C

RAM

MEMORY

/

ALL

I

INPUTS

FROM

BLOCKS

I

ONE NEW VALUE

EACH CPU

SWEEP l-l

LATEST VALUE

FOR EACH CHANNEL

EACH BUS SCAN

For more information about the Read Analog Inputs command, see chapter 7.

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4-l

Chapter

4

Automatic Diagnostics and Fault Clearing

GFK-017 1

This chapter explains how set up an application program to use the built-in Genius I/O diagnostics and fault-clearing features of the Logicmaster 6 software. Use of these features requires the Expanded

Functions in both the PLC and in the software. If the system will make use of more than one application program at different times, each program should be set up as described in this chapter. Begin by starting up the Logicmaster 6 software and loading the application program into programmer memory.

The CPU Configuration Instruction

To access the Expanded Functions, the CPU Configuration instruction must be placed in the ladder logic program. When this has been done, the following line should appear as rung 1 of the program:

-ISERIES SIX CONFIGURATION DATAI-

If there is already a CPU Configuration instruction in the program, do not enter another one. With the

CPU Configuration instruction in the program, the screens shown on the following pages can be used to set up and display information about the Bus Controllers and Genius I/O in the PLC system.

If you

change any of the setup screens for a program that was already stored to the Series Six CPU, the program must be stored to the CPU again for the changes to be used.

Expanded Functions Menu

Press F7 (Expanded Functions) from the Supervisor menu to display the Expanded Functions menu.

LOGICMASTER

EXPANDED

L/M OFFLINE

FUNCTIONS

(TM) 6

KEY 3

FUNCTION

Fl - CPU CONFIG

F2 - I/O FAULTS

F4 -MSDFUNC...

F8 - SUPERVMENU.

. . . . . .

.Display/Modify CPU Configuration

. . . . . . .

Display/Clear Genius I/O Faults

e .e.

Display/Modify Machine Setup Data

F5 - 90-70 CONFIG

F6 - 90-70 DSPLY.

. . . . . . .

Display/Modify 90-70 operands

. . . . .

Display 90-70 operands and status

e . . o . . . . .

Return to Supervisor Menu

CPU I/O

1CONFIG 2FAULTS 3

MSD

4FUNC

90-70 90-70

SCONFIG 6DISPLY 7

SUPERV

8 MENU

This menu is used to select several different Expanded CPU functions (not all are related to Genius I/O diagnostics).

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Automatic Diagnostics and Fault Clearing

GFK-0171

CPU Configuration Setup Menu

The

first step in customizing the application program is to match it to the intended characteristics of the system. This is done by completing entries on the CPU Configuration Setup Menu. To access this menu, select Fl (CPU Configuguration) from the Expanded Functions menu.

L/M OFFLINE

CPU CONFIGURATION

SET UP MENU

EIBANDED I/O

SCAN:

ENABLED

BEGIN RANGE

END RANGE

CHANNEL0

CEaNNELO

Y

(Y/N)

POINT 1

POINT 1024

GENIUS I/O

DIAGNOSTICS:

DIAGNOSTICS ENABLED

DIAGNOSTIC TABLES

B/C -> POINT FAULTS

DIAGNOSTIC RANGE LIMIT

CPU REGISTER SIZE

FAULT TABLE LENGTH

Y

Y

N

7

8192

8

BUS STATUS/CONTROL

BYTE LOCATION

993

COMPUTER MAILBOX: ENABLED

N

B/C

1MAp 2 3

4 5

6

(Y/N)

(Y/N)

(Y/N)

(O-7) CHANNELS

(Y/N)

7

REGISTERS

ENTRIES

XPNDED

8 FUNC

The CPU Configuration Setup Menu displays entries for selecting: l

Expanded I/O scanning. l

Automatic diagnostics and fault clearing. l

The Computer Mail Box.

When the CPU Configuration function described on the previous page is placed in the program, it uses

the entries

currently selected on this menu. Check the entries on the screen against the descriptions in this chapter.

Diagnostics Enabled:

Setting this

entry to Y causes the CPU to create a fault table to automatically store Genius I/O faults. The table will occupy the number of registers specified by the entry FAULT TABLE LENGTH (see the next page). The maximum length and location of the fault table depend on the CPU memory capacity. See appendix A for the maximum fault table length and location for your CPU.

Individual Bus Controllers will always be capable of reporting faults and clearing faults.

Selecting Diagnostics Enabled = YES allows all fault reports from all configured Bus

Controllers to be automatically gathered together; it also allows all faults on all busses to be cleared with a single action from the programmer or PLC.

A Bus Controller with diagnostics automatically provides fault information for this table.

If diagnostic reports are not needed from a

Bus

Controller, it may be excluded from diagnostics scanning by specifying a smaller range with the entry for DIAGNOSTIC

RANGE LIMIT (see below).

If this entry is set to N, the CPU will not store diagnostics information; neither automatic nor programmed diagnostics or fault clearing from the programmer will be possible.

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Automatic Diagnostics and Fault Clearing

GFK-017 1

However, fault reports and fault clearing will still be accessible with a Hand-held

Monitor on the bus.

Diagnostic Tables:

This is an

optional selection; for

most applications it should be

set to N. If this

entry is set to Y, when an I/O circuit fault occurs the CPU sets the internal bit which corresponds to the circuit reference to 1. For example, if a fault occurs at 12+0003, the

CPU sets the internal bit at 12-0003 to 1.

Because this function will operate over the entire range of Genius I/O for which diagnos- tics is enabled (by the entry DIAGNOSTIC RANGE LIMITS), it requires that an amount of memory equal to the amount for which diagnostics scanning is enabled be set aside in the CPU. For example, if Expanded I/O scanning is enabled for channel pairs l-3 and

9-B, the CPU will use registers R129 - R512 and R1153 - R1472 for inputs and outputs.

If Diagnostic Tables were enabled by setting this entry to Y, the CPU would use registers

R2177 - R2496 and R3201 - R3520 to store I/O circuit faults.

If this entry is set to Y, it is important to avoid using any registers within the reserved area for any other purpose (the location of internal references in register memory is shown in appendix A). In addition, Bus Controller reference numbers must be assigned

(with the backplane DIP switches) on 256.reference boundaries, NOT on 64.reference boundaries. The Bus Controller will use the additional references for I/O diagnostics.

B/C -> Point Faults:

This

entry is an extension of the one directly above; it defaults to N.

Unless the application requires all II0 point status bits to not select Y for this entry.

be

set in case of Bus Controller failure, do

If both entries above were set to Y, setting this entry to Y would cause the CPU to set all

208 input and 208 output point fault bits associated with a Bus Controller to 1 during any

CPU sweep if the Bus Controller failed to communicate with the CPU. This would affect only the internal status table; it would not change any real I/O states. To use these internal references, additional program logic would be required.

Diagnostic Range Limits:

This

entry specifies the upper limit for diagnostics scanning. The CPU scans I/O channels as pairs. For a system with non-Expanded I/O addressing, this entry should be 0 to scan the Main/Auxiliary I/O chain pair. For a system with Expanded I/O addressing, it defaults to the highest channel pair for which I/O scanning is enabled.

For example, if Expanded I/O scanning for channels O-3 and 8-B were enabled, but diagnos- tic reports were not needed from channels 3 and B, you would enter the number 2 here.

ENTRY

MAIN I/O CHAIN

AUX. I/O CHAIN

B

3

4

5

6

7

0

(main)

1

2

8

(a=)

9

A

B

C

D

E

F

4

I

BEING SCANNED

NO

DIAGNOSTICS

In this example, the program would report diagnostics from channel pairs O-2 and 8-A.

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Automatic Diagnostics and Fault Clearing

GFK-0171

CPU Register Size:

This

defaults to the number of registers in the Scratch Pad. The availability of register memory may limit the number of I/O points for which diagnostics can be stored.

If the CPU register size were 256, diagnostics could be stored for only the first 256 inputs and outputs in the Main I/O chain. For a CPU register size of lK, diagnostics would be stored up to the first 1024 inputs and 1024 outputs of the Main I/O chain. If the CPU register size is either 8K or 16K, diagnostics can be stored for 16K inputs and 16K outputs. If the Scratch Pad has already been set up, this entry should be correct for the

CPU. If it is not correct, change it by entering 256 or 1 (for lK), or 8 (for 8K) or 16 (for

16K).

Fault Table Length:

If

DIAGNOSTICS ENABLED is set to Y, this entry spec3ies the size (in registers) of the area in CPU memory where faults will be stored. The length of the fault table determines the number of faults that can be stored at the s ame time. (A fault will remain in the table until it is cleared by the program or from the computer keyboard).

If the table became full, there would be no room for additional fault storage, and the overflow faults would be lost. No new faults would be stored until the table was cleared.

The default fault table length is 8. Each fault occupies 10 registers of memory. The default Fault Table size, therefore, is 80 registers.

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Automatic Diagnostics and Fault Clearing

GFK-017 1

Each entry in the Fault Table has the following format:

Register 1 bits bits

o-9 :

10-11: bits

Register 2

.

12-15: bits

o-9:

bit 10: bit

.

bits

11:

12-15

Register 3 bits o-3

Bus Controller Address

Reference of Bus Controller (l-1000) zeros

Bus Controller channel (O-F)

Series Six I/O Address

I/O reference of circuit (l-1000) within a channel l= input reference affected

1 = output reference affected

Series Six I/O channel number (O-F) relative number of the circuit on the block (O-15*)d with zeros if the fault is not a circuit fault. unused, set to zero

Bus Controller status byte 83 bits 4-7 bits 8-15

Register 4: bits O-7 bits 8-15

Register 5: bits O-7 bits 8-15

Bus Controller status byte 84

Bus Controller status byte #5

Register 6: bit 8 o-3 bits 4-7 bits 8-15:

Register 7: bit 0: bit 1: bit 2: bit 3: bit 4: bit 5: bit 6: bit 7: bits 8-15:

Regist #er 8: bits O-7: bits 8-15:

Register 9: bits O-7: bits 8-15:

Register 10: bits O-7: bits 8-15:

Bus Controller status byte 86

Fault type bit 8: 1 = Bus Controller not responding

0 = Bus Controller OK bit 9: 1 = Serial bus error bit 10: 1 - Circuit fault bit 11: 1 = Loss of block bit 12: 1 = Addition of block bit 13: 1 = I/O address conflict bit 14: 1 - Block terminal assembly EEPROM failure bit 15: unused, set to 0

Fault type

0000 = Block headend fault

0001 - discrete circuit fault

0010 - analog circuit fault

1001 = discrete circuit fault (circuits 17-32 only)

0100 = RTD circuit fault ** unused, set to 0

Fault description bit 8: 1 - Loss of I/O power (Isolated block only) bit 9: 1 = Short circuit bit 10: 1 - Overload bit 11: 1 = No load/open line bit 12: 1 = Over temperature bit 13: 1 - Switch failed bits 14, 15: undefined

Fault description

1 - Analog input low alarm

1 - Analog input high alarm

1 - Analog input under range

1 - Analog input over range

1 = Analog input open wire

1 - Analog output under range, or RTD wiring error

1 - Analog output over range, or RTD internal fault

1 = not used, or RTD circuit shorted undefined, set to 0

Fault time - seconds tenths of seconds (00-09) two binary-coded decimal digits seconds (00-59) two BCD digits

Fault time - minutes/hours minutes (00-59) two BCD digits hours (00-23) two BCD digits

Fault time - days days (00-99) two BCD digits hundreds of days (00-99) two BCD digits

* Add 16 to this if fault type is 1001.

** Bits O-3 will show faults 1001 and 0100, but no further decoding is performed in register 6 or 7.. Logicmaster 6 version 4.01 decodes the Bus

Controller status bytes for this information.

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Automatic Diagnostics and Fault Clearing

GFK-0171

The size selected for the fault table will depend on the amount of register memory available, and the number of faults that are expected to accumulate before an operator is able to clear them.

The amount of register memory available for the Fault Table depends both on the entry for CPU Register Size (above), and on the Computer Mailbox. Appendix A shows the allocation of registers in CPU memory.

The Computer Mailbox is explained on the next page. If the Computer Mailbox is enabled, it will occupy some of the register memory that would otherwise be used for the fault table. Maximum table lengths (number of faults that can be stored) are listed below.

REGISTER

SIZE

I

MAXIMUM TABLE LENGTH

I

COMPUTER MAILBOX ENABLED?

NO YES

256

1K

8K

16K

8

68

399

1218

1

75

406

1225

Bus Status/Control Byte Location:

This

is an address shared by ALL Bus Controllers in the system for status and control information. The Logicmaster 6 software defaults this address to

993, which reserves references 993 to 1000 in both the input and output tables in the

Main I/O table for the Bus Controllers. Any byte of available memory may be assigned, however

it is important that the contents of this

memory location not be

used for

anv

other purpose by the program, If the application program requires the use of I/b addresses 9934000 in the Main I/O chain, change this entry on the CPU Configuration

Setup Menu.

Computer Mailbox: Enabled:

The

Computer Mailbox is an area of memory that can be reserved for communications between devices. If the Computer Mailbox is enabled, any device that needs to communicate with another device can place a command and address of the other device in the Computer Mail Box. The CPU detects that a command is waiting, and opens a window to that device. The device should look in the mailbox registers for a command, then either read or write data (depending on the command specified). Devices that can communicate using the Computer Mailbox include the Series Six CPU, the

ASCII/BASIC Module, the CCM Module, and the Bus Controller.

The Computer Mailbox occupies the last 70 consecutive registers out of the total number available. Therefore, its starting address varies according to the CPU register memory size. For example, for a CPU with 8K register memory, the Computer Mailbox is located from R8123 through R8192. If the Computer Mailbox is not enabled, these registers are available for other use, for example, for the CPU fault table described above.

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Automatic Diagnostics and Fault Clearing

GFK-017 1

Genius Bus Controller Locations Screen

After completing the CPU Configuration Setup Menu, the next step is to indicate the locations of the

Bus Controllers. Press B/C Map (Fl) from the CPU Configuration Setup Menu. The screen will show each possible Bus Controller location in the system:

GENIUS

CURSOR:

BUS

L/M OFFLINE

LOCATIONS CONTROLLER

CHANNEL 0

LOCATION 0001

1

MAINCElAIN

CEZANNEL LOCATIONS

4

5

6

3

0

1

2

3

00000000 00000000

00000000

00000000

00000000 00000000

00000000 00000000

00000000

00000000

00000000 00000000

00000000 00000000

00000000 00000000

INSERT

2 BC 3 4 5

AUX. CHAIN

CHANNEL LOCATIONS

8

9

A

B

C

D

E

F

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

6

7

CPU

8CONFIG

The number beside the word LOCATION represents a possible Reference Number that might be assigned to a Bus Controller (using the backplane DIP switches). The cursor first appears at the rightmost location in the Main I/O chain (location 0001). Move the cursor to select a location, then press F2 to insert a Bus Controller. For example, this partial screen shows a Bus Controller at address

0129 in the Main I/O chain (channel 0):

Bus Controller location

CURSOR: CHANNEL 0 LOCATION 0129

MAIN CHAIN

CHANNEL

LOCATIONS

0

1

00000000 00000100

00000000 00000000

AUX. CHAIN

CHANNEL LOCATIONS

8

9

00000000

00000000

00000000

00000000

In this example, the CPU would use the 64 I/O references starting at 0129 for diagnostic data for the

BUS

Controller assigned to Reference Number 0129 in the Main I/O chain. This is explained in chapters 8 and 9. If there were only one Bus Controller in the system, no other entries would be needed.

Entering the Bus Controller locations on this screen completes the setup steps.

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Automatic Diagnostics and Fault

Clearing

GFK-0171

Genius I/O Fault Table Screen

When the PLC system is in operation, faults can be displayed and cleared from the Genius I/O Fault

Table screen. This screen lists all the faults currently stored by the CPU. Faults appear in the order they are reported to the CPU, with the first fault at the top.

To display and clear faults from 32.Circuit DC

block and RTD blocks, Logicmaster 6 version 4.01 or later is required.

TOTAL FAULTS: 0000

TOP FAULT DISPLAYED:0000

FAULT DISPLAYED:

GENIUS I/O FAULT TABLE

WC

POINT CIRC FAULT

ADDR. ADDR. NO. CATEGORY

----- ------ -m-Q I--oIIIIIIIIIIm- date time

oooo:oo:oo:oo:o

FAULT

FAULT

TYPE DESCRIPTION

~~~~~~~~ ~~~~~~~~~~~~~~~0

DAY:HR:MN:SC:T

~~~~~~~I~~~----

NEXT

PREV CLEAR

1 PAGE 2 PAGE 3FAULTS 4 TOP SBOTTOM 6 7

XPNDED

8

FUNC

This screen can only be displayed if the current ladder logic program includes the CPU Configuration function, and if Genius I/O diagnostics is enabled in the CPU Configuration Set Up Menu.

The table includes both I/O block faults, and the following faults which may be reported directly by the

Bus Controller: l

Bus Controller fault l

Bus Error l

Loss of block l

Addition of block l

Address conflict l

EEPROM failure

Fault definitions are given in chapter 5. The format of each fault listing in the table is explained on the following pages.

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Automatic Diagnostics and Fault Clearing

GFK-017 1

Fault Table Display: Definitions

The

entries in the fault table show the following information about a fault. If a fault occurs that has more than one category (see below) each description is listed as a separate line in the table.

B/C Addr:

Bus Controller II0 Reference: Displayed for all faults. This entry has two fields:

Series Six Channel Number: The first field is the number of the channel where the error occurred. A hex value from 0 to F. The Main I/O Status Table is shown as 0 and the Auxiliary I/O Status Table is shown as 8.

MAIN

AU?CILIARY

0

8

1

2

3

4

5

6

7

C

D

E

F

9

A

B

Channel Byte

= 0 to 125.

Address: The second field is byte address of the error within the indicated channel. Range

Point Addr:

Series Six Point Address: Not displayed for a Bus Controller or Serial Bus fault. This entry has two fields:

Input/output: faults.

The first two characters indicate an input (I) or output (0). Both may appear for some

Address: The second field shows I/O reference address of the error within the channel (base address for analog blocks). Range = 1 to 1000.

Circuit Number:

The

circuit number on the block. Displayed onlv for a circuit fault.

Range = 1 to

32.

Fault Category:

This

entry shows the category of error that has occurred.

BC FAULT

BUS ERROR

CIRCUIT FAULT

LOSS OF BLOCK

BLOCK ADDITION

ADDRESS CONFLICT

EEPROM FAILURE

???????????????? (displayed for unknown entries)

Fault Type:

If the

fault is an I/O block circuit fault, this entry shows the error type: BLOCK,

DISCRETE, or ANALOG. For other types of faults, this field is blank.

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4-10

Automatic Diagnostics and Fault Clearing

GFK-0171

Fault Description:

Displayed only if the Fault Category is CIRCUIT FAULT. Multiple lines are displayed if more than one description is associated with a fault data entry. Some example descriptions are:

EEPROM FAILURE

SHORT CIRCUIT

NO LOAD

SWITCH FAILED

HIGH ALARM

OVER RANGE

BC NOT OK

LOSS OF MODULE

I/O ADDRESS CONFLICT

INTERNAL FAULT

LOSS OF POWER

OVERLOAD

OVER TEMP

LOW AId4RM

UNDER RANGE

OPEN WIRE

SERIAL BUS ERROR

ADDITION OF MODULE

IN WIRING ERROR

INPUT CHAN SHORT

Fault Time:

The

day, hour, minute, second, and tenth of a second. The value of the CPU’s real-time clock when the error report was received corn the Bus Controller.

Clearing Faults

Press the F3 (Clear Faults) key to clear all faults in the table. This sets the fault count to zero, clears out any faults currently buffered in the Bus Controller, and clears the fault data currently latched at the

Genius I/O blocks. Subsequent incoming faults fill the Fault Table from the beginning. If a condition which caused a fault has not been corrected, the fault message will reappear.

For the serial version of Logicmaster 6 sofnuare, On-Line changes to the CPU must be enabled to clear faults

from

the programmer.

Printing

a

Copy of the Fault Table Screen

When the fault table is displayed on the screen, it can be printed using the ALT/P keys. (Printing must be set up as explained in

the Logicmuster 6 Software User’s Manual).

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S-1

Chapter

5

Programming Window Commands

GFK-0171

This chapter explains how to use “window” commands if the program needs to communicate with a

Y device on the bus.

Each window instruction recognizes the following commands:

1

Idle

2 Read Configuration*

3 Write Configuration*

4

Read Diagnostics*

7 Read Analog Inputs

9 Read Status Table Address

11 Switch BSM”

12 Send Datagram

13 Receive Datagram

*

Can also be programmed as a Datagram. See chapter 6 for more information.

If the system includes multiple CPUs connected by a Genius bus, programmed as described in chapters

6

and

7.

communications betwecn them can be

Program Instructions

Communications between the CPU and one of its Bus Controllers can be specified with a DPREQ or

WINDOW instruction in the program, or via the “Computer Mailbox”. For most applications, a

DPREQ will be used if the system is set up for Normal I/O addressing (main and auxiliary I/O chains only). A WINDOW instruction will be used if the system is set up for Expanded (channelized) I/O addressing.

Format of the DPREQ Instruction

The

ladder logic instruction for the DPREQ has this format:

Register where the address is stored

I I

--------I

RO800

DPmQ 1 ~L~~~-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~---

0339

( 1

Address of the device communicating with the CPU

Do not use a DPREQ in a system with Expanded addressing. It would be broadcast to

the specified

address on all channels. If that address were used for more than one intelligent device (for example, more than one Bus Controller), conflicting replies would be received.

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5-2 Programming Window Commands

GFK-0171

Format of the WINDOW Instruction

The WINDOW instruction is similar to a DPREQ, except that it specifies both an address and a channel.

When the CPU encounters a WINDOW instruction in the program, it opens a communications window to the device at the specified address on the specified channel. The ladder logic for the

WINDOW instruction has this format:

First register in the

Command Block or Computer

Mail Box

1 I

-------(I

Const

I WINDOW Address

0601

RO800

Corn Block ~~~~~~~~~~-~------~~(

)

Address of the device communicating with the CPU

The WINDOW instruction is available with Logicmaster 6 software release 3.0 and later. It requires a

CPU with microcode version 110 or greater.

Using the Computer Mailbox

The

Computer Mail Box is an automatic communications window mode. The only ladder logic required to enable the Computer that operates when the CPU is in Run

Mail Box is the CPU Configuration instruction as the first rung in the program.

_

Use of the Computer Mail Box must be set up on the CPU

Configuration Setup Menu, as described earlier. Any device that needs to communicate with another can place a command and window address of the other device in the Mailbox. At the end of the CPU sweep, the CPU detects that a command is waiting and either reads data from the Mailbox or places data in the Mailbox to be returned to the requesting device.

The window that allows the Bus Controller to access the Mailbox is generated automatically by the CPU at the end of the CPU sweep. It is the last

Executive window, after the PDT, DPU, and CCM windows. It has a 5mS timeout length.

The CPU continues to open windows to the specified address every sweep there is a valid address in the

Mailbox. To stop opening windows, the address must be cleared out of the Mailbox by the device that accepts the window or the device or program that set up the address in the Mailbox. Although one of the registers in the Mailbox contains a status code, the CPU will not examine this register, and will not automatically close the window. The Computer Mail Box always uses the last 70 consecutive registers out of the total number available. The location of the Computer Mail Box registers depends on the

CPU register memory size. For example, for a CPU with 8K register memory, the Computer Mail Box is located from R8123 through R8192. For a CPU with 16K register memory, the Computer Mail located from R16315 through R16384.

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Programming Window Commands

GFK-017 1

The Command Block

The DPREQ and WINDOW instructions and the Computer Mailbox are programmed with a group of registers called a Command Block. The Command Block contain the instructions for the data transfer.

A typical Command Block has the following content:

,

\

Bus Controller

Address

Command Number

I-- -I ~

1

Target Address r

Address for data data registers

Register 1

I

Register 2

I

I

Register

3

Register 4

Register 5

1

Data can be placed in the Comrnan d Block registers with one or more Block Moves, or similar program instructions:

Permissive

Logic

Typical Command Block Contents

I-----___~

R0201

Block Move

I

+01257 +01257 +00002 +OOOOO +00321 +00211 +OOOOO +OOOOO

1st Register

in Command Block

R0201

+

1

04E9

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Programming Window Commands

GFK-0171

The exact content of the Command Block depends upon the type of command it describes, as summa- rized below.

In

Register 2 is

this discussion, the term “Register 1” simply means the first the second register, and so on.

register of a group.

Register 1. The

first register of the Command Block provides the backplane address of the Bus

Controller to which the CPU sends the command.

For a WINDOW instruction, use the Bus Controller’s address. For example, 257.

For a DPREQ, use the Bus Controller’s address plus 1000. For example, 1257.

For the Computer Mailbox, use (channel number times 1024 plus starting I/O reference).

Use the decimal equivalent of the channel number. For example, Bus Controller location 257 on channel E (14 decimal) would be calculated like this:

(14x1024)+257 = 14593

Register 2. The

second register contains the Command Number, which may be one of the following:

2

=

3

=

4

=

7

=

9

=

11

=

12

=

13

=

Idle

Read Configuration

Write Configuration (also used to start/stop Global Data)

Read Diagnostics

Read Analog Inputs

Read Status Table Reference

Switch BSM

Send Datagram: Assign Monitor/Write Device/Write Point

Receive Datagram: Read Device

Register 3.

Status Code. This register should first be cleared to zero by the CPU. It will be loaded by the Bus Controller at the end of the window command (when status is available). Its content may be:

Hex

0000

0001

0002 oooc

0014

DtSCimd

00000

00001

00002

00012

00020

= Not accepted, CPU or Bus Controller busy with previous DPREQ.

=

Command in process but not completed.

=

Command completed successhlly.

=

Command terminated due to syntax error.

=

Command terminated due to data transfer error.

The Bus Controller verifies the Command Block for valid command syntax and the absence of a command of that type already in execution. If any syntax errors exist, the Bus Controller writes the error code (12) into the Status Code in the third register of the Command Block in the CPU

Registers 4 - 10. The

remaining registers in the Command Block are used for varying purposes by different commands, as indicated later in this chapter. Not all registers are used by all commands.

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Programming Window Commands 5-5

GFK-017 1

Program Structure

Window instructions can be programmed as separate rungs with conditional logic. It may be preferred to use just one window command and change the content of the Command Block each time. If that method is used, conditional logic should check the current Status Code (in Command Block register 3) before the content of the Command Block is changed.

If the program will also include programmed CPU to CPU communications, there are additional considerations for using window instructions which are explained in chapters 6 and 7.

Timing for Window Commands

The impact of window commands on the CPU sweep time depends on

the type

of commands used, and the relationship between the CPU sweep and the bus scan.

, l

An immediate

command is started and completed during a single window. The Bus Controller returns data to the CPU in the same instruction in which the command was issued and indicates Done (2) in the Status Code (Command Block register 3).

PROGRAM

CPU

BUS

CONTROLLER

1 (Read Configuration

of

Bus Controller)

1 opens window

2

sends command

3

transfers data

4 resumes logic execution

-- >

< a-

>

<

-a

1 reads command

2 transfers data

3 closes

window

It is possible for several immediate window commands to execute during the same CPU sweep. l

A Non-immediate

command is not completed during the same CPU/Bus Controller window.

When a Non-immediate command is accepted, the CPU opens a window to the Bus Controller, and sets the Status Code to 1 (In Progress). If the command cannot be executed immediately, the

Bus Controller puts the command into a queue and the window closes. While the window is closed, the Bus Controller will not accept any more non-immediate window comrnan ds for the

Bus Controller.

After the Bus Controller has finished processing the command (for example, sending configuration data to a block or reading configuration data from a block), it changes the status to “complete”

during the next available window

to that

Bus Controller. This probably will not occur during the same CPU sweep. In the interim, the status indicates “in progress”. If the processing fails

to

complete, perhaps due to a broken cable, the

Bus Controller sets the status to 20, “transfer error”.

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Programming Window Commands

GFK-0171

The

table below shows how long the CPU/Bus Controller window mav be open for both immediate and non-immediate commands.

Command

Idle

‘Read Configuration write configuration

Read Diagnostics

Read Analog Inputs

Read Status Table Reference

Switch BSM

Send Datagram

Receive Datagram

Immediate for a Block

n/a

IlO no no

Yes

no* no** no** no**

Immediate for a Bus controller

Yes

Yes

Yes

Yes n/a

Yes n/a

no** no**

Window Time

Best Case

1.2mS

2.5mS

2.5mS

2.5mS

2SmS

2.5mS

2.5mS

2.5mS

2.5mS

Worst Case

1.2mS

4.5mS

4.5mS

4.5mS

3.5mS

3.5mS

3.5mS

5.5mS

5.5mS n/a = the command cannot be sent to that type of target device).

* = or to another bus interface module on the same bus.

** = non-immediate if directed to a specific device. If a Datagram command is broadcast to all devices on the bus, it is an immediate command

When estimating CPU sweep time, add together the times of all windows the CPU might open to Bus

Controllers in the system during the same sweep. Remember that a Bus Controller will only accept one non-immediate command at a time. For each Bus Controller, the types of commands used and the relationship of the CPU sweep to the bus scan will determine how many co mmands executed in one sweep. are actually

In addition to these window times, the sweep time estimate must include the time required by some commands to transfer the requested data to the CPU. Each byte of data will add approximately

.O3lmS

to the CPU sweep time. For non-immediate commands this data will be returned during the next available window after receipt of data by the Bus Controller handling the command.

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Programming Window Commands

GFK-017 1

Idle

The Idle command opens a window from the CPU to the Bus Controller, but does not specify a task to be executed. Some program uses for the Idle command are:

1. to delay the CPU sweep.

2. to update I/O points that have been assigned register Reference Numbers.

3. to receive communications from other bus interface modules. See chapter 6 for information.

The Idle command takes approximately 1.2mS to execute if starting, or

there is no pending operation to

delay its

data

tran,$er to delay the window’s closing. The Idle command is immediate; it is always accepted.

Once the Idle command is accepted, if the previous command requested data from a device on the bus, or if an incoming Datagram has been received, the window will remain open while the data is transferred to the CPU. Similarly, the Bus Controller will transfer all Global Data it has received during the previous CPU sweep to the CPU during the first available window in the program. If the Idle command is first in the sweep, Global Data will be transferred at that time, adding .03lmS per byte to the CPU sweep.

Command Block for the Idle Command

The Idle command uses only registers 1-3. Command Block format for Idle is:

Register 1: Bus Controller Reference Number (plus 1000 for a DPREQ)

Register 2:

Command number 1

Register 3:

Status Code (supplied by the Bus Controller)

Delaying the CPU Sweep--More than 5 Analog Blocks

The Idle co mmand can be used to delay the CPU sweep at a selected place in the program. For example, a delay might be programmed if there were more than 5 analog blocks on the bus. This delay would allow the Bus Controller enough time to update all analog input values in its shared RAhL When used for this purpose, the Idle command should be located before any I/O update in the program.

3 for more information

See chapter

Updating II0 Points with Register References

For most applications, I/O points are assigned Reference Numbers in I/O memory and are updami during the I/O scan portion of the CPU sweep.

If I/O points have been assigned Reference Numbers which are in register memory instead of I/O memory, the points

will not be updated

during the I/O scan, An Idle command can be used to open a communications window, during which these I/O points will be updated.

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Programming Window Commands

GFK-0171

Read Configuration

The Read Configuration command is used to request current configuration data from the Bus Controller or a block. It cannot request data from another interface module on the bus, a Hand-held Monitor, or a block that has been assigned a register Reference Number.

If configuration data is requested from the Bus Controller, no message is sent on the bus; the Bus

Controller returns its configuration data to the CPU during the same window.

If configuration data is requested from a block, the Bus Controller schedules a Read Configuration message to the block as a “background” task then returns the Status Code 1 (In Process) to the CPU and closes the CPU/Bus Controller window. The Bus Controller accepts no additional non-immediate

CPU/Bus Controller window commands from the CPU until the task is completed. With the window closed, program execution resumes. The Bus Controller reads the configuration data from the block in

16.byte increments. When all the data has been received, the Bus Controller transfers it to the CPU at the start of the next available CPU/Bus Controller window and sets the Status Code to 2 (Done).

Command Block for the Read Configuration Command

Command Block format for Read Configuration is:

Register 1: Bus Controller Reference Number (plus 1000 for a

DPREQ)

Register 2:

Command number 2

Register 3:

Status Code (supplied by the Bus Controller)

Register 4:

Ten bit beginning address of the device from which configuration data is to be read. If the data is requested from an outputs-only block (not outputs with feedback),

bit 15

(MSB) must be set to 1. For an inputs-only block, bit 15 must be 0.

Register 5: Pointer to the group of registers in the Series Six CPU where the configuration data will be placed after the command executes.

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Programming Window Commands

GFK017 1

Data Returned by a Read Configuration Command

The

content of the reply message depends on the type of device being queried. Read Configuration

Reply contents for the Series Six PLC Bus Controller are shown on the following pages. Read

Configuration Reply messages for I/O blocks are defined in the Genius

I/O Svstem User’s h4anuaZ.

If the command requests the configuration of the Bus Controller, the Bus Controller immediately returns to the CPU its software revision number, the current I/O configuration of the bus, the states of the

Outputs Disable bits, and its Global Data (if any) starting address and length. Data format is shown below (register numbers below show relative locations).

20

21

22

23

16

17

18

19

12

13

14

15

8

9

10

11

4

5

6

7

REG. #

BYTE

1

2

3 lsb msb lsb msb

Isb msb

DESCRIPTION

Bus Controller Type (see Bit Assignments)

Software revision number bits O-4: No. of devices on bus (1-32)

Bus Controller Device Number (O-31)

Serial bus baud rate (see Bit Assignments) not used

Bit map of input points l-128

Bit map of input points 129-256

Bit map of input points 257-384

Bit map of input points 385-512

Bit map of input points 513-640

Bit map of input points 641-768

Bit map of input points

769-896

Bit map of input points 897-1000

Bit map of output points 1-128

Bit map of input points 129-256

Bit map of output points 257-384

Bit map of output points 385-512

Bit map of output points 513-640

Bit map of output points 641-768

Bit map of output points 769-896

Bit map of output points 897-1000

Outputs Disable flags for devices O-15

Outputs Disable flags for devices 16-31

Global Data starting address

Global Data/Datagram length (in bytes)

-

ONLY

_ Bus

Controller

_ CBB902 or CBB903 only

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5-10

Programming Window Commands

GFK-0171

Device Type (lsb of register 1) may be:

(IC660CBB900)

Bus Controller w/o diagnostics (IC660CBB901)

Bus Controller w diagnostics (IC660CBB902)

Bus Controller w/o diagnostics (IC660CBB903)

Decimal Iiinary

1

3

6

7

00000001

00000011

00000110

00000111

Register 2: Block Configuration Bit Assignments:

15~14(13~12~11)10( 91 81 71 6) 51 41 31 21 11

0

I

-----

. . . .

Register 3: Baud Rate

.

No. of active devices on bus

(l-32) READ ONLY not used

(0)

Bus Controller Device Number (O-31) READ ONLY

11 hex binary

----c-----

Baud

Rate: 153.6 Kbaud ext 4 100 not used (0)

153.6 Kbaud std 3 011

76.8 Kbaud 2 010

38.4 Kbaud 1 001

Registers 4-19: Bit map of active blocks (read only):

A

binary “1” in a bit indicates that the corresponding addresses (8 references) are assigned to a block. Some blocks (such as 16 circuit discretes) require more than 1 bit in this map. Registers 4-11 are a bit map of INPUTS assigned to active blocks. Registers 12-19 are a bit map of OUTPUTS assigned to active blocks.

BIT # bit 0 bit 1 bit 2 bit

3 bit 4 bit 5 bit 6 bit 7 bit 8 bit

9

bit 10 bit 11 bit 12 bit 13 bit 14 bit 15

Register

4112

00 l-008

009-016

017-024

025-032

033-04-O

041-048

049-056

057-064

065-072

073-080

081-088

089-O%

097-m

105-l 12

113-120

121-128

Register

s/13

129-136

137-144

145-152

153-160

161-168

169-176

177-184

185-192

193-200

201-208

209-216

217-224

225-232

233-240

241-248

249-256

Register

6114

257-264

265-272

273-280

281-288

289-296

297-304

305-3 12

313-320

321-328

329-336

337-344

345-352

353-360

361-368

369-376

377-384

Register

7/15

385-392

393-400

401-408

409-416

417-424

425-432

433-440

441-448

449-456

457-464

465-472

473-480

481-488

489-496

497-504

505-5 12

Register

S/16

5 13-520

521-528

529-536

537-544

545-552

553-560

561-568

569-576

577-584

585-592

593-600

601-608

609-616

617-624

625-632

633-640

Register

9117

641-648

649-656

657-664

665-672

673-680

681-688

689-696

697-704

705-712

713-720

721-728

729-736

737-744

745-752

753-760

761-768

Register

10118

769-776

777-784

785-792

793-800

801-808

809-8 16

817-824

825-832

833-840

841-848

849-856

857-864

865-872

873-880

881-888

889.8%

Register

11119

897-904

905-912

913-920

921-928

929-936

937-944

945-952

953-960

961-968

969-976

977-984

985-992

993-1000

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Programming Window Commands

GFK-017 1

5-11

Registers

20

and 21: (read/write) For Bus Controllers IC660CBB902 and 903

only, registers 20 ami 21

are used as Output Disable flags, with one bit for each device on the bus. The least significant bit of register 20 represents Device Number 0 and the most significant bit of register 21 represents Device

Number 31.

31

IIIIII

Register 21

III

Ill IIIIIII

16 15

Register

20

Illlllllllll~

0

Output disable bit

.

for device

#0

Output disable kt for device

#31.

For each bit, a one causes the CPU to read the block’s outputs are sent to the corresponding Device Number. inputs, but not to send outputs. When a bit is 0,

No more than two CPUs on the same bus should have their outputs enabled to the same blocks. This table can be defaulted to all 0 or all 1 at powerup using the Disable Outputs DIP switch on the Bus Controller (see chapter 2).

Register 22 (Read/write): For Bus Controllers IC660CBB902 and 903 only, register 22 contains the starting register address for the Global Data in the resident CPU. The Bus Controller defaults register 22 to FFFF hexadecimal, indicating no Global Data to be sent. See chapter 7 for information about using

Global Data.

Register 23 (Read/write): For Bus Controllers IC660CBB902 and 903 only, register 23 contains the length in bytes (number of registers times 2) to be transmitted from resident CPU to another CPU on the bus using Global Data. Maximum is 128 bytes (64 registers). At powerup, the Bus Contdkr cMauks register 23 to 0.

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5-12

Programming Window Commands

GFK-0171

Write Configuration

The Write Configuration command is used to send configuration data from the CPU to the (phase B)

Bus Controller or to a block on the bus. It cannot be sent to another bus interface module or to a block that has been assigned a register Reference Number.

When sent to the Bus Controller, this command is immediate (completed during

the Bus Controller window). The Write Configuration command can also be used to:

1. enable or disable outputs from the CPU to devices on the bus.

2. start or suspend Global Data transfer (see chapter 7).

I/O blocks can be configured (or reconfigured) using this command. However, each block must first have its Reference Number and Device Number (serial bus address) entered using the Hand-held

Monitor. If configuration data will be sent to a block, the

Bus

Controller first reads the intended configuration data from the CPU registers during the CPU/Bus Controller window and schedules background Write Configuration messages to the block. The Bus Controller returns the Status Code 1

(In Process) to the CPU then closes the window. The Bus Controller accepts no more non-immediate window

commands

from the CPU. Once message transmission begins, the Bus Controller sends the configuration data to the block in 16-byte increments. The block does not use any of the new configuration data until it all has been received. No new commands can be sent to the block until the operation has been completed. When all the data has been sent, the Bus Controller changes the Status

Code to 2 (Done) at the next available DPREQ or WINDOW instruction, then closes the window.

NOTE

When performing a Write Configuration command to the Bus Controller, pay special attention

to

the

output enable/disable bits to ensure that these are changed only when that is the intent.

Outputs should be disabled if there are no blocks on the bus.

Command Block for the Write Configuration Command

Command Block format for the Write Configuration command is:

Register 1:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Register 2:

Command number 3

Register 3:

Status Code (supplied by the Bus Controller)

Register 4:

Ten bit beginning reference address of device to which configuration data is to be is written to an outputs-only block, you must set the MSB (bit

15)

to

1. written.

If the data

Register 5: Pointer to block of registers where configuration data for the block or Bus Controller starts

Data Written by the Write Configuration Command

The configuration data to be written must be set up in the registers before the command executes. The data must have the format shown for the Read Configuration command. Also see the

Genius I/O

Svstem

User’s Manual, “Read Configuration Reply”.

Items marked Read Only are ignored by the blocks.

Changing the register values for one feature (such as disabling outputs) will not change another feature

(such as Global Data) if the registers for that feature retain their previously-configured values.

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Programming Window Commands

543

GFK-017 1

Enabling and Disabling Outputs

When sent to the Bus Controller, the Write Configuration command can be used to enable or disable the sending of output messages from the CPU to some or all of the blocks on the bus.

This applies to input-only blocks

too, as they rely on receipt of the null output message

to turn their II0 Enabled LEDS on and o#.

Enabling Outputs at

Powerup

The Bus Controller’s on-board DIP switch can be set to disable all outputs at powerup as explained in chapter

2.

With program logic, use the Write Configuration command to enable outputs to the blocks which are intended to be under the control of this Bus Controller. This includes input-only blocks.

Disabling Outputs on a Communications Bus

If the bus is used for communications, and has no blocks, outputs should be disabled to conserve scan time.

Selectively Disabling Outputs for Distributed Control

of I/O

Blocks

Some systems use two or more CPUs on the same bus for distributed control of I/O blocks. Each CPU sends outputs to (and receives fault reports from) certain blocks on the bus and not others. This is accomplished by selectively enabling or disabling outputs with a Write Configuration command to the

Bus Controller.

\

CPU a42485

CPU

CPU

BUS

INTERFACE

MODULE

BUS

INTERFACE

MODULE

BUS

INTERFACE

MODULE

v

(DEVICE 31)

\

(DEVICE 7)

1 ,

(DEVICE 30)

-T=zF F==a-

t 1

Obtaining Diagnostics from Blocks with Outputs Disabled.

from a block only to the Bus Controller that is sending or

Diagnostic messages are automatically sent has previously sent it outputs. If the CPU should receive all diagnostics reports from one or more blocks to which outputs are permanently disabled, the Assign Monitor Datagram can be used.

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5-14 Programming Window Commands

GFK-0171

Disabling Outputs for an Assigned Monitor

In some systems, the Series Six PLC will be used as a monitoring device only, to receive I/O data from the blocks on the bus. When being used as a monitor, the PLC can also receive fault reports and configuration change messages from any blocks that have been sent the Assign Monitor command.

CONTROLLER MONITOR a42566

CONTROLLER CONTROLLER

I

PHASE B I 10 BLOCKS

Output data for these blocks will be supplied by one or more other CPUs on the same bus.

a!42566 CONTROLLER MONITOR r

I r

I

PLC

I I

PLC

I

I

I

PHASE B I / 0 BLOCKS

A device that is assigned as a monitor should have all its outputs disabled. This can be done using a

Write Configuration co mmand in the program or by setting the Bus Controller DIP switch. If a

Bus

Controller is used as a monitor, it cannot be located in the same CPU as any other Bus Controllers on

the same bus. Othenvise, the CPU would receive input data from both Bus Controllers for the same references, and purity errors could result.

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Programming Window Commands 5-15

GFK-017 1

Read Diagnostics

The Read Diagnostics command can be used to request diagnostic information about a block and its I/O circuits, or the status of Bus Controller and the bus. It cannot be sent to a block that has been assigned a register Reference Number.

The diagnostic data returned by blocks in response to this command indicates faults that have occurred since powerup, or since the last Clear Faults message was issued. Current diagnostic state can be found by first issuing a Clear Faults command to the circuit(s) or channel(s) to clear the fault history, then issuing a Read Diagnostics command.

A Read Diagnostics command is completed during the same window only if it is sent to the Bus

Controller If diagnostics data is requested from a block, the Bus Controller schedules a background message to the block and returns the Status Code 1 (In Process) to the CPU. The Bus Controller then closes the CPU/Bus Controller window and accepts no additional non-immediate window commands from the CPU. With the window closed, the Bus Controller reads the diagnostic data from the block in

16.byte increments. When all the data has been received, the Bus Controller transfers it to the CPU at the start of the next available CPU/Bus Controller window and sets the Status Code to 2 (Done) then closes the window.

Command Block for the Read Diagnostics Command

Command Block format for the Read Diagnostics command is:

Y

Register 1:

Register 2:

Register 3:

Register 4:

Register 5:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Command number 4

Status Code (supplied by the Bus Controller)

Ten bit beginning reference address of the block or Bus Controller from which diagnostic data is to be read.

If the diagnostic data is read from an

t

block, set the MSB (bit 15) to 1. this register contains a pointer to an address where the retumed diagnostic data will be stored in the

CPU registers.

Data Returned by the Read Diagnostics Command

The exact content of the Read Diagnostics reply message depends on the type of device being queried.

Read Diagnostics Reply message contents for the Series Six PLC Bus Controller are shown on the following page. Read Diagnostics Reply messages for I/O blocks are defined in the

Genius II0 System

User’s Manual.

The PLC can also obtain diagnostic information from I/O blocks by:

1. enabling the automatic diagnostics features of the Logicmaster 6 software, as described in chapter 4.

2. monitoring the Bus Controller input references, as described in chapter 8.

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5-16

Programming Window Commands

GFK-0171

Data Available using a Read Diagnostics Command to a Bus Controller

If the Read Diagnostics command is sent to the Bus Controller, the returned data has the following format (register numbers below are relative locations).

If the Bus Controller does not have diagnostics capabilities (IC660CBB901 or 903), an error message is returned. This command is immediate when sent to the Bus Controller; the data is returned during the same window.

REG.

1

BYTE kb msb kb msb

I

DESCRIPTION

Device type

Software revision number

Self-test Diagnostics not used, always 0

Serial bus error count

Serial bus scan time in milliseconds (3-400 decimal)

Number of active blocks (O-31)

Device Type (lsb of register #l) mav be:

Bus Controller w diagnostics

Bus Controller w diagnostics

(IC660CBB900)

(ICddOCBB902)

Decimal

1

6

BiIllU-J7

00000001

00000110

Self-test Diagnostics (Register 2) may be:

71 61

51 41 31 21

4

*

1

= Bus Controller

1 = EPROM failure

Manager microprocessor failure

1 = RAM failure

1 = Series Six shared RAM failure

1 = Communications port shared RAM failure not used

1 = Communications

Port microprocessor failure not used

Error Count (register 3) is a sixteen-bit rollover count of the number of CRC receive errors detected on the serial bus. This count will roll over from 65,535 to 0, and may not be reset.

An FFFF value in Register 4 indicates that the scan time has exceeded 400mS which means that the Bus

Controller must have missed its turn on the serial bus.

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Programming Window Commands

517

GFK-017 1

Read Analog Inputs

The Read Analog Inputs command is used to read all of the input values from an certain future devices during one CPU sweep. Read Analog Inputs is an immediate analog block, and command and can therefore always be executed.

a register Reference Number.

Note that this command cannot be sent to

a block that

has

been assigned

How Analog Inputs are Obtained by the CPU

An analog block broadcasts current values for all of its input circuits each bus scan. The Bus Controller receives these values, and stores them in its on-board RAM. memory. Once each CPU sweep, (during the

programmer

window), the Bus Controller transfers the latest inputs for a specific analog circuit on the block into the portion of its RAM. memory it shares with the CPU. Each sweep, the circuit number changes on a rotating basis.

ONE

’ b

BUS CONTROLLER MEMORY

9 b 4

SHARED

RAM

MEMORY

B/C

RAM

MEMORY

.

/ a42892

ALL

INPUTS

I

FROM

ANALOG

BLOCK

TRANSFER OCCURS

DURING l/O SCAN

TRANSFER OF A SINGLE VALUE

OCCURS DURING PROGRAMMER WINDOW

During the I/O scan portion of the CPU sweep, one input per analog block and its circuit number are picked up by the CPU automatically from the block’s assigned input references. On successive CPU sweeps, other inputs from the block overwrite the same input references. As explained in chapter 3, logic must be used to copy the input values into other registers to prevent their being constantly overwritten.

Using Read Analog Inputs

The Read Analog Inputs command reads input values from the “direct access” area of memory in the

Bus Controller (not from shared RAM). This area of memory always contains the latest values from all blocks on the bus. Since Read Analog Inputs supplies a register bank into which the analog input values are to be transferred, circuits do not overwrite one another. Only the data values are supplied, one value per register; no circuit number is supplied.

Logic for a Bus with More than 5 Analog Blocks

If there are more than 5 analog blocks, a High-speed Counter, or a Power Monitor Module on the bus, the programmer window may be too brief for the BUS Controller to copy all the input data for those modules from its RAM. memory into shared RAM. A Read Analog Inputs command can be used to obtain input values, as described above.

See chapter 3 for information about using analog blocks,

High-speed Counters and PowerTWK Modules.

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.

5-18

Programming Window Commands

GFK-0171

Using DO II0 to Update Analog Inputs

If the program must know the most current values of analog inputs as the logic executes, use a Read

Analog Inputs command, not a DO I/O instruction. DO I/O reads input values from shared RAM. Since the Bus Controller updates shared RAM. only once per CPU sweep, multiple DO I/O instructions in the same program sweep will return the same values each time. a42893

PROGRAM

READ ANALOG

\

DO I/O

b

.

SHARED

RAM

MEMORY

I

I

\

B/C

RAM e

MEMORY

ALL

1

INPUTS

FROM

BLOCKS

ONE NE; VALUE

EACH CPU

SWEEP

LATESYVALUE

FOR EACH CHANNEL

EACH BUS SCAN

Example program logic for Read Analog Inputs is shown on the next page*

Command Block for the Read Analog Inputs Command

Register 1: Bus Controller Reference Number (plus 1000 for a DPREQ)

Register 2: Command number 7

Register 3: Status Code (supplied by the Bus Controller)

Register 4: Ten-bit Reference Number of the device whose input data will be read.

Register 5:

Pointer to a register address where returned analog data will be placed,

For analog blocks, the Bus Controller provides input values received from the block to the PLC, in the following format (register numbers are relative).

Register 1:

Input channel 1 (16 bit engineering units)

Register 2:

Input channel 2 (16 bit engineering units)

Register 3:

Input channel

3

(16 bit engineering units)

Register 4:

Input channel 4 (16 bit engineering units)

Register 5:

Input channel 5 (16 bit engineering units), RTD only

Register 6:

Input channel 6 (16 bit engineering units), RTD only

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Programming Window Commands 5-19

GFK0171

Example Program Logic to Read Analog Inputs

The example logic that follows would repeatedly execute a communications command to read analog inputs from a 4 Input/2 Output analog block. The program would store the engineering units values of the analog inputs in four consecutive registers starting at register R013 1. Therefore, R013 1 would always contain the value of input 1, R0132 would contain the value of input 2, and so on.

<< RUNG 1 >>

*****************************************************************************

* The Block Move instruction below moves seven constants to seven

* consecutive registers starting with Roll. Five of these constants

* represent a READ ANALOG INPUTS command that will read the four analog

*

*

*

* inputs from an Analog I/O block with I/O table address 337 and will store *

* the engineering units values into four consecutive registers starting

*

* at R0131. 00957 is permissive logic set elsewhere in the program to

*

*

* control execution of the DPREQ.

*****************************************************************************

ANALOG

DPREQ

00957 R0011

l/C w-m C

+01257 +00007

BLOCK MOVE

+OOOOO

+00337 +00131 +00000 +00000

I- ( 1

<< RUNG 2 >>

*****************************************************************************

* Other logic in the program tests the state of the Bus Controller OK bit.

*

* If the Bus Controller is OK, this DPREQ instruction will execute the

*

*

* READ ANALOG INPUTS coxunand every other CPU sweep.

*****************************************************************************

BUS

CONTRLR

OK

IO257

+

-0

1

[

-----

ANALOG

DPREQ

00957

R0011

10 ---[DPREQ]-

<< RUNG 3 >>

*****************************************************************************

* The rung below checks the READ ANALOG INPUTS command block status

* register to determine whether the current status of the command is 2,

* indicating successful completion.

If the status is not

equal to 2,

* input data may not be current and could be invalid.

*****************************************************************************

( 1

*

*

*

*

ANALOG

IN DATA

VALID

00001

Const

+[ A

+00002

MOVE

ANALOG

ALWAYS ALWAYS

DPREQ

+00002 +00002 STATUS

R0010

B

l-1

R0010

A

R0013

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5-20

Programming Window Commands

GFK-0171

Read Status Table Reference

The Read Status Table Reference

command is used to:

1. read the Reference Number of the Bus Controller.

2. read the Reference Number and I/O type of an I/O block.

3. read the Global Data address of another CPU on the same bus.

This command is immediate if sent to the target Bus Controller.

It is non-immediate if sent to a block or another bus interface module elsewhere on the bus.

Command Block for the Read Status Table I/O Reference Command

Command Block format for the Read Status Table I/O Reference Command is:

Register 1:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Register 2:

Command number 9

Register 3

Status Code (supplied by the Bus Controller)

Register 4: 5-bit Device Number of device to be read (O-31)

Register 5: Pointer to pair of registers where the I/O reference information from the device is to be written in the

CPU.

Data Returned by a Read Status Table I/O Reference Command to an I/O Block

If register 4 contains the Device Number of an I/O block, the following data about the block is returned to the CPU.

Register

1:

lo-bit Status Table Reference of block requested above.

Register 2: bits O-1:

Block I/O Configuration: 1= Inputs

only

2 = outputs only

3 = I/O combination bits 2-15: not used (zero)

Data Returned by a Read Status Table I/O Reference Command to a Bus Controller

If register 4 contains the Device Number of a Bus Controller or any other Global Data device, the following data about the device is returned to the CPU.

Register

1:

Register 2:

starting

address of Global Data for a Global Data device on the same bus.

FFFF = no Global Data

3

Any device on the bus which is capable of sending Global Data will return this information; it does not actually have to be using this feature.

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Programming Window Commands

5-21

GFK-017 1

Switch BSM

Use the Switch BSM command to cause a Bus Switching Module to select a bus in a dual bus system.

The program must already know which bus is

currently

selected. The CPU may issue the Switch BSM command at intervals to ensure continued proper bus switching capability.

If the command is successful, the CPU will report a Loss of Block diagnostic for the BSM Controller block and for any other block on the same bus stub. If the dual bus system includes a second Bus

Controller in the same CPU or another CPU controlling the other bus, that Bus Controller should report an Addition of Block diagnostic for each of those blocks. If the BSM position is currently forced by the

Hand-held Monitor, the command will be ignored. It is also ignored if the block does not control a

BSM.

Command Block for the Switch BSM Command

Format of the Command Block for the Switch BSM command is:

Register 1:

Register 2:

Register 3:

Register

4:

Register 5:

Registers 6-8:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Command number 11

Status Code (supplied by the Bus Controller)

S-bit Device Number of the discrete block that controls the BSM. Be sure the block is the BSM

Controller-this command does not check the block’s configuration.

Pointer to the qister in which the desired BSM position is indicated (see Register n below) not used

The content of the data sent from the CPU registers to the target device is:

Register n: BSM position (bit 0): 0 = bus A, 1 = bus B.

If not

0 or 1, syntax error number OC hex is returned in the status code.

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Chapter

6

Datagrams

chapter describes:

Types of Datagrams Supported

Normal or High Priority Datagrams

Using Datagrams instead of Global Data

Programming for Incoming Datagrams

Effect of Datagrams on the Genius I/O Bus

Maximum CPU Sweep Time Increase

Assign Monitor Datagram

Write Point Datagram

Write Device Datagram

Read Device Datagram

Types of Datagrams Supported

The Series Six Bus Controller supports the following Datagrams:

Message Type

Read Configuration *

Read ConfQwation Reply write [email protected] *

Assign Monitor

Begin Packet Sequence

End Packet Sequence

Read Diagnostics *

Read Diagnostics Reply

write Point

Report Fault

Pulse Test

Pulse Test Complete

Clear Circuit Fault

Clear All Circuit Faults

Switch BSM

Read Device

Read Device Reply

Write Device

Configuration Change

Read Data

Read Data Reply

Write Data

Subfunction Code m=)

12

13

1c

1E

1F

20

22

27

28

29

08

09

OB

OF

10

11

02

03

04

05

06

07

*

Window commands can be used to send Read Configuration, Write Configuration, and Read

Diagnostics Datagrams to the Bus Controller or to blocks on the bus which are assigned to

I/O memory.

For blocks assigned to register memory, the Send Datagram and Receive Datagram commands

(described in chapter 5) can be used to send these Datagrams instead.

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Datagrams

GFK-0171

Using Datagrams instead of Global Data

Datagrams and Global Data can be used to send messages between CPUs on the same bus. are individual messages, while Global Data is transferred automatically and repeatedly.

Datagrarns

CPU to CPU Datagrams can be used together with Global Data, or can replace Global Data. Consider using Datagrams instead of Global Data if:

1. Global Data takes up too much serial bus scan time for the application.

2. The data does not need to be sent every serial bus scan.

3. CPU sweep time becomes too long for the application.

In addition, Datagrams can be sent to either I/O or register memory in the receiving CPU, while Global

Data must be sent to register memory.

Normal or High Priority Datagrams

The Bus Controller handles Datagram commands in the same way as the other window commands described in chapter 7. When a Datagram command is encountered in the program, the CPU opens a window to the specified Bus Controller. The Bus Controller reads the command, sets the status, then closes the window. The Bus Controller sends the Datagram according to its assigned priority (see below).

Until transmission of the Datagram is complete, the Bus Controller will not accept

any

other non-immediate CPUIBus Controller window commands for processing.

A BUS Controller can send exactly one Datagram per bus scan. That Datagram may be assigned either

Normal Priority or High Priority. During one bus scan, there may be one Normal Priority datagram followed by up to 31 High Priority Datagrams or up to 32 High Priority datagrams sent by the devices on the bus.

If the bus will also be used for I/O block control, Normal Priority datagrams are recommended to allow other messages such as fault reports (which the system handles as Normal-priority Datagrams) to get through. In addition, Normal Priority Datagrams ensure that bus scan time is only modestly delayed for communications. Bus scan time affects the response time of any I/O data on the bus. If there are

I/O

blocks on the bus, use High Priority only if the Datagram transmission cannot be delayed. Normal

Priority will work satisfactorily except when there are many devices attempting to send Datagrams simultaneously.

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Datagrams

GFK-017 1

Programming

for

Incoming Datagrams

The Bus Controller may -receive Write Point, Read Device, or Write Device Datagrams from other interface modules on the bus. The Bus Controller will transfer the received Datagram message to the

CPU during the next open CPU/Bus Controller window. To open a window, a DPREQ or WINDOW instruction with the address of that Bus Controller must be present in the program. If the application program does not include any window commands to the Bus Controller, an Idle window command can be used.

It is important to handle incoming Datagrams efficiently, to prevent data loss. Each Bus Controller maintains an area in its RAM. memory where it can store 16 incoming Datagrams at the same time. It transfers one to the CPU each time a DPREQ or WINDOW instruction with its address is encountered in the program. If there are not enough window co mmands directed to a Bus Controller during one CPU sweep, it may accumulate only 16 incoming Datagrams. If that happens, additional Datagrams

will be lost.

This loss will not be detected by the system.

Because only one incoming Datagram can be sent to the CPU during a single window, it may be necessary to place additional window commands in the program if multiple incoming Datagrams are expected. The number of window instructions to a Bus Controller that are needed depends on whether the Datagrams have been sent using Normal or High Priority, and the relative lengths of the CPU sweep time and the scan time of the bus.

If the Bus Scan Time is Greater than the CPW Sweep Time

If all Datagrams on the bus are sent with Normal Priority, there is a limit of one incoming Datagrarn per

CPU sweep. Therefore, only one DPREQ or WINDOW instruction per sweep will be needed to handle the incoming Datagrams.

If all Datagrams on the bus are sent with High Priority, the Bus Controller can receive one Datagram from each transmitting device during each scan.

The program should include the sarne number of

DPREQ or

WINDOW instructions as incoming Datagrams.

If the Bus Scan Time is Less than the CPU Sweep Time

If the bus scan time is significantly shorter than the CPU sweep time, you can estimate the number of

DPREQ or WINDOW instructions that must be sent to the Bus Controller to accommodate incoming

Datagrams on that bus.

First, determine how many scans can occur in one CPU sweep. For example, if the bus scan were 2OmS and the CPU sweep were 9OmS, the ratio between them would be 4.5 to 1. This should be rounded upward to 5.

This is the maximum number of Normal Priority Datagrams that might be received in a

single CPU

sweep.

Plan to have the same number of DPREQ or WINDOW instructions in the program to handle the incoming Datagrams.

For High Priority Datagrams, multiply the number found above by the total number of devices on the bus that might send a High Priority Datagram to the Bus Controller in one bus scan This is the total number of incoming Datagrams from that bus the program might have to handle in a single CPU sweep.

Plan on this number of DPREQs or WINDOW instructions.

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Datagrams

GFK-0171

Effects of Datagrams on the Genius I/O Bus

Normal Priority Datagrams allow fault reports and Hand-held Monitor communications on a bus to continue undisturbed. Only one Normal Priority Datagram is allowed each bus scan, so the scan time stays relatively constant, and I/O update timing varies only by small increments.

If High Priority Datagrams are being transmitted constantly, the Hand-held Monitor will not function properly; fault reports from blocks will be prevented from being transmitted on the bus, and regular

DPREQ or WINDOW instructions (such as Write Configuration commands) to that Bus Controller will fail with a transmission error.

For these reasons, use of High Priority Datagrams on a bus with I/O blocks should be avoided if possible.

If High Priority Datagrams are transmitted infrequently, they will cause some delay in the Hand-held

Monitor communications and other normal system messages, but the delay should not be noticeable.

High Priority Datagrams will typically put more pressure on the Bus Controller to transfer multiple

Datagrams per CPU sweep. However, this can also occur with Normal Priority Datagrams if the bus scan time is much shorter than the CPU sweep time.

Maximum CPU Sweep Time Increase for Datagrams

To estimate the impact of Datagrams on CPU sweep time, add together the times required for all

Datagrams that might be sent between the Bus Controller and the CPU during one sweep. Repeat this for each Bus Controller in the Series Six PLC that sends or receives Datagrams.

+

OR

+

+ total Datagram Bytes Sent

(may be none)

LARGEST incoming Normal priority

Datagram Received, bytes total incoming High Priority

Datagram Bytes Received

2SmS to 5SmS for each window command used

+ x x

X

.03lmS =

.031mS =

.031mS =

1.20 mS = mS mS

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Datagrams

GFK-017 1

Assign Monitor Datagram

A

BUS

Controller or CPU on the bus can be used to monitor block faults and configuration changes.

Blocks broadcast their inputs to all devices on the bus; inputs will be received by a monitoring device automatically. In addition, one or more blocks can be instructed to send extra fault and configuration change messages to the assigned monitor.

These extra reports will add to the bus scan time, as explained in the

Genius I/O System User’s Manual. There can only be one device assigned as a monitor to any given block.

Send the Assign Monitor Datagrarn to all blocks that should report faults and configuration changes to the monitor. The message contains the Device Number of the monitor. If necessary, the assigned monitor may be changed by issuing another Assigned Monitor Datagram, with a new Device Number, to the block.

MONITOR

CONTROLLER

I

PLC

I I

COMPUTER

I

PCIM BUS

CONTROLLER

1 a42480

- VO BLOCKS -

The Assign Monitor Datagram can be sent to phase

B

Genius I/O blocks only. If sent to phase A blocks or to bus interface modules, the Assign Monitor command has no effect. A complete listing of phase

A and phase B Genius devices is located in the

Genius I/O System User’s Manual (GEK-90486).

Command execution is not immediate; the Bus Controller will not set the Status Code to 2

(Done) until

it receives an acknowledgement from the block.

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~~

Datagrams

GFK-0171

Command Block for the Assign Monitor Datagram

Command Block format for the Assign Monitor Datagram is:

Register 1:

Register 2:

Register 3:

\

Register 4:

Register 5:

Register 6:

Register 7:

Bus Controller Reference Number

Command Number 12 (Send Datagram)

Status code (supplied by the CPU). If the message is sent to one device, Assign Monitor is a non-immediate command the status register will indicate “done” when that device acknowledges the message. However, if FF is specified in register 4, Assign Monitor is an immediate command register 3 is set to “done” as soon as the message is sent, with no guarantee that the devices have received the message. the Device Number (serial bus address) of the block which should issue extra fault reports. If all blocks on the bus should issue extra fault reports, enter FF (hex) in this register. If only some blocks should report to the faults to the assigned monitor (for example, to minimize bus scan time), program separate Assign

Monitor commands to each one. the location in register memory of the Assign Monitor Datagram (header plus data) to be sent. (See register n, below).

Length of message (1 byte).

Command code:

Lower byte:

Upper byte:

08 (hex) for Assign Monitor Datagmm

20 (hex) for normal priority, or

A0 (hex) for high priority

Content of the Assign Monitor Datagram

Message length for the Assign Monitor message is 1 byte.

Register n:

The least significant byte of this reference contains the Device Number of the bus interface module which will receive the fault reports.

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Datagrams

GFK-017

1

Write Device Datagram

To send up to 128 bytes of register data to register or I/O memory in another CPU on the bus, use the

Send Datagram command to send a Write Device Datagram.

Command Block for the Write Device Datagram

Register 1:

Register 2:

Register

3:

Register 4:

Register 5:

Register 6:

Register 7:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Command Number 12 (Send Datagram)

Status code (supplied by the CPU). If the message is sent to one device, it is a non-immediate command the status register will indicate “done” when that device acknowledges the message.

However,‘if FF is specified in register 4, the command is immediate; register 3 is set to “done” as soon as the message is sent, with no guarantee that the devices have received the message.

Device Number of the bus interface module to which the Datagram will be sent. To broadcast this message to all devices on the bus, enter FF (hex) in this register.

Location in CPU memory of the Write Device Datagram to be sent. (See register n, below).

Length of message in bytes up to 134. This is equal to the number of data bytes (up to 128) plus 6 header bytes.

Command code:

Lower byte:

Upper byte:

20 (hex) = Write Device &tagram

20 (hex) for normal priority

A0 (hex) for high priority

Content of the Write Device Datagram

Register n:

Register n+l:

Register n+2:

Register n+3:

Lower byte must be 00 hex. Upper byte contains 2 least significant hex digits of the absolute memory address (see below) in the destination CPU where the data will be placed.

Lower byte contains 2 most sign&ant hex digits of the destination CPU absolute memory address. Upper byte must be 00 hex.

Lower byte must be 80 hex. Upper byte is data length in bytes.

First register of data (may be up to 64 registers total).

Register n msb 1Sb

Al

1 00

I

Register n+l msb lsb

1 00 1

40

Register msb

1

02 n+2 lsb

1 80

I

I

Must be 80 hex

Data length in bytes

2 most significant hex digits of address

Must be 00 hex

Must be 00 hex

2 least sig. hex digits of address

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Datagrams

GFK-0171

Specifying the Address of the Other CPU

The Command Block for a Write Device, Write Point, or Read Device Datagram must specify the address of the receiving CPU or computer in terms

of absolute memory.

If the receiving device is a

Series Six PLC, a target location in either register memory or I/O Status Table memory can be specified

(however, the source of the data in the sending Series Six PLC must always be register memory). For another type of PLC or computer, refer to the documentation supplied with its bus interface module.

\

\I

Be sure the CPU address specified is for the register table (first hex digit will be 4-7) or the

I/O Status Table (first hex digit will be 2). Writing CPU data to any other absolute memory location may cause potentially hazardous control conditions.

SERIES SIX MEMORY TYPE

X/O Status Table

Register Memory

OutjNlts

Inputs

ROOOOLR16384

I

I

ABSOLUTE

ADDRESS

DECIMAL 1 HEXADECIMAL

08192 - 08319

08320 - 08447

16384 - 32767

2000 - 207F

2080 - 20FF

4000 - 7FFF

I

1

The absolute address in decimal for any register is equal to 16383 plus the register number. For example:

Register number (R3000)

Add 16383

Decimal absolute address

3000

+16383

19383

To find the hexadecimal equivalent of this number using the Logicmaster 6 software:

1

.

When entering the co mmand block, place the work area in decimal format by pressing the

Shift ad

Dee keys. Then, enter the value you want to convert to hex. For example:

DEC

19383

2

.

Convert the work area to hex format by pressing the Shift and Hex keys. The screen displays the hex equivalent of the number:

HEX

4BB7

Enter this hex value into the registers as explained previously. For Write Device, it would be

entered

like this:

Register n

2 1

I

B7

1 00 1

Register n+l

2 1

00 [

4B

Register n+2

2

1

1

02 1 80

1 = lsb

2 =

msb two least significant digits two most significant digits

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Datagrams

GFK-017 1

Example Ladder Logic for

a

Write Device Datagram

This logic uses a Write Device datagram to send two bytes of data from one CPU to another. The

DPlXEQ contains the address of the resident Bus Controller (513 + 1000 decimal). The other CPU must include logic in its application program to receive the Datagram.

<< RUNG 1 >>

***********************************************************************************

* Rung 1 uses a one-shot to initialize the program. The output 00042 will be used*

* as a permissive in subsequent rungs. The datagram is only sent once; to send a *

* new datagram, the status byte should be cleared and set to zero.

************************************************************************************

*

1 11008 00042

(0s)

<< RUNG 2 >>

***********************************************************************************

* Rung 2 uses output 00042 (from rung 1) to initiate loading the Command Block

*

RO29O:Bus Controller address +lOOO (1513)

*

R0291:Command Number 12 (Send Datagram)

*

RO292:Communications status

*

*

*

*

*

RO293:Device Number of second Bus Controller (31)

*

*

R0294:Pointer to the location of the Write Device datagram to be sent

*

*

*

*

RO295:Length of the Write Device datagram (2 data bytes + 6 header bytes)*

RO296:Command Code. Lower byte = 20 hex for Write Device datagram

*

Upper byte = 20 hex for normal priority

***********************************************************************************

*

+ --

00042

1 [

--a

C

ROO290

BLOCK MOVE

+01513 +00012 +ooooo +00031

+00350 +00008 +08X4

l- ( 1

<< RUNG 3 >>

***********************************************************************************

* Rung 3 contains the Write Device header (RO350-R0352). First two registers

*

* (RO35O and R0351) contain the absolute memory address of the destination CPU.

*

* Third register is data length in bytes (not counting header)( then 80 hex.8

*

* Enter these three registers in hex.

*

The example hex entries look like this:

*

*

*

*

Al00 0040

0280

+ooooo +ooooo +ooooo +ooooo

* Pressing the Accept key converts them to the decimal values shown below.

* RO353 contains the actual data to be sent (22222 decimal).

***********************************************************************************

*

*

*

*

+ --

00042

1 t aLO

E

R00350

BLOCK MOVE l-

-24320 +00064 +00640 +22222 +OOOOO +OOOOO +OOOOO

( )

<< RUNG 4 >>

***********************************************************************************

* DPREQ opens the communications window. It should be tied to the left rail.

***********************************************************************************

RO290

+[DPREQ]-

( 1

*

<< RUNG 5 >>

+[ENDSW]-

,_

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6-10

Datagrams

Write Point Datagram

The Write Point datagram is used to set or reset up to

16 individual bits of data in another CPU. The target address must be specified in terms of absolute memory (see Write Device). Do not send a Write

Point datagrarn to a Series 90-70 PLC. Use a Write Device datagram to bit memory instead.

Setting the Mask Bits

Changes are made to the specified 16 bits by setting the corresponding bits in the AND mask and the

OR mask (see above).

A. To set a bit to 0:

1. set the corresponding AND bit to 0, and

2. set the corresponding OR bit to 0.

B. To set a bit to 1:

1. the corresponding AND bit may be either 0 or 1,

2. the corresponding OR bit MUST be 1.

C. To keep all other bits the same (no change):

1. set the remaining AND bits to 1, and

2. set the remaining OR bits to 0.

Example

1010 0000 0101 0000 originaldata

1

0

1

intended bit changes

1111 1101 1110

0000 0070 OOOG

1111

-

AND mask

OR mask

Notice that the AND mask bits for bits 7 and 15 are not the same. When setting a bit to 1, its

AND mask bit canbe either 0 or 1.

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Datagrams

GFK-017 1

Command Block for the Write Point Datagram

6-11

Register 1:

Register 2:

Register 3:

Register 4:

Register 5:

Register 6:

Register 7:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Command Number 12 (Send Datagram)

Status code (supplied by the Bus Controller). If the message is sent to one device, command execution is immediate; the status register will indicate “done” when the device acknowledges the message. However, if FF is specified in register

4, command execution is non-immediate; register 3 is set to “done” as soon as the message is sent, with no guarantee that the devices have received the message.

Device Number (serial bus address) of the bus interface module that will receive the Datagram. To broadcast the message to all devices on the bus, enter FF (hex) in this register.

Location in register memory of the Write Device datagram. (See register n, below).

Length of message (9 bytes).

Command code:

Lower byte:

Upper byte:

OB (hex) = Write Point datagram

20 (hex) for normal priority

A0 (hex) for high priority

Content of the Write Point Datagram

Register r~

Register n+l

Register n+2

Register n+3

Register n+4

Lower byte must be 00 hex. Upper byte contains 2 least significant hex digits of the absolute memory address in the destination CPU where the data will be placed. See “Write Device

Datagram” for instructions on specifying absolute memory addresses.

Lower byte contains 2 most significant hex digits of the destination CPU absolute memory address. Upper byte must be 00 hex.

Lower byte must be 80 hex. Upper byte: AND mask for bits O-7. For the AND mask, set to 0 any bits to be changed. Set to 1 alI other bits.

Lower byte: OR mask for bits O-7. For the OR mask, set to the desired state any bits to be changed Set to 0 all other bits. Lower byte: AND mask for bits 8-15.

Upper byte: OR mask for bits 8-15

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6-12

Datagrams

GFK-0171

Read Device Datagram

To read I/O or register data from another CPU and place it in register memory, use the Receive

Datagram command to send a Read Device datagram.

Command Block for the Read Device Datagram

Command Block format for the Read Device Datagram is:

Register 1:

Register 2:

Register 3:

Register 4:

Register 5:

Register 6:

Register 7:

Register 8:

Register 9:

Register 10:

Bus Controller Reference Number (plus 1000 for a DPREQ)

Command Number

13

(Receive Datagram).

Status code (supplied by the Bus Controller).

Destination Device Number (serial bus address).

Pointer to the first register of the data buffer in the CPU for the Read Device Datagram header. (See register n, below).

Length of the Read Device Datagram header, which is always 6 bytes.

Command code: Lower byte must be 1E hex, upper byte is 20 hex for normal priority or A0 for high priority.

Pointer to the first register of the data buffer in the CPU where the reply message is placed. (See register m, below).

Length of reply message in bytes up to 134. This is equal to the number or data bytes (up to 128) plus header. The Bus Controller supplies this information; it is not necessary to enter a value.

Command code: Lower byte must be 1F hex, upper byte must be 20 hex.

Content of the Receive Datagram Header

When the Read Device Datagram executes, the group of registers beginning at the location specified by register 8 (above) must contain the following information:

Register n

Register n+l

Register n+2

Lower byte must be 00 hex.

Upper byte contains 2 least significant hex digits of the source CPU absolute memory address the data will be read fi-om. See “Write Service Datagram” for instructins on specifying absolute memory addresses.

Lower byte contains 2 most significant hex digits of the source CPU absolute memory address.

Upper byte must be 00 hex.

Lower byte must be 80 hex. Upper byte is data length in bytes (hex).

Content of the Reply

Data returned by the Read Device Datagram has the following format. The content of the frst three registers of the reply is the same as the Receive Datagram header (above).

Register m

Register m+l

Register m+2

Register m+3

Lower byte must be 00 hex.

Upper byte contains 2 least significant hex digits of source CPU absolute memory address.

Lower byte contains 2 most significant hex digits of source CPU absolute memory address.

Upper byte must be 00 hex

Lower byte must be 80 hex Upper byte is data length in bytes (hex).

First register of data conten, up to 64 registers total.

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Datagrams

643

GFK-0171

Example Ladder Logic for the Read Device Datagram

This

logic uses a Read Device datagram to read two bytes of data from another CPU. The DPREQ contains the address of the resident Bus Controller (513 + 1000 decimal). The ladder logic for the other

CPU must include a communications instruction with the address of its Bus Controller to be able to provide the data requested.

I:

Start of Program ]-

<< RUNG 1 >>

***********************************************************************************

* Rung 1 uses a one-shot to initialize the program

* as a permissive in subsequent rungs. The datagraxn is only sent once;

* new datagram,

The output 00042 will be used* the status byte should be cleared and set to zero.

*******************************

*********************************************** to send a *

******

*

042

OS)

<< RUNG 2 >>

***********************************************************************************

* Rung 2 uses output 00042 (from rung 1) to initiate loading the Command Block.

*

RO29O:Bus Controller address +lOOO (1513)

*

R0291:Comrnand Number 13 (Receive Datagram)

*

RO292:Communications status

*

RO293:Device Number of second Bus Controller (31)

*

R0294:Pointer to the location of the Read Device header (RO350)

*

R0295:Length of the Read Device header in bytes (always 6)

*

R0296:Comnand Code. Lower byte = 1E hex for Read Device datagram

*

Upper byte = 20 hex for normal priority

*

2OlE hex = 8222 decimal

***********************************************************************************

*

*

*

*

*

*

*

*

*

*

+--I

00042

[--- [

ROO290

BLOCK MOVE

+01513 +00013 +ooooo +00031 +00350

+00006 +082X

I- ( 1

<<

RUNG

3 >>

***********************************************************************************

*

Rung 3 contains the Read Device header (RO297-R0299). First register is the

* address where the received data will be placed. Enter this in decimal.

The

* second register is the data length; this value will be supplied by the Bus

* Controller.

Enter the third Block Move register in hex: 2OlF.

Pressing the

* Accept key converts it to the decimal value shown in R0299 below.

***********************************************************************************

00042

+ -- 1 1 --- C

ROO297

BLOCK MOVE

1

+00350 +OOOOO

+08223 +OOOOO +OOOOO

+OOOOO +OOOOO-

( 1

*

*

*

*

*

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6-14

Datagrams

GFK-0171

<<

RUNG 4 >>

**********************************************************************************

*

Rung 4 is entered in hex format. Registers RO350 and RO351 contain the

* destination device absolute address in hex (40 Al hex = register R0162)

*

R0350: Al 00 hex = -24320 decimal

*

Lower byte = 00 hex

*

Upper byte = destination device absolute address byte 1 (LSB

*

Al hex in this example

*

R0351:

00 40 hex = 0064 decimal

*

Lower byte = destination device absolute address byte 2 (MSB)

*

40 hex in this example

*

Upper byte = 00 hex

*

R0352: 02 80 hex = 0640 decimal

*

Lower byte = 80 hex

*

Upper byte = 02 hex, length of data (2 in this example)

*

The example hex entries look like this:

*

*

Al00

0040 0280

+ooooo +ooooo +ooooo +ooooo

*

*

Pressing the Accept key converts them to the decimal values shown below.

**********************************************************************************

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

* r-l

00042

1

C

R00350

BLOCK MOVE

1

-24320 +00064 +00640 +OOOOO +OOOOO +OOOOO +OOOOO-

( 1

<< RUNG 5 >>

**********************************************************************************

*

DPREQ opens the communications window.

It should be tied to the left rail.

*

**********************************************************************************

RO290

&DPREQ]-

<< RUNG 6 >>

+[ENDSW]-

<< RUNG 7 >>

+[ENDSW]-

( )

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GFK-0171

This chapter explains how to program Global Data communications between CPUs on the same bus.

If registers in one CPU are required as data by any other CPUs on the bus, and the data must be constantly updated, use Global Data. Attempting to transfer register data using repeated Datagram messages will have a negative impact on system features, as previously described.

Each interface module can send Global Data to all other interface modules on the bus. A Global Data message may consist of up to 128 bytes of register data. Each interface module will receive all Global

Data on the bus.

Global data differs from the Read Device and Write Device Datagrams (which can also be used to send

128 bytes of data) in several ways:

1 .

Global Data is used for automatic and repeated register data transfer; Datagrams are used to send specific messages.

2

.

After being initialized in the program, Global Data will be sent by the Bus Controller repeatedly, with minimal additional programming (Idle co mmand) required. Each Datagram requires a DPREQ or WINDOW instruction both to send and to receive, and status must be monitored.

3

.

The Bus Controller sends all the Global Data it has received to the CPU once each CPU sweep.

This requires only one DPmQ or

WINDOW

instruction to the Bus Controller. For Datagrams, each message received requires a separate window command to transfer the embedded data to the

CPU.

4

.

Global Data cannot be read from or written to I/O memory (Datagrams can).

A Global Data message is always associated with a specified memory address in the sending CPU. If the receiving device is a Bus Controller in a Series Six PLC,

the

data is placed into the same registers it occupied in the sending CPU. (For this reason, Global Data

cannot be sent by two

or more Bus

Controllers in the same Series Six PLC. The second Bus Controller in the PLC would always write

Global Data received from the first into the same registers it was sent from, so the data in those registers would never change.) In this example, there are three Series Six CPUs on the same bus. Each CPU sends 16 registers of Global Data to both of the other CPUs.

/_1 I_1 ]I

Ol+OOOl

0001

0001

0256

0256

0256

+ t- f-

0001

0001

0256

0256

+

_j f-

0001

0001

0001

0256

0256

0256

If the receiving device is a bus interface module in another type of CPU, the data may be stored differently.

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Global Data

GFK-0171

Programming to Send Global Data

If the Bus Controller will send Global data, use a Write Configuration command to the Bus Controller.

Contents of the Command Block are shown below. For more information about using the Write

Configuration command, see chapter 5.

Global Data transmission will start, stop, or change 1.5 seconds after the command. During this 1.5 seconds, the Bus Controller’s second LED goes off, and no outputs are updated. This occurs only when there is a Global Data command, not during routine transmission of Global Data.

Command Block for the Write Configuration Command to Send Global Data

The Command Block format for Global Data is:

Register 1: Bus Controller Reference Number (plus 1000 for a DPREQ)

Register 2: Command number 3

Register 3: Status Code

(supplied by the CPU)

Register 4:

Ten bit Reference Number of the resident Bus Controller (l-1024).

Register 5:

Pointer to the first register where the configuration data for Bus Controller begins.

The CPU location and length of data to be transferred using Global Data are determined by the content of the last two registers of the Bus Controller configuration table (stored in the Bus Controller).

23 22 1

I I

Configuration data

Global Data address

Global Data length in bytes

Registers 1-21 contain configuration data, as described earlier (see “Data Returned by a Read Configur- ation Command to a Bus Controller” in chapter 5). Register 22 must contain the Global Data address.

The address specified is the same for all the sending and receiving CPUs. At powerup, the BUS

Controller defaults register 22 to FFFF hexadecimal, which indicates no Global Data to be sent.

Register 23 should contain the number of bytes up to 128 (registers times 2) to be broadcast by the

BUS

Controller. At powerup, the Bus Controller defaults register 23 to

0.

Starting Global Data

To start Global Data, the beginning Global Data address and the message length should be loaded into registers 22 and 23, respectively, of the Bus Controller configuration table. The ladder logic for Global

Data only needs to be executed once. After that, Global Data will be transferred between CPUs automatically and repetitively unless stopped, as described below.

Stopping Global Data

Global Data can be stopped by loading register 22 in the data buffer (R0322 in the example that follows) with the hexadecimal value FFFF and resetting the status register to 00. The status register (third register in the Command Block) should always be cleared before executing any new communications command.

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Global Data

GFK-017 1

Example Ladder Logic for Global Data

The ladder logic that follows is an example of programmin g Global Data. This program initiates Global

Data transfer of two bytes of data. The Global Data address for both CPUs is ROOOl.

+I

Start of

Program

<< RUNG 1 >>

]-

* Rung 1 uses a one-shot to create permissive logic used to load the Command *

*

Block and data registers in subsequent rungs.

********************************************************************************

*

11008

1 1 -----------------------------------------------------------------------

<<

RUNG 2 >>

00042

(0s)

********************************************************************************

* Rung 2 contains the Write Configuration command block:

*

*

RO290 = Bus Controller I/O reference (+ 1000 decimal)

*

*

RO291 = Command Number (3)

*

*

RO292 = Communications status (supplied by CPU)

*

*

RO293 = I/O reference of the Bus Controller. This is the same as *

*

RO290 above, except that

1000 is not added for a DPREQ. *

*

RO294 = Pointer to the first register of the data storage

* buffer in the CPU (in this example, RO301).

********************************************************************************

*

*

00042

1 1 --- [

ROO290

BLOCK MOVE 1

+01513 +00003 +ooooo +00513 +00301 +ooooo +ooooo-

( >

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Global Data

GFK-0171

<< RUNG 3 >>

**********************************************************************************

* Rung 3 contains registers 22 (R0322) and 23 of the Bus Controller configuration*

* table. Register R0322 contains the Global Data address (ROOOOl).

R0323

*

*

* contains the number of data bytes to be transferred (2).

**********************************************************************************

000'42

1 [: em- C

RO0322

BLOCK MOVE 1

+00001

+00002 +ooooo +ooooo +ooooo +ooooo +ooooo-

( )

<< RUNG 4 >>

**********************************************************************************

* Rung 4 can be used to stop the Global Data transfer. If 10009 passes power to *

* the right, the value FFFF hex will be moved into R0322 beginning Global Data

*

* address register. Then the value 00 is moved into RO292 communications status. *

**********************************************************************************

10009 Const

1 c -w-w C

A

FFFF

MOVE

RO0322

B ]-------[

Const

A

0000

MOVE

ROO292

B l-

<< RUNG 5 >>

**********************************************************************************

* DPREQ instruction opens the communications window.

It should be tied

* to left rail.

**********************************************************************************

( 1

*

*

1

RO290

+[DPREQ]-

( )

<< RUNG 6 >>

**********************************************************************************

* Rungs 6 and 7 implement the increment counter in ROOOl, which is transmitted

* on the bus as Global Data.

**********************************************************************************

*

* f

Const

+[

A

+0001

MOVE

<<

RUNG 7 >>

B

ROOOl

+[ A +

R0288

B

=

ROOOl

C l-

<<

RUNG 8 >>

RO0288 l-

( )

( )

<< RUNG 9 >>

+[ENDSW]-

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Global Data

GFK-017 1

Programming to Receive Global Data

For the Series Six PLC, all incoming Global Data is transferred from the Bus Controller to the CPU during the first open window to the Bus Controller that occurs during the CPU sweep. If the application program does not contain any commands to open a window between the CPU and the Bus Controller, window must be opened. An Idle command can be used.

a

Be sure registers used for both outgoing and incoming Global Data are not assigned to any other use in the program, even if the CPU will not make use of Global Data it receives. If another device on the bus sends Global Data, it will always be received if the program opens a window to the Bus Controller

(using a DPREQ or WINDOW instruction or the Computer Mailbox).

Maximum CPU Sweep Time Increase for Global Data

The Bus Controller will send all incoming Global Data to the CPU each sweep if the application program opens a window to the Bus Controller.

If there are active window commands to the Bus

Controller, there is no way for the Bus Controller to receive only part of

the

Global Data on the bus. It is possible to keep a CPU from receiving Global Data by completing all communications tasks during the startup period, then disabling the window commands during system operation. Datagrams may be preferable to Global Data in applications where the CPUs do not require all of the register message data on the bus.

The impact of incoming and outgoing Global Data on the CPU sweep can be estimated by adding all of the Global Data bytes sent and received for each bus in the Series Six PLC system:

FOR EACH BUS: total Global Data Bytes Sent x .031mS =

+

+

+

total Global Data Bytes Received total number of Global Data messages

X

X

.031mS =

.omms =

1.20 mS =

=

GLOBAL DATA mS

Using Global Data to Check CPU Operation

Global Data is sometimes used to set up a “heartbeat” between two CPUs on the bus, enabling each to check the operation of the other. For this technique to work successfully, the sweep times of both CPUs must be

similar. In

addition, these CPU sweep times must be approximately twice as long as the

scan

time of

the

bus that connects the CPUs.

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Chapter

8

Programming for Diagnostics Using Bus Controller Input

References

GFK-0171

This chapter shows the format of the diagnostic data provided by the Bus Controller. You will not need this information if you are using the automatic diagnostics features of the Logicmaster 6 software. If the

Logicmaster 6 software Expanded Functions are enabled as described in the chapter 4, the

CPU can access this data automatically, and lengthy programming can be avoided.

The following diagnostic information is available from the Bus Controller:

Bus Controller OK

S&al Bus Error

I/O Circuit Fault

Loss

or Addition of Block

Address Conflict

Pulse Test Active

HHM Force Active

(all Bus Controllers)

(all Bus Controllers)

(Bus Controller with Diagnostics)

(Bus Controller with Diagnostics)

(Bus Controller with Diagnostics)

(Bus Controller with Diagnostics)

(Bus Controller with Diagnostics)

Program logic can be used to monitor this information. In addition, the program can use the BUS

Controller’s output references to clear faults or to disable outputs (see chapter 9).

Additional Programming for Diagnostics

In addition to monitoring the Bus Controller data described in this chapter, the ladder logic can obtain diagnostics data directly fkom devices on the bus using the Read Diagnostics command. See chapter 5 for more information.

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Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Bus Controller Input Reference Formats

A Bus Controller provides diagnostics data to the CPU in its assigned input references. The

format of

data in these references depends on whether the Bus Controller has diagnostics capabilities. Each diagnostic is available for exactly one CPU sweep.

Bus Controller without Diagnostics

A Bus Controller without diagnostics (IC66OCBB903) uses eight input references (one byte) to report status and the status of the serial bus to the CPU once each CPU sweep.

its

I

8

1

I

bits bit 1 = Bus Controller OK bit 2 = Bus Error

7

Of these assigned references, bits 3-8 are not used

Bus Controller with Diagnostics

A Bus Controller with diagnostics (IC660CBB902) uses 48 input references (six bytes). The

BUS

Controller places fresh diagnostic data in these references every CPU sweep.

.

48

E61

411

El

331

‘I’

Ml

251

I_

Circuit

Reference

Fault Type,

Circuit Number:

0 = block

1 = discrete

2= analog

PI

171

121

PI

byte number

91

-

-

-

-

1 I/O reference

I

bit 1 = Bus Controller

OK

bit 2 = Bus Error

bit 3 = Circuit Fault bit 4 = Loss of Block bit 5 = Addition of Block bit 6 = Address Conflict bit 7 = Pulse Test Active bit 8 = Circuit Forced

-

Input/Output

-

Fault Description

The program can monitor this data as explained below,

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Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Logic to Monitor Diagnostic Information

The

ladder logic can monitor the Bus Controller input references for faults, and use Source-To-Table

Moves or other program instructions to capture the data. A fault or system change is sent to the CPU for one sweep only. The Bus Controller buffers up to 60 faults and sends one at a time to the CPU every

CPU sweep. Thus, input status bits change each CPU sweep when faults exist.

To use this diagnostic data, the program should look first at bits l-8 of the Bus Controller input references. Bits 948 have meaning only if bit 3,4, 5, or 6 is set to 1. Bits 3-6 can be

1

for only one sweep of the CPU, and only one bit between 3 and 6 can be 1 at a time. Bits 1, 2, 7, and 8 are independent. They can be 1 or 0 regardless of the state of the other inputs. For example:

WI

411

Is1

331

WI

25)

PI

171

El

91

PI byte number

1

I/O reference bit 1 = 1,Bus Controller

-

Circuit

Reference of

-OK* bit

3 =

1,Circuit Fault

-bit 8 = 1,Circuit Forced

the Circuit

Fault bit

9 =

1,

Input circuit bit 10 =

0

Input

33 = 0,

Discrete block

Inputs

37-40 =

Number of the circuit

- Circuit Fault Description

Automatically cleared by the CPU if DIAGNOSTICS ENABLED is set to Y on the CPU

Configuration Setup Menu.

In this example, three bits in status byte 1 are currently 1.

They indicate that the Bus Controller is communicating with the CPU, at least one circuit is forced, and a circuit fault is being reported during

Status bytes 2 through 6 describe the circuit fault.

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Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Monitoring Bus Controller Status

Bus Controller input reference bit 1 (the least significant bit) indicates the status of the Bus Controller.

It is set ON within one second of power-up if the Bus Controller passes its self-test.

I:

Byte 1 1

Bus Controller OK

If this bit fails to become 1 at powerup and remain 1 with power applied, the Bus Controller may need to be replaced. If bit 1 is 0, none of the other Bus Controller input reference bits have meaning.

The way the program can monitor the Bus Controller status data will depend on whether DIAGNOS-

TICS ENABLED has been set to Y on the CPU Configuration Setup Menu, and whether the Bus

Controller is included within the range of I/O specified for diagnostics scanning.

Monitoring Bus Controller Status: Diagnostics is NOT Enabled

If the Bus Controller is not set up for automatic diagnostics as defined

1 once every CPU sweep then clear it using a Bit Clear instruction. above, the ladder logic can test bit

Monitoring Bus Controller Status: Diagnostics IS Enabled

If the BUS Controller is set up for automatic diagnostics, the CPU automatically checks bit 1 during the diagnostics portion of the sweep.

EXECUTIVE

WINDOW

PROGRAM

LOGIC

SOLUTION

I

I/O

SCAN

I

DIAGNOSTICS

I

CLEAR BUS

CONTROLLER

OK

BIT (bit 1)

6 Bit 1 checked here

< Bit 1 cleared here

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Programming for Diagnostics Using Bus Controller Input References

GFK-017 1

If bit 1 is 1 (indicating that the Bus Controller has passed its self-test), the CPU

automaticah clears it

at the end of the CPU sweep. This sequence of diagnostics and bit clearing by the CPU mea& that bit 1 will always appear to be 0 during the program logic solution part of the sweep. Therefore, if automatic diagnostics are enabled for the CPU, program logic cannot monitor input reference bit 1 to determine the status of the Bus Controller.

However, the program can monitor the status of Bus Controller output bit

33

.

Monitoring

Bus Controller

Status

using the

Bus

Controller OUTPUT Bit 33

A Bus Controller with Diagnostics uses 48 references in the output table. Of these 48 references, bits 1 through 32 are used to send commands to I/O blocks:

I41 131 c21 fll

byte number

32 251

171

91 1 bits

I_

Circuit

Reference bit 1 = Disable Outputs

bit 2 = Clear All Faults

bit 3 = Clear Circuit Fault

bit 4 = Pulse Test

I_

bits 9-16 = Inputs-only

block

If DIAGNOSTICS ENABLED is set to Y on the CPU Configuration Setup Menu, the CPU also reserves

Bus Controller output reference bits 33 through 48 for diagnostics information. Of these additional 16 bits, only bit 33 and bit 34 are used:

I

48

411

bit 34 =

Serial Bus Error last sweep

I

33

‘I

bit 33 = Bus Controller

OK last

251

171 91

I

I sweep

1 bits

I

References Fault

I_

bit 4 = Pulse Test

bits 9-16 = Inputs-only

block

Before clearing Bus Controller input bit 1, the

CPU copies it into Bus Controller output bit 33. On the next sweep, if the Bus Controller fails to reset input reference bit 1 to 1, the CPU looks at output reference bit 33. If bit 33 was 1 on the previous sweep, a Bus Controller fault is triggered. If it was 0 on the previous sweep, no additional fault occurs

Because bit 33 is an accurate reflection of the Bus Controller state (on the previous CPU sweep), the program can monitor Bus Controller status by reading this bit. The program should NOT clear output bit 33.

I

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Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Checking for Bus Errors

To have the program detect errors such as an open bus or excessive noise in the bus, use logic to monitor bit 2 of the Bus Controller input references.

’ “5’ / Serial Bus Error

1

This bit is normally set to 0; it is set to 1 if:

1

. the Bus Controller receives ten or more corrupted messages within a lOosecond time period. It will be set to 0 again when the error rate continuously set to 1, there are multiple b errors from one or more devices. The bus may continue to operate in spite of these errors. falls below ten errors in a lOosecond period. If bit 2 is

2

. the Bus Controller does not obtain its turn on the serial bus at least once every 5OOmS. This bit is 1 for at least one scan. It is set to 0 if the Bus Controller is able to transmit data on two successive scans.

If bit 2 is equal to 1 for several scans, it means the

Bus

Controller cannot access the bus due to duplicate

Device Number assignment, or bus scan greater than 5OOmS.

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Programming for Diagnostics Using Bus Controller Input References

GFK-017 1

Detecting I/O Circuit Faults

A Bus Controller with Diagnostics uses input reference bit 3 to report circuit faults.

Note that circuit diagnostics are obtained

from

devices on the bus that have been assigned Reference Numbers in II0 memorv. Automatic diagnostics are NOTper$ormed on devices assigned Reference Numbers in register memo& See chapter

3

for more information.

j Circuit Fault

j

For each fault reported, bit 3 is set to 1 for one sweep

. references contain the following information:

When this bit is 1, the other Bus Controller input

[:a

El

411 371 331

I41

251

PI

171

PI

91

PI byte

number

I31 II bit (I/O reference)

l-

I

bit 3 =I,

Circuit Fault bit 9 = 1, input reference affected bit 10 = 1, output reference affected

I_

bits 17 - 24 = least significant 8 bits of reference (within channel) bits 25 - 32 = most significant 2 bits of reference (within channel) bits 37-40 = relative circuit number on the block. bits 41 48 = Circuit fault type

Bits

9

through 16 indicate whether input or output references (or both) are affected. If bit 9 is 1, the circuit is an input. If bit 10 is 1, the circuit is an output.

If both are 1, the circuit is an output with feedback, or the fault affects an entire block which is configured as a combination block.

16~15~14~13~12~11~10~ 9

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Programming for Diagnostics Using Bus Controller Input References

GFK-0171

If the fault is a circuit fault, bytes 3 and 4 of the Bus Controller input reference of the circuit (l-1000) within the channel.

references contain the I/O

I

I/O Reference:

Least Significant

8

bits

"/'T' ;[," &ef;rence: Most Significant 2 bits

For an analog or RTD block, the circuit is identified by the first six references assigned to the block.

The following example shows circuit identification for a 4 Input/2 Output Analog block that

starts at

I/O references 10801 and 00801):

Analog circuit

Input circuit

1

Input circuit 2

Input circuit 3

Input circuit

4 output circuit 1 output circuit

2

I/O Reference

Starting reference

Starting reference plus 1

Starting r(eference plus 2

Starting reference plus 3

Starting reference plus 4

Starting reference plus 5

Value

0801

0802

0803

0804

0805

0806

Byte 5 contains the block type and relative circuit number of the circuit where the fault has occurred0

Content of bytes 5 and 6 depends on the block type specified in bits 33-36. If bits 33-36 are all 0, the fault is in the EEPROM in the block’s Terminal Assembly.

[ Brte

5 1

I lo

0 0

0’

Fault in block EEPROM not used

For a discrete block: bits 33-36 will be: 0 0 0 1 or 1 0 0 1.

If

a fault

has occurred on one of the upper sixteen circuits of a 32-point block, bits 33-36 are set to: 1 0

0 1 l

To find the correct relative number of the circuit, add 16 to the value in bits 37-40 (see below).

IIOol

IO

0 0 1

Discrete circuit fault on circuits

Discrete circuit fault on circuits

Relative circuit number

l-16

17-32

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Programming for Diagnostics Using Bus Controller Input References

GFK-0131

Bits

37-40

contain the relative number from 0 to 15 of the circuit where the fault occurred. The value zero represents the topmost circuit on the block. The higher value is the bottom circuit on the block (for example, 7 for a &circuit block).

For analog blocks: Bits 33-36 indicate the block type. Bits 37-40 indicate the relative circuit number

(0 to n for inputs, 0 to n for outputs) where the fault occurred.

[ Byte 5

1

40139138137136135(34133

lo

0 10

010 0 circuit fault on 4 In/Z Out Analog block circuit fault on RTD or Thermocouple block

Relative circuit number (O-n)

For the 4 Input/2 Output Analog block, bits 9 and 10 indicate whether the circuit is an input or output.

Input circuits are numbered O-3. Output circuits are numbered 0 and 1.

Fault Type

If the fault is a circuit fault, bits 41 to 48 of the Bus Controller input references identify the fault type.

The meaning of these bits depends on whether the block is a discrete or analog block.

Fault type bits for a discrete block:

48147146145144143142141

I’

Loss of I/O power

I ’

I

'- Short Circuit

Overload

No Load Present or Open Wire

(outputs)

(inputs)

Overtemperature

Failed switch not used

Fault type bits for an analog block:

I

1 Byte 6 1

48147146145)44143142141

I ’

I

Input Low Alarm

Input High Alarm

Input Underrange

Input Overrange

Input Open Wire

Output Underrange or Input Circuit Wiring Error

Output Overrange or Internal Fault *

Input Circuit Shorted *

*

I

*

for RTD blocks only

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8-10

Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Detecting the Loss or Addition of a Block

To have the program detect the loss or addition of a block on the bus, use logic to monitor Bus

Controller input reference bits 4 and 5.

Loss of Block

Addition of Bloz

If bit 4 is 1, the Bus Controller has detected the loss of an I/O block that was previously operating.

If bit

5 is 1, the Bus Controller has detected the addition of a block to the bus. Either of these bits may be

1

for one CPU sweep for each detected loss or addition; they are never both equal to

1

at the same time. If either of these bits is equal to 1, the other Bus Controller input reference bytes describe the block that was lost or added.

Byte 2 indicates the block’s I/O type: all inputs, all outputs, or combination.

16~15~14~13~12~11~10~ 9

Input reference affected

Output reference affected

If 9 and 10 both = 1, block has both input and output circuits not used

Bytes

3

and 4 contain the block’s starting I/O reference:

24123[22121120119118117

I/O Reference: Least Significant 8 bits

E Byte 4

1

I/O Reference: Most Significant 2 bits

0 (not used)

Bytes 5 and 6 contain the number of input and output references used by the block. Byte 5 contains the number of input references used by the block.

[ Byte 5

1

Number of input references used by the block

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Programming for Diagnostics Using Bus Controller Input References

GFK-017 1

Byte 6 shows the number of output references used by the block.

48147146145144143142141

8-11

Number of output references used by the block

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8-12

Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Detecting Reference Number Conflict

If the program should check for possible assignment of duplicate or overlapping Reference Numbers, monitor bit 6 of the Bus Controller input references.

Bit reported.

6 is

set to 1 for one sweep for each conflict

\

1 Byte 1 1

81 71 61 51 41 31 21 1

.

Address Conflict

If bit 6 is 1, indicating a conflict, bits

(input

9

and 10 indicate whether the conflict involves input references

9

is 1) or output references (input 10 is l), or both inputs and outputs (both bits are ON).

[ Brte

2 1

Input reference affected

Output reference affected not used

Bytes

3

and 4 contain the lowest reference (O-993) involved in the conflict.

I Byte

3 1

I/O Reference: Least Significant

8 bits

I:

Byte 4 1

I

I

I’-’

I/O Reference: Most Significant 2 bits

0 (not used)

Byte 5 is the Device Number (the serial bus address) of the block that was not accepted. That block is left in a default state; no inputs are accepted and no outputs are activated.

Device Number

(l-31) of the block

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Programming for Diagnostics Using Bus Controller Input References

S-13

Byte

6

contains the Device Number (l-3 1) of the block that is already using the I/O references requested by the second block.

C Byte 6 1

,

~48~4~[46[45[44~;j~42~41~ o

Device Number

(l-31)

of the block using the I/O reference in conflict

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s-14

Programming for Diagnostics Using Bus Controller Input References

GFrs-0171

Detecting Execution of

a

Pulse Test

The program can periodically issue a command to Pulse Test discrete outputs on a bus (see chapter 6).

Additional program logic can monitor execution of the Pulse Test, and determine whether the Pulse Test has located any faults.

To check execution of the Pulse Test, monitor Bus Controller input reference bit 7.

‘I’

Pulse Test Active

Bit 7 is set for one CPU sweep after a Pulse Test is commanded by the CPU. It remains 1 until all discrete I/O blocks configured for the Pulse Test have completed the test.

To determine whether any faults have been generated as the result of a Pulse Test (Failed Switch, LOSS of I/O Power, Short Circuit, or No Load), monitor bit 3 (Circuit Fault).

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Programming for Diagnostics Using Bus Controller Input References

8-15

GFIS-017

1

Detecting

a

Force Condition on the Bus

The Hand-held Monitor can be used to force circuits, which removes them from program control. Such a force condition must also be removed with the Hand-held Monitor. The program can detect whether a force exists by monitoring Bus Controller input reference bit 8. If this bit changes to 1, the program can alert an operator that a forced condition exists on the bus. The operator can remove the force with

Hand-held Monitor.

a

‘I’

HHM Force Active

Bit 8 is equal to 1 if any discrete or analog circuit is forced. No indication is provided as to which I/O block or reference contains the force condition.

If forces or unforces occur while the CPU is in Stop mode, or while outputs are disabled to the block being forced or unforced, this bit may not reflect changes, and may not be accurate when the

CPU is

returned to Run mode, or when outputs to the block are enabled.

Some versions of block firmware are responsible for this effect.

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846

Programming for Diagnostics Using Bus Controller Input References

GHC-0171

Storing Diagnostic Information in CPU Registers

The

CPU will automatically create a fault table in register memory if DIAGNOSTKS ENlEKED is set to Y on the CPU Configuration Setup Menu (see chapter 4).

Alternatively, logic can be used to copy individual diagnostic reports from the

BUS

Controller’s input references as described below. Because of its complexity, this method is not recommended.

Creating Diagnostic Tables

The information in the Bus Controller input references changes each CPU sweep. The following example shows program logic to copy the content of these references to register memory.

Ladder Logic Example

This example logic captures and displays diagnostic information from one Bus Controller for which automatic diagnostics is would be needed.

not

enabled. For a system with multiple Bus Controllers, additional logic

The logic creates a table which will store up to 19 faults at a time. The logic monitors Bus Controller input reference bit 3 (Circuit Fault), bit 4 (Loss of Block), bit 5 (Addition of Block) and bit 6 (Address

Conflict). If any of these bits is equal to 1 during a CPU sweep, the program turns on an output which causes fault data to be logged into registers. The example program also monitors the Bus Controller OK and bus error bits, maintains an output which can be used to flash an indicator light, and clears the table pointer.

<< RUNG 0 >>

+E

Start of Program ]-

<< RUNG 1 >>

*****************************************************************************

* This program will monitor fault diagnostic information

from the BUS

* Controller and establish a fault table in CPU register memory. This

* program assumes the Bus Controller's starting address is

257.

*****************************************************************************

+[NO OP]-[NO OP]-[NO OP]-[NO OP]-[NO OP]-[NO OP]-[NO OP]-[NO OP]-[NO OP]- ( )

*

*

*

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8-17

Programming for Diagnostics Using Bus Controller Input References

GFK-0171

First, the logic checks the condition of the Bus Controller by monitoring Bus Controller input bit 1 (the

Bus Controller OK bit). This bit should always be equal to

1.

WI

byte number

48

161

411

El

WI

331

25

I

[31

1’1

PI

“\’

Reference

Fault Type,

Circuit Number:

0 = block

1 = discrete

2 =

analog

91

1 bits (I/O references)

-

bit 1 = Bus Controller

OK bit

2 =

Bus Error

(10257)

(10258)

bit

3 =

Circuit Fault

(10259)

bit 4 = Loss of Block bit bit

(10260)

5 =

Addition of Block

(10261)

6 =

Address Conflict

(10262)

bit 7 = Pulse Test Active bit

8 =

Circuit Forced

(10263)

(10264)

Input/Output

Fault

Description

The Bus Controller’s 48 assigned input references are 10257 through 10305, so bit 1 is located at 10257.

C<

RUNG

2 >>

*****************************************************************************

*

This rung monitors the Bus Controller OK bit from the Bus Controller and *

* the latched bus error output from the next rung.

If the Bus Controller *

* is NOT OK or if there are 10 or more bus communications errors within 10 *

*

* seconds, output 1 will indicate the problem by turning off.

*****************************************************************************

BUS

CNTRLR

OK BIT

BUS

ERROR

IO257 00904

1 1 -----

311 ~~~C~~~~~~~~~~~L~~~~~~~~~~~~~~~~~L~~~~~~~~~~~~-~----------~~

GENIUS

BUS

IS OK

00001

t )

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8-18 Programming for Diagnostics Using Bus Controller Input References

GFL0171

Rung 3 checks

for bus errors by monitoring

Bus

Controller input bit 2,

located at 10258.

<<

RUNG 3 >>

*****************************************************************************

* This rung latches the Bus Communications Error bit.

It will turn on if *

*

10 or

more errors occur within

10

seconds. Output 1 (Genius Bus OK) will *

* turn off if an error occurs.

(The previous rung). Can reset output 1 by *

* turning on input 1.

*

***~*************************************************************************

BUS COM

ERROR

BIT

I

IO258

RESET

BUS COM

ERROR

+

--

I0001

1

ERROR

BIT

1 IO258

BUS

ERROR

00904

[LATCH]---( L)

( )

( 1

( )

( )

( )

( )

ERROR

00904

[LATCH]---( L)

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LOSS OF

BLOCK

BIT

+--1

10260

[--4

ADD.

OF

BLOCK

BIT

10261

+--I [--+

ADDRESS

CONFLCT

BIT

IO262

+--I [--+

Programming for Diagnostics Using Bus Controller Input References 8-19

GFK-0171

Rung 4 checks for the presence of any I/O circuit fault by monitoring input bit 3 (10259), the addition or loss of a block (IO260 and 10261), or a reference number conflict.

<< RUNG 4 >>

*****************************************************************************

* This rung monitors the Circuit Fault bit, Loss of Block bit, Addition of *

* Block bit, and Address Conflict bit from the Bus Controller. If any of *

* these types of faults occur output 909 is turned on. This is

*

* used in the next several rungs to cause the fault information to be

*

*

* logged into registers.

*****************************************************************************

CIRCUIT

BUS

FAULT CNTRLR

BIT

OK BIT

10259 IO257

A FAULT

HAS

OCCURRD

00909

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s-20 Programming for Diagnostics Using Bus Controller Input References

GFK-0171

If a

fault occurs,

rung 5 creates a table of 19 registers.

Each register can contain the first 16 BUS

Controller input references for one fault.

<< RUNG 5 >>

*****************************************************************************

* Registers

101

through

119

store the first two input status bytes for each *

* of 19 possible faults. Each register can contain the following:

*

*

In each register: - bit 1 = Bus Controller OK

*

* bit 2 = Bus Error

*

* bit 3 = Circuit Fault

*

* bit 4 = Loss of Block

*

* bit 5 = Addition of Block

I

*

* bit 6 = Address Conflict

*

* bit 7 = Pulse Test Active

*

* bit 8 = Forced Circuit

*

*

*

* bit

9 =

Input bit 10 = output bits 11-16 = not used

If bits

9

and 10 are both on = *

Input and Output.

*

*

*****************************************************************************

A FAULT

BUS

HAS CNTRLR

OCCURRD OK BIT

FAULT

TYPE

STORAGE

+ w e

00909 IO257 ROOlOO

Const

1 [ ---[ SRC ADD-TO-TOP LIST

LEN]-

019

The

result of this rung is:

( )

RlOO pointer for RlOl - R119

RlOl fault 1 fault type

R102 fault 2

R103 fault 3 fault type fault type

/

R119 fault 19 fault type

The f’rrst register assigned by the Add-to-Top function is a pointer to the rest of the entries in the list.

The first fault information will be placed in RlOl.

These registers will show the fault type for each of the 19 faults.

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Programming for Diagnostics Using Bus Controller Input References

8-21

GFK-017 1

If a fault occurs, rung

6 creates another table of

19 registers. Each register in this table can contain Bus

Controller input references 17 - 32 for one fault. These references indicate the location of an I/O circuit fault.

<<

RUNG 6 >>

*****************************************************************************

* Registers 121 through 139 store Input Status bytes 3 and 4 from the Bus

* Controller for each fault that occurs.

This is the circuit reference

* number in binary.

*****************************************************************************

*

*

*

A FAULT

HAS

OCCURRD

]

00909

CIRCUIT

REF.

STORAGE

IO273 R00120

Const

SRC ADD-TO-TOP LIST

LEN]-

019

( 1

NOW, the assignment of register memory is:

RlOO

RlOl

R102

R103 pointer for RlOl - R119 fault

1

fault type fault 2 fault 3 fault type fault type

Rll9 fault 19 fault

type

Rl20 pointer for R121 - R139

R121 fault 1 location, if I/O circuit fault

R122 fault 2 location, if I/O circuit fault

R123 fault 3 location, if I/O circuit fault

,

R139 fault 19 location, if I/O circuit fault

*

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8-22

Programming for Diagnostics Using Bus Controller Input References

GFKO171

Shilady, rung 7

creates a table that stores additional infomation for each of the 19 faults.

<< RUNG 7 >>

*****************************************************************************

* Registers 141 through

159 store Input Status bytes 5 and

6 from the Bus

*

* Controller for each fault that occurs.

The first eight bits store

*

* whether the fault is internal to a block, a discrete circuit, or an

*

* analog circuit. Also the relative circuit number on the block is stored. *

* The second eight bits of each register are a description of what type

*

* of circuit fault occurred.

*****************************************************************************

*

A FAULT

HAS

OCCURRD

FAULT

DESCRIP

STORAGE

I

00909

IO289

R00140

--

SRC ADD-TO-TOP LIST

Const

LEN]-

019

( 1

Now, the assignment of register memory is:

RlOO pointer for RlOl - R119

RlOl fault 1 fault type

R119

1 fault 19 fault type

R120 pointer for R121 - R139

R121 fault 1 location, if I/O circuit fault

R139

1 fault 19 location, if I/O circuit fault

R140 pointer for R141 - R159

R141

I fault 1 fault description

R159

1 fault

19

fault description

I

I

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Programming for Diagnostics Using Bus Controller Input References

S-23

GFK-017 1

Rungs 8 through 12 of this example logic cause an indicator light to flash if any type of fault has occurred.

<< RUNG 8 >>

*****************************************************************************

* This instruction forces R23 to always contain

00000.

*****************************************************************************

*

ALWAYS

ZERO

1 Const

+c A

I

+ooooo

<< RUNG

MOVE

9 >>

ROO023

B

l-

( 1

*****************************************************************************

* This rung compares one of the storage list's pointers to determine if any *

* faults exist. If RX0 compares with the

00000 in

R23

no faults exist and *

* output

910 is turned on.

*****************************************************************************

*

CIRCUIT

REF. ALWAYS

STORAGE ZERO

FAULT

LIST

EMPTY

R0120 RO023

+[ A :

B l-

<< RUNG

10 >>

00910

( 1

*****************************************************************************

* If any faults are stored in the fault storage registers, R120 will not

*

* equal

00000 and output

910 will be off. This allows output 6 to flash on *

* and off to indicate that at least one fault exists.

*

*****************************************************************************

FAULT

LIST

EMPTY

FLASH

ON

00910 00905

GENIUS

FAULTS

EXIST

00005

( 1

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8-24 Programming for Diagnostics Using Bus Controller Input References

GFK-0171

I

<< RUNG la >>

*****************************************************************************

* This rung times the on portion of a flashing indicator light.

*****************************************************************************

*

\

+ -------------------------~---------~-----------------~-IC--------

FLASH

OFF

00906

+ -- 1 1 -----------------------------------------------------------

FLASH

ON

Const

00905

[PRESC] ---

(TT)

003

( )

( 1

R00002

( 1

( 1

( 1

( 1

<< RUNG 12 >>

*****************************************************************************

* This rung times the off portion of a flashing indicator light.

*****************************************************************************

*

FLASH

ON

00905

+ --

1 [ -----------------------------------------------------------

FLASH

OFF

00906

FLASH

OFF

Const

00906

[ PRESC] ---(TT)

003

R00003

( 1

( 1

( 1

( )

( 1

( 1

Rungs 13 and 15 are used to reset (clear) registers and the Bus Controller OK bit. Rung 14 turns off the

Bus Controller OK bit at the end of each sweep. This fix&on is performed automatically by

Logicmaster 6 software release 3.0 or later.

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Programming for Diagnostics Using Bus Controller Input References

GFK-017 1

<< RUNG

13 >>

*****************************************************************************

* This rung insures that all of the fault storage registers are cleared if *

* the CPU is restarted or if the fault list pointers are equal to

00000.

*****************************************************************************

*

POWER

UP

FAULT

TYPE

FAULT

TYPE

FAULT

TYPE

RESET STORAGE STORAGE STORAGE

1

00908

ROOlOO ROOlOO

ROOlOO

Const

+--I/[--+[ A EOR B = C

LEN

]-

060

( )

EMPTY

I I

[--+

<< RUNG 14 >>

*****************************************************************************

* This rung turns off the Bus Controller OK bit at the end

of

each CPU

*

* sweep so that the Bus Controller can turn it back on.

It is then checked *

* to always be on in the program above. If it is ever found to be off,

*

*

* output 1 is turned off to indicate the problem.

*****************************************************************************

BUS

CNTRLR

OK

BIT

Const

BIT CLEAR

IO257

MATRIX

Const

LEN]-

( )

<< RUNG

15 >>

*******************~*********************************************************

* This rung generates the power up reset pulse used in the program above.

*

* Output 908 is always on except during the first sweep of the CPU when it *

* is first powered up or restarted.

*

*****************************************************************************

POWER

UP

RESET

+[NO OP] ------------------------------------------------------------------

<< RUNG

16 >>

00908

( 1

8-25

<< RUNG

[ENDSW]-

17 >>

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8-26

Programming for Diagnostics Using Bus Controller Input References

GFK-0171

Displaying the Example Diagnostic Table

The

Display Register Tables function of the Logicmaster 6 software can be used to display the information currently in the fault table registers assigned by the example program logic. The Register

Tables display shows a full screen of register values in either decimal or hexadecimal format. Initially, register values are in decimal. Pressing the Change All (F7) key and the Hex Display (F3) key converts all values to hexadecimal:

REG

00100

00110

00120

00130

00140

00150

00160

00170

00180

00190

0200

00210

0002

0000

0002

0000

0000

0000

03E9

0002

03E9

0000

0000

0002

REGISTER

OlC3 0000

0000

OlC3

0000

0000

0000

0000

0000

0000

0002

0000

0000

0000

0x3

0000

0000

0000

0000 ooc7 oooc

0000

0000

0000

00101 (

0148

0000

0148

0000

0000

0000

0000

4420

0000

0000

0000

0148

0001

0000

0001

0000

0000

0000

0000

4924

0000

0000

0000

0001

0000

0000

0000

L/M OFFLINE

) EQUALS 0000001100000101

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0005

OFAO

0000

0000

003E

0000

003E

0000

0000

0000

0000

0000

0000

OFAO

0000

003E

0000

0205

0000

0032

0000

0411

0000

4074

0000

0000

0205

0000

00220

00230

00240

0000

0000

0002

0000

0000

OlC3

0000

0000

0000

DEC SIGNED HEX DBPREC

1DISPLY 2DISPLY SDISPLY 4DISPLY

0000

0000

0148

0000

0000

0001

0000

0000

0000

0000

0000

0000

0000

0000

003E

0205

0205

0000

TEXT

SDISPLY

FL PT CHANGE DISPLY

GDISPLY 7 ALL

8REF TB

-

0000

103051

0000

0031

0000

0801

0000

4074

0000

0007

0000

OOlE

0000

0000

0000

In addition to the Register Table display, the Mixed Reference Tables function could be used to create custom tables of register, I/O and text data. To create a Mixed Reference display, see

Sofnyare User’s

Manual

for instructions.

the Logicmaster 6

In the preceding example, register RlOO is the pointer to registers RlOl through R119, which store the fault types (see rung 5). The number currently in this pointer register is the number of faults that have occurred. Looking at register RlOO shows that two faults are stored in the fault table:

REC

00100

REGISTER

0x3 0000

00101 (

0148 0001

) EQUALS

0000

L/M OFFLINE

0000000000000010

0000 003E 0000 0000

2 faults

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Programming for Diagnostics Using Bus Controller Input References 8-27

GFK-017 1

Registers RlOl through R119 store the fault type for 19 possible faults. The information in these registers is copied from Bus Controller input references 1 through 16:

. bit

. bit

. brt

. bit

. bit

. bit

. bit

. bit

. bit

.

bit

1

2

3

4

5

6

7

8

9

10

=

Bus Controller OK

=

Bus Error

=

Circuit Fault

=

=

Loss of Block

Addition of Block

=

Address Conflict

=

=

=

=

Pulse Test Active

Forced Circuit

Input Ifbits 9 and 10 are both= 1,

Output Input and Output bits 11-16 = not used

Moving the cursor to RlOl would display its binary equivalent beside the word EQUALS:

I

I

REG

00100

REGISTER 00101 (

L/M OFFLINE

) EQUALS 0000001100000101

0002 OlC3 0000 0148 0001 0000 0000

003E 0000 0000

0205

00110 0000

0000 0000 0000 0000 0000 0000 0000

I

RlOl

This is the fault type information for fault 1:

EQUALS

0000001100000101

Bits 1,3,9, and 10 are 1, showing that the Bus Controller is OK (bit 1 is 1) and there is a Circuit

Fault

(bit 3 is 1). Bits 9 and 10 are both equal to 1, so the circuit with the fault is an output with feedback.

If the cursor were moved to R102, the binary content of Bus Controller input bytes 1 and 2 for the second fault would appear beside the word EQUALS:

EQUALS 0000001000000101

Bits 1,3, and 10 are equal to 1. The Bus Controller is OK and there is a Circuit Fault. Bit 10 is set to 1, showing that the circuit is an output.

Registers R121 through R139 each store Bus Controller input references 17 through

32

for one of the 19 faults (see rung 6). If a fault is an I/O circuit fault, its reference number will appear in the appropriate register.

Register

RlOl shows that fault 1 is a circuit fault. Its reference number would be stored in register

R121. In the previous screen illustration, the table was shown with hexadecimal values. Pressing the

Decimal Display (Fl) would show the content of register RlOl in decimal:

00049

I/O

reference of the I/O circuit having the fault

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8m28 Programming for Diagnostics Using

Bus

Controller Input References

ax-0171

Registers R141 through R156 can store the following information about each fault:

48 411

331 25)

PI

171

VI

91

WI byte number

1 bits (I/O references)

Fault Type,

Circuit Number:

0 = block

1 = discrete

2 = analog

I_

Fault Description

Fault 1 is an I/O circuit fault. Its fault type and description would be stored in R141. Moving the cursor to R141 would show the binary content of this register:

EQUALS 0000100000000001

Bit

33 (the

first bit shown in status byte 5), is equal to 1. That means the fault is on a discrete block.

The value 0 in bits 37-40 shows that the fault has occurred on the topmost circuit on the block. Finally, bit 45 is set to 1, showing that the fault is an OVERTEMPERATURE fault.

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9-l

Chapter

9

Programming Commands to I/O Blocks Using the Bus

Controller Output References

GFK-017 1

This chapter explains how setting or clearing individual Bus Controller output reference bits can:

Disable all outputs on the bus

Clear all faults

Clear faults on a specific circuit

Pulse Test discrete outputs

(all Bus Controllers)

(Bus Controllers with Diagnostics only)

(Bus Controllers with Diagnostics only)

(Bus Controllers with Diagnostics only)

Bus Controller Output References

The length and content of the Bus Controller output references depend on whether the Bus Controller has diagnostics capabilities.

Bus Controller without Diagnostics

A Bus Controller without Diagnostics (IC660CBB903) has 8 output reference bits. Only the first bit is used. Bits 1 to 32 are used by the Bus Controller directly.

El1 byte number bit 1 = Disable Outputs bits 2-8 not used

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Programming Commands to I/O Blocks Using the Bus Controller Output References

GFIL0171

Bus Controller with Diagnostics

A Bus Controller with diagnostics (IC660CBB902) has 48 output reference bits. The first four bytes are used for commands to the blocks. Bits 1 to 32 are used by the Bus Controller directly. Bits 33 and 34 are controlled by the PLC if the Bus Controller has been entered on the Logicmaster 6 software BUS

Controller Locations screen.

bit 34 = Serial Bus Error last sweep

_-

,

41 I

I

I- bit

33 =

Bus Controller OK last

25 I

91

331 s7 I

I

48

‘q’

IT--’

I-

Circuit

Reference

L sweep

-I

-

1 bits

I

bit 1 = Disable Outputs bit 2 = Clear All Faults bit

3 =

Clear Circuit

Fault bit 4 = Pulse Test

-

I

bits

35

to 48 reserved.

I

bits 9-16 = Inputs-only block

Bits 1 - 4ze used for commands. Bits

9 -

32 are used only for the Clear Circuit Fault command; they contain the circuit reference of the fault, and its I/O type.

Bit 33 can be monitored to detect a Bus ControlIer error (see chapter 8).

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Programming Commands to I/O Blocks Using the Bus Controller Output References

GFIS-017 1

Enabling or

Disabling all Outputs from the Bus Controller

Bus Controller output reference bit 1 can be used to enable or disable outputs to all I/O blocks on the bus. (To disable outputs on a block-by-block basis, see chapter 5).

81

71

61 51

41 31 21 1 bits

Disable Outputs

When this bit is set to 1, the blocks stop reLeivi.ng outputs and their I/O Enabled LEDs go off. Each output either defaults to a previously-selected state (or value), or holds its last state or value, depending on how the block has been configured. The Bus Controller still accepts input data from the blocks, which remain “logged on” to the system; no Addition of Block or Loss of Block diagnostic is generated.

When bit 1 is set to 0, the outputs begin to receive data and the

I/O

Enabled LEDs go on. Blocks will drive the new states/values as soon as new output data is received.

Pulse Testing Outputs

Pulse Testing checks the ability of discrete outputs to change state. It also checks the continuity of switching devices, power sources, wiring, interposing devices such as fuses, and output devices. The program can issue a Pulse Test command periodically (for example, once a day) to check outputs that seldom change state during normal system operation.

Executing a Pulse Test will not activate mechani- cal devices such as motor starters, relays, or solenoid valves.

However, blocks that do not control sensitive loads can be configured to ignore a Pulse Test command.

Pulse Testing can also be done using a Hand-held Monitor.

To have the program Pulse Test all discrete outputs on a bus, set Bus Controller output reference bit 4 to

1

.

WI

[31 E21

PI bytes

141 bits

I I

I bit 4 = Pulse Test

The Bus Controller will send the Pulse Test command to all discrete blocks on the bus. Discrete blocks that have been configured to disable Pulse Testing, inputs-only blocks, and analog I/O blocks will not perform the test.

The test will begin at the block with the lowest Device Number, and proceed as quickly as the CPU receives test complete signals through all I/O blocks up to device 3 1. The Pulse Test should cause outputs that are OFF to go ON and outputs that are ON to go OFF momentarily. If an output does not switch, a fault (Failed Switch, Loss of I/O Power, Short Circuit, or No Load) is generated. The Bus Controller then sets the appropriate diagnostic bits in its assigned input references for one CPU sweep per fault. After all blocks have completed the Pulse Test, Bus Controller input reference bit 7 (Pulse Test Active) is set to 0.

If output bit 4 were still equal to 1 when the Pulse Test finished, another round of Pulse Tests would start immediately. Because outputs should not be pulsed continuously, the ladder logic should set the

Pulse Test output bit (4) to 1 for one CPU sweep at a time. If repeated Pulse Testing is required, Pulse

Test cycles should be at least 5 minutes apart.

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Programming Commands to I/O Blocks Using the Bus Controller Output References

GFK-0171

Clearing all Faults on the Bus

To have the program automatically clear all faults on the bus and all circuit faults buffered in the Bus

Controller, set bit 2 for one CPU sweep. The bit must transition from 0 to 1 to clear faults.

WI PI PI [11

bytes

I I

121

bits

\

bit 2 = Clear All Faults

The Clear All Faults command causes the blocks to attempt to clear their faults once. If a fault condition

(for example, a short circuit) still exists, the fault is reported again.

Clearing a Specific Circuit Fault

To have the program automatically clear just one fault, set bit 3 for one CPU sweep. The bit must transition from 0 to 1 to clear the fault.

I

141

126

C

131 VI

bytes

Dl

PI

. .

I bits bit

3 =

Clear One Fault bit 9 = 1, circuit to be cleared is on inputs-only block

= 0, circuit to be cleared is on outputs-only block circuit reference

Use bit 9 to indicate whether the block has inputs only or outputs only. Bit

9 will be

ignored if

the

block has both input and output circuits.

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Programming Commands to I/O Blocks Using the Bus Controller Output References

GFK-017 1

Specify the circuit reference and the block’s I/O type in the remaining output references. 1tiividual

circuit faults can

be cleared for any block assigned a Reference Number

in II0 memory. Circuit faults on blocks assigned

a Reference Number in register memorv cannot be cleared using

this command. A

Datagram command to the block can be used instead.

*

Bits 17-26 contain the circuit reference (1 to 1000). Analog circuits are identified by the first six references assigned to the analog block. The following example shows circuit assignments for either an

RDT or a 4 Input/2 Output Analog Block assigned I/O references 10801 and 00801:

RTD Circuit

Input circuit 1

Input circuit 2

Input circuit 3

Input circuit 4

Input circuit 5

Input circuit 6

Analog circuit

Input circuit

1

Input circuit

2

Input circuit 3

Input circuit

4 output circuit

1 output circuit 2

I/O Reference

Starting reference

Starting reference plus 1

Starting reference plus 2

Starting reference plus 3

Starting reference plus 4

Starting reference plus 5

Value

0801

0802

0803

0804

0805

0806

Each time the Clear Circuit Fault command

is

received, any faults associated with the specified circuit are cleared. To

clear another circuit (either discrete or analog), set bit 3 to 0 for one CPU sweep, change the values in Bus Controller bytes 2,3 and

4 to reflect the individual circuit to be cleared and set bit 9 to reflect the I/O type of the circuit. Then set bit 3 to 1 again.

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10-l

GFK-0171

This chapter lists errors that might occur, and suggests corrective actions you can take.

Errors are most likely when a new system is being started up. They are often caused by mistakes in cabling>or field wiring, or by faulty logic in the CPU’s application program. If problems occur, consult the troubleshooting information in this chapter. It will help you isolate any problem that originates in a

Bus Controller. If these steps do not pinpoint the problem, the cause may lie in the CPU or programmer.

You should refer to chapter 5 of the

Series Six Plus installation and h4aintenunce iManual (GEK-96602) for further troubleshooting information.

If you have questions that are not answered in this manual or in the other documentation for your system, contact your local authorized GE Fanuc distributor. After business hours, please don’t hesitate to call

Programmable Control Emergency Service Number, (804) 9785747 (DIAL COMM

8-227-5747). An automatic answering device will direct you to the home phone of one of our

Programmable Control Service Personnel. Thus, you are never without backup help.

How to Begin

l

Check the operating mode of the CPU and9 if appropriate, the programmer. l

Check the status LEDs on the CPU.

- If some of the CPU status LEDs are off, refer to the

Series Six Installation and Maintenance

Manual.

- If all the CPU status LEDs are on but either of the Bus Controller LEDs is not, refer to the troubleshooting information on the following pages.

- If all the CPU and Bus Controller LEDs are on, check cabling then proceed to I/O block troubleshooting. Refer to the

Genius II0 System User’s A4and.

Identifying the Problem

If a problem occurs, look for a description of the problem in the list that begins below. Then, refer to the troubleshooting suggestion with the same number on the pages that follow.

1 .

Both Bus Controller LEDs are off.

2

.

3

.

The Bus Controller BOARD OK LED is off and the COMM OK LED is on.

The BOARD OK LED is on and the COMM OK LED is off.

4

.

The BOARD OK and COMM OK LEDs are flashing in unison.

5

.

The Bus Controller is not communicating with the CPU. Intermittent or total lack of communica- tions. No input data at CPU. No output data at block.

6

.

Window commands to the Bus Controller cause a syntax error.

7

.

Window commands to the Bus Controller don’t show any status change.

8

.

The Bus Controller is not communicating on the Genius I/O serial bus.

9

.

The Bus Controller begins operating, but does not seem to be operating normally.

10

.

There are no functioning circuits on one bus, but other busses are working.

11

.

There are no functioning circuits on more than one bus.

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1012 Troubleshooting

GFK-0171

12 .

The

CPU system shuts down with parity errors after operating for a short time, or after changing the system configuration.

13 . Communications on the bus are intermittent or lacking.

14 . One of the following occurs: a. The Bus Controller COMM OK light flashes excessively. b. There are delays on the bus. c.

\

Addition of Block/Loss of Block diagnostics occur repeatedly although no blocks are actually being added or removed.

Problems 1 -

4

1. Both Bus Controller LEDs are off.

- The Bus Controller is probably not receiving enough power from the rack

or the

computer power supply. Be sure the board is seated properly.

2. The Bus Controller BOARD OK LED is off and the COMM OK LED is on.

- Be sure the Bus Controller is installed in the correct slot.

- Be sure the rack DIP switches are set for a Reference Number at or below 993 for a Bus

Controller without Diagnostics, or at or below 953 for a Bus Controller with Diagnostics.

3.

The

BOARD OK LED is on and the COMM OK LED is off.

- Check for correct cable type and length.

- Check for correct terminating impedance at both ends of the bus.

- Be sure the cable is daisy-chained.

- Be sure wires to the Serial 1 and Serial 2 terminals are not crossed.

- Look for a broken cable.

Problems 4 - 8

4. The BOARD OK LED and COMM OK LEDs are flashing in unison.

- The Bus Controller detects another device on the same bus using the same Device Number.

Change the Device Number of one of the two.

5. The Bus Controller is not communicating with the CPU.

- This may indicate a progr amming or address assignment error. Also, check the CPU operating mode. Check particularly for overlapping addresses with other modules in the CPU rack.

This includes blocks controlled by other Bus Controllers in the CPU rack.

6. Window commands to the Bus Controller cause a syntax error.

- If the Bus Controller is located in a Remote I/O rack, DPREQ and WINDOW commands cannot be used. Please refer to chapter 1 for more information.

7. Window commands to the Bus Controller don’t show any status change.

- The Window Command is being sent to a non-existent Bus Controller. Power flows through

the

DPREQ or WINDOW instruction, but the status doesn’t change.

8. The Bus Controller is not communicating on the Genius I/O serial bus.

- Two devices on the same bus may have been configured with the same Device Number. Check this using the Hand-held Monitor. Note that a Phase B Bus Controller will not communicate on a bus if its assigned Device Number is already used by another device. However, both the Unit OK and the COMM OK LEDs will be blinking together.

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Troubleshooting

10-3

GFK-017 1

- Be sure wires to the Serial l/Serial 2 terminals on the module are not crossed or shorted together or to ground.

- Check the baud rate.

- Check the Device Number (serial bus address) assigned to the Bus Controller against the intended

Device Number from your records of system configuration. New Bus Controllers are shipped from the factory already set up to use Device Number 31.

- Check the Bus Controller’s Outputs Disabled bits using Read Configuration command to the Bus

Controller. Also check Bus Controller output #l (Disable All Outputs).

Problems 9 - 12

9. The Bus Controller begins operating, but does not seem to be operating normally.

- Be sure serial bus wiring has been completed in a daisy chain fashion.

- Make sure

the communications cable is not close to high voltage wiring.

- Look for a broken cable. Check for intermittent cable breaks and connections.

- Ensure that cable shielding is properly installed and grounded (see chapter 6 of the

Genius II0

System User’s Manual).

10. There are no functioning circuits on one bus, but other busses are operating normally.

From the CPU, see if the Bus Controller has its Outputs Disabled. This selectable feature allows a module to receive inputs, but not to send outputs.

See the chapter 1 for more information.

Check to see if the Bus Controller is properly installed, seated properly, and receiving power.

Check the on-board DIP switches, especially switch

4

at position U16.

Pull out the Bus Controller and reinsert.

Check for loose communications cable connections or breakage.

If necessary, replace the Bus Controller.

11. There are no functioning circuits on more than one bus.

- Please refer to the documentation for the Series Six PLC for troubleshooting information

12. The CPU system shuts down with parity errors after operating for a short time, or after changing the system configuration.

- There may be duplicate or overlapping I/O references coming from different busses.

- Unplug one Bus Controller, refer to the configuration worksheets, and use the I-MM to

Reference Numbers. If necessary, check other buses the same way.

read

- Verify that no conventional I/O module has reference numbers that overlap references

Genius I/O devices.

assigned to

Problems 13 - 14

13. Communications on the bus are intermittent or lacking.

- This may be caused by mixed baud rates. at their respective baud rates using HHM.

All devices on the bus must use the same

take effect until block power is cycled.

To check”&, power up blocks one at a time and look

If you find different baud rates, they must be changed. baud rate.

Any change to baud rate in block will not

- For Phase A devices, check for duplicate confirm Block Numbers using the HHM.

Block Numbers. Power devices up one at a time and

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10-4 Troubleshooting

GFK-0171

- The terminating resistors on the bus may be missing or incorrectly chosen or placed. Check terminators at ends of the bus for correct resistance value; BSM cluster “stubs” should not be terminated.

- The cable may be too long. Shorten the cable or configure all devices on the bus to use a lower baud rate. Please refer to chapter 5 of

the Genius I/O System User’s Manual for more information about cabling and baud rate selection.

- Wires may be open, shorted, or reversed. Check all bus electrical connections.

14 .

The COMM OK light on the Bus Controller blinks excessively, and/or there are propagation delays on the bus, and/or the bus is operating, but the CPU repeatedly receives Addition of Block and/or

Loss of Block diagnostics.

- There is excessive ambient noise on the bus. This can be corrected by lowering the baud rate, re-routing the communications cable, or shielding the source of the electrical noise. The proper solution to these problems will depend on the application. Please refer to chapter 5 of the

Genius

Z/O Svstem User’s Manual for information on cabling, baud rates, and ambient electrical noise.

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A-l

GFK-017 1

Appendix A

Expanded I/O Addressing

The tables that follow show how Expanded I/O is mapped for CPUs with different amounts of memory.

Expanded I/O Addressing for 8K and 16K Registers

For a CPU with either 8K or 16K of register memory: l

Real I/O references OO+OOOl to 00+1024, IO+0001 to 10+1024,08+0001 to 08+1024, and 18+0001 to IS+1024 can not be used as program references. However, internal I/O references 00-0001 to

00-1024, IO-0001 to 10-1024, 08-0001 to 08-1024, and 18-0001 to 18-1024 can be used. l

Channel 1-7 real I/O references are for the Expanded Main I/O channels.

* Channel 9-F real I/O references are for the Expanded Auxiliary I/O channels.

REGISTERS

AWL. I/O ROOOOl to ROOO64

Rooo65 to RO0128

Channel l+ R00129 to RO0192

RO0193 to RO0256

Channel 2+ RO0257 to ROO320

RO0321 to RO0384

Channel 3+ RO0385 to Roo448

ROO449 to ROO512

Channel 4+ RO0513 to RO0576

RO0577 to ROO640

Channel 5+ ROOW to ROO704

ROO705 to RO0768

Channel 6+ RO0769 to RO0832

RO0833 to ROOS%

Channel 7+ RoO897 to ROO960

ROO961 to RO102.4

Gen. use

R01025 to RO1088

RO1089 to Roll52

Channel 9+ Roll53 to R01216

R01217 to RO1280

Channel A+ RO1281 to R01344

ROW5 to ROl408

Channel B+ RO1409 to R01472

R01473 to R01536

Channel C+ R01537 to ROl600

ROl601 to R01664

Channel D+ R01665 to R01728

R01729 to R01792

Channel E+ R01793 to R01856

R01857 to RO1920

Channel F+ R01921 to R01984

R01985 to RO2048

USED FOR

A00001 to A01024

AI0001 to AI1024

Ol+OOOl to 01+1024

Il+OOOl to 11+1024

02+0001 to 02+1024

I2+0001 to I2+1024

03+0001 to 03+1024

13+0001 to I3+1024

04+ooOl to 04+1024

14+ooOl to 14+1024

05+0001 to 05+1024

I5+ooOl to IS+1024

06+0001 to 06+1024

16+0001 to 16+1024

07+oool to 07+1024

I7+0001 to IT+1024

09+OOOl to 09+1024

I9+0001 to I9+1024

OA+OOOl to OA+1024

IA+0001 to IA+1024

OB+OOOl to OB+1024

IB+OOOl to IB+1024 oc+OoO1 to oc+1024

1c+ooo1 to IC+1024

OD+OOOl to OD+1024

ID+ooOl to ID+1024

OE+OOOl to OE+1024

IE+O001 to IE+1024

OF+0001 to OF+1024

IF+0001 to IF+1024

REGISTERS

Channel 0- ROZO49 to R02112

RO2113 to R02176

Channel l- R02177 to RO2240

R02241 to RO2304

Channel 2- RO2305 to R02368

R02369 to R02432

Channel 3- R02433 to R02496

R02497 to RO2560

Channel 4- R02561 to R02624

R02625 to R02688

Channel 5- R02689 to R02752

R02753 to R02816

Channel 6- R02817 to RO2880

R02881 to R02944

Channel 7- R02945 to RO3008

R03009 to RO3072

Channel 8- RO3073 to R03136

R03137 to RO3200

Channel 9- RO3201 to R03264

R03265 to R03328

Channel A- R03329 to R03392

R03393 to R03456

Channel B- R03457 to RO3520

R03521 to R03584

Channel C- R03585 to R03548

R03549 to R03712

Channel D- R03713 to R03776

R03777 to RO3840

Channel E- R03841 to RO3904

RO3905 to RO3%8

Channel F- R03%9 to RO4032

RO4033 to RO4096

RO4097 to R04112

R04113 to R04116

R04117 to R04119

RO4120

R04121 to Rxxxxx

R08123 to R08192

R16315 to R16384

USED FOR

O-0001 to O-1024

I-0001 to I-1024

01-0001 to 01-1024

11-0001 to 11-1024

02-0001 to 02-1024

I2-Oool to I2-1024

03-0001 to 03-1024

I3-Oool to I3-1024

049oool to 04-1024

14-0001 to 14-1024

050oool to 05-1024

I5-0001 to Is-1024

06-0001 to 06-1024

16-0001 to 16-1024

070oool to 07-1024

IT-0001 to IT-1024

08-0001 to 08-1024

18-0001 to I8-1024

09-0001 to 09-1024

I9-0001 to I9-1024

OA-0001 to OA-1024

IA-0001 to IA-1024

OB-0001 to OB-1024 lB-0001 to IB-1024

0C-0001 to OC-1024

IC-Oool to IC-1024

OD-0001 to OD-1024

ID-0001 to ID-1024

OE-0001 to OE-1024

IE-0001 to IE-1024

OF-0001 to OF-1024

IF-0001 to IF-1024

Bus Ctr. bit map

User registers

Real time clock

Fault table pointer

Fault table entries

Computer Mailbox 8K

Computer Mailbox 16K

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Am2 Expanded I/O Addressing

GFK-0171

Expanded I/O Addressing for 1K Registers

Registers can be used as register references, for Expanded I/O, or for Genius I/O diagnostics storage.

For a CPU with 1K or 256 registers of memory, you should plan register use carefully, as mixing some or all of these may be difficult.

The table below shows how Expanded I/O is mapped into memory for a CPU with 1K register memory.

Channel 0 I/O is scanned on the Main I/O chain.

Expanded discrete references Ol+OOOl to 07+1024 and Il+OOOl to 17+1024 are mapped into the register table.

Auxiliary discrete references A00001 to A0 1024 and AI0001 to AI1024 are mapped into registers.

REGISTER

RANGE

ROOOl - R0128

R0129 - R0256

I/O ADDRESSES

A00001 - A01024

AI0001 - AI1024

01-0001 - 01-1024

11-0001 - 11-1024

R0257

R0258 - R0266

R0267 - R-269

R0270

R0271 - RXXYDL

R0955 - R1024

User Registers

ReaI Time clock

Fault Table Pointer

Fault Table Entries

Computer Mail Box

REGISTER CONTENTS

Auxiliary I/O

GENIUS I/O point fault status. If enabled, associated with Main Chain

I/O, 0001 - 1000 Bus Controller Status

Bit Map

If Genius I/O diagnostics is enabled, can be referenced as:

02-0001 to 02-1000

I2-0001 to I2-1000 through

07-0001 to 07-1000

17-0001 to 17-1000

Expanded I/O Addressing for 256 Registers

The table below shows how Expanded I/O is mapped into memory for a CPU with 256.word register memory. Auxiliary and Expanded discrete references A00001 through A01024, Al0001 through

AI1024,01+0001 through 01+1024, and Il+OOOl through 11+1024 are mapped into the register table.

REGISTER RANGE I/O ADDRESSES

ROOOl - R0128 (AO-0001 - AO-1024)

(AI-0001 - AI-1024)

R0129 - R0160 (Oli-0001 - 01+0512)

R0161 Bus Controller Status Bit Map

R0162 - ROW User Registers

R0167 - R0169 Real Time Clock

R0170 Fault Table Pointer

R0171 - Rxxx Fauk Table Entries

Rxxxx - R0186 User Registers

R0187 - R0256 Computer Mail Box

REGISTER CONTENTS

Either Auxiliary I/O or general use registers. If Genius diagnostics is enabled can be referenced as:

OH513 to

01+1000

(R0193) Il+OOOl - Il+lOOO

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GFK-017 1

Appendix B

Bus Controller Compatibility

This manual describes the operation and use of Phase B Genius I/O Bus Controllers. Basic differences between Phase B Bus Con&ollers and the earlier Phase A versions are explained below.

1

Feature Phase A Bus Controller Phase B Bus Controller

Power Supply and

+5V and +12V

req. CPU rack or High

+5 volts only May use High Capacity I/O rack, regular

Rack Requirement Capacity I/O Rack I/O rack, or CPU rack

Bus Scan Time

Multiple Bus

Controllers

Bus Controller used as a Monitor.

Less than 25oms.

Not supported.

Not supported

Less than 4ooms.

Supported.

Bus Controller outputs can be disabled allowing it to monitor bus . inputs and diagnostics from other devices on the

Baud Rate

Detection of

Device Number conflict

Powerup Tests

Uses 153.6 Kbaud only Selectable baud rates: 153.6 Kbaud standard, 153.6

Kbaud extended, 76.8 Kbaud or 38.4 Kbaud. Permits longer cables and better noise immunity.

Duplicate Device Numbers not de- Tests for another device on bus with the same Device tectti Number as the Bus Controller. If there is a Device

Number Number conflict, both LEDs on the Bus Control- ler will flash in unison. The conflicting Bus Controller must be removed and assigned another Device Number.

Then power to the Bus Controller must be cycled. both LEDs if communi- Will flash both LEDS in unison if powerup communica- cations test fails. Does not test MIT tions test or MIT test fails. circuits.

Bus Error

Detection

Clear All Faults

Command

Use of 16/32-

Circuit Blocks

Use of Aoalog

Blocks

If 1 bus error is detected in a 25OmS If 10 bus errors are detected in 10 seconds, Comm OK period, Comm OK LED turns off. LED goes off. Comm OK also goes off if Bus Controller

Comm OK also goes off if the Bus misses its turn on the bus. Comm OK LED goes back on

Controller misses its turn on the bus. if no new errors are detected in 250 mS. The bus error count is cleared every 10 sec.

Clears all faults, and completely clears

Clears all faults, but does not remove Addition or Loss of the fault queue. Block or Bus Controller Address faults from the queue.

Updates the input table during the

Updates the input table during the regular I/O portion of programmer window part of the sweep the sweep. DO I/OS may be able to capture updates. with latest inputs from blocks. DO

I/OS provide no updates.

Updates the I/O table during the No change. programmer window. DO I/OS pro- vide no update; same input, same data until next programmer window.

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B=2

Bus Controller Compatibility

GFK-0171

Feature

Phase A Bus Controller Phase B Bus Controller

Number of Analog If the number of analog blocks plus No restriction on the use of discrete blocks on one bus. If

Blocks and

Discrete Blocks on a Bus

16/32 ckt discrete blocks on bus ex- the number of analog blocks (of any type) exceeds 8, the ceeds 8, the program must prevent I/O program must prevent I/O scanning until the Bus Control- scanning until the Bus Controller has ler has updated all inputs. See chapter 3 for more infor- updated all inputs. Idle DPREQ or mation. Idle DPREQ or WINDOW provides automatic

WINDOW instruction provides auto- buffer time. matic buffer time.

Data Coherency Bus Controller version 1.6 (IC660CBB902G or

CBB903G) or later is required to guarantee data coheren- cy for future devices such as the High-speed Counter and

PowerTRAC.

Discrete blocks: 8-bit (1 byte) qua&-

Discrete blocks: same as phase A. ties only.

Analog blocks: 16.bit channel values

Analog blocks: same as phase A. handled as coherent data.

Control Data Sent

Does not send control data message to Sends null message to any inputs-only block on each to Inputs-only inputs-only blocks. Block I/O Ena- scan. This turns on I/O Enabled LED. If the block stops

Blocks bled LED goes on when logged in, never goes off. receiving this message for 3 scans, its I/O Enabled LED goes off.

Channel&d I/O

RTD Block support

Use of Expanded I/O channels re- Bus Controller DIP switch used to select Expanded I/O quires channelized I/O Transmitter and select channel unless down-stream of channelized I/O

Cards. Transmitter card.

Not supported Omy supports andog

Supported - maximum number of channels is 128 for any blocks with 4 input channels (or few- analog block. er).

Login

Switch BSM

Message

Programmed communications

Send/Receive

Datagrams

Relatively slow. Must process login Fast. Can handle multiple login messages per scan. messages 1 per bus scan.

Phase A blocks won’t recognize some of these, and will revert to phase A login procedure, which will go more slowly.

Not supported. Supports use of the Bus Switching Module and Switch

BSM message. Additionally, version 1.5 or later supports

BSM switching for BSMs controlled by analog blocks.

Specific Datagrams between the Bus Supports Datagrams and Global Data between Bus Con-

Controller and blocks only. trollers (CPUs) in addition to phase A features. Also

Send/Receive Datagram functions for Datagrams without built-in support, or for devices assigned to regis- ter memory.

These DPREQ or WINDOW com- Fully supported as either DPREQ or WINDOW com- mands not supported. Syntax error. man&. Used to send or request messages not covered by existing commands. Also used for CPU to CPU commu- nications.

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GFK-017 1

A

Active blocks, map, S-10

Addition of block, detection, 8-10

Analog blocks, 3-1,3-g

Analog, I/O, B-l

Analog I/O data, 3-6

Analog I/O Programming, l-11

Assign Monitor Datagram, 6-5

Assigned monitor, 5-14, B-l

Automatic diagnostics, 4-1

Auxiliary I/O, l-5

B

Baud Rate, 2-3,510, B-l

Block I/O type, 5-20

Block reference number, 5-20

Bus, 1-3

Bus Controller, 8-2 input references, 8-2

Set up, 2-1 status bit, 8-4

Terminating impedance, 2-2

Bus Controller baud rate, 2-3

Bus Controller compatibility, B-l

Bus Controller configuration worksheet, 2-8

Bus Controller Device Number, 2-3

Bus Controller diagnostics, 5-16

Bus Controller fault status, 1-12

Bus Controller Location, 1-4

Bus Controller locations screen, 4-7

Bus Controller model numbers, 5-10

Bus Controller number on bus, B-l

Bus Controller Operation, 1-7

Bus Controller output references, 9-1

Bus Controller references, 2-7,3-3,4-g

Bus Controller Setup, l-10

Bus Controller status byte, 4-6

Bus Controller types, 1-1

Bus error detection, 8-6, B-l

Bus Scan, 1-7

Bus scan time, l-12,5-16,6-3, B-l

Bus Switching Module, 5-21, B-2

Bus termination, 2-2

Bus Wiring Terminals,

1-2

Busses, number, 1-3

C

Channelized I/O, B-2

Clear all faults on bus, 9-4, B-l

Clear circuit fault, 9-4

Command block format, 5-3

Command Number, 5-4

1,5-4

11,594

12,5-4

13,504

2,5-4

3,5-4

4,5-4

7,5-4

9,5-4

Communications programming, 1-13

Communications timing, 5-5

Computer mailbox, 4-6,5-2

Control data, B-2

CPU address, 6-8

CPU Configuration instruction, 4-1

CPU register size,

4-4

CPU Shutdown mode, 2-3

CPU Sweep, l-9,8-4

CPU Sweep Time, 6-3,7-5

D

Data Coherency, B-2

Datagram, 6-l

Assign Monitor, 6-5 incoming, 6-3 priority, 6-2

Read Device, 6-12 timing, 6-4 types, 6-1

Write Device, 6-7

Write Point, 6-10

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Index

Datagrams supported, B-2

Device Number, 2-3

Device Number conflict, B-l

Diagnostic range, 4-3

Diagnostics enabled, 4-2

Diagnostics from Bus Controller, 8-l

Diagnostics programming, l- 12

Disable outputs, 2-5

DPREQ instruction, 5-l

I/O force detection, 8-15

I/O memory, 3-2

I/O Transmitter module, B-2

I/O Transmitter Modules, l-5

Idle command, 5-7

Inputs-only blocks, B-2

E

Error rate, 1-12

Expanded Functions, 4-1

Expanded I/O, 2-3, B-2

Expanded I/O addressing, A-l

L

LEDs, 1-2, 10-l

Logicmaster 6 version, 2-4

Login of bus devices, B-2

Loss of block, detection, 8-10

M

Memory mapping, A-l

F

Fault clearing, l-12,4-10

Fault Table, 4-4,4-g

Force I/O, 8-15

0

Output states, 1-12

Outputs disable, 2-5,5-l 1,5-13,9-3

G

Global Data, 7-1

Global Data address, 5-20

Global Data address and length, 5-11

Global Data vs Datagrams, 6-2

H

Hand-held Monitor Connector, 1-2

High-speed Counter, 3-9

P

Phase A/B compatibility, B-l

Phase A/phase B compatibility, l-1

PLC system setup, l-11

Power Supply, B-l

PowerTRAC, 3-9

Powerup tests, B-l

Programmer window, 3-10

Pulse Test detection, 8-14

Pulse Test outputs, 9-3

Pulse test programming, 1-12

I

I/O Addressing, 2-3

I/O block compatibility, B-l, B-2

I/O block references, 3-2

I/O block status, 1-12

I/O fault detection, 8-7

R

Rack, B-l

Read Analog Inputs command, 3-10,5-17

Read Configuration command, 5-8

Read Device Datagram, 6-12

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Index

GFK-0171

Index

GFK-017 1

Read Diagnostics command, 5-15

Read I/O type, 1-12

Read Status Table command, 5-20

Redundancy programming,

l-13

Redundant bus termination, 2-2

Reference Number, l-12,2-7

Reference Number configuration worksheet, 3-5

Reference Number conflict, 8-12

Reference number, block, 5-20

Reference Numbers, 3-1

Register Memory, 3-1

Remote I/O, 1-6

S

Subfunction codes, 6-1

Switch BSM, B-2

Switch BSM co mmand, 5-21

T

Troubleshooting, 1 O-1

W

WINDOW instruction, 5-2

Write Configuration command, 5-12

Write Device Datagram, 6-7

Write Point Datagram, 6-10

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