datasheet for VL470T2863B

datasheet for VL470T2863B
Product Specifications
PART NO:
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
General Information
1GB 128Mx 64 DDR2 SDRAM NON-ECC UNBUFFERED SODIMM 200-PIN
Description:
The VL470T2863B is a 128Mx64 DDR2 SDRAM high density SODIMM. This memory module consists of eight
CMOS 128Mx8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin
TSSOP package. This module is a 200-pin small-outline dual in-line memory module and is intended for
mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each
DDR2 SDRAM.
Features:
.
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200-pin, small-outline dual in-line memory module (SODIMM)
Fast data transfer rates: PC2-5300, PC2-4200, and PC2-3200
VDD = VDDQ = 1.8V
VDDSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18 compatible)
Differential data strobe (DQS, DQS# ) option
Four-bit prefetch architecture
DLL aligns DQ and DQS transition with CK
Programmable CAS# Latency (CL): 5 (DDR2-667), 4 (DDR2-533),
3 (DDR2-400)
Programmable burst; length (4, 8)
On-die termination (ODT)
Auto & Self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge PCB contacts
Lead-free, RoHS compliant
PCB: Height 30.00mm (1.181”), double sided components
Operating temperature (TOPER): -400C to +850C (module
screening using commercial DRAM)
Order Information:
VL470T2863B-E6 S X-I
I: Screening temperature
DRAM DIE (option)
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
Pin Name
Function
A0~A13
Address Inputs
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS7
Data Strobes
DQS0#~DQS7#
Data Strobes Complement
ODT0
On-die Termination Control
CK0,CK0#,CK1,CK1#
Clock Input
C KE0
Clock Enables
C S 0#
Chip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
VD D
Voltage Supply 1.8V +/- 0.1V
VSS
Ground
SA0~SA1
SPD Address
SD A
SPD Data Input/Output
SC L
SPD Clock Input
DM0~DM7
Data Masks
A10/AP
Address Input/Autoprecharge
VREF
SSTL_18 Reference Voltage
VD D SPD
SPD Voltage Supply 1.7V to
3.6V
NC
No Connect
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 10
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
Pin Configuration
200-PIN DDR2 SODIMM FRONT
200-PIN DDR2 SODIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQS2
101
A1
151
DQ42
2
VSS
52
DM2
102
A0
152
DQ46
3
VSS
53
VSS
103
VD D
153
DQ43
4
DQ4
54
VSS
104
VD D
154
DQ47
5
DQ0
55
DQ18
105
A10/AP
155
VSS
6
DQ5
56
DQ22
106
BA1
156
VSS
7
DQ1
57
DQ19
107
BA0
157
DQ48
8
VSS
58
DQ23
108
RAS#
15 8
DQ52
9
VSS
59
VSS
109
WE#
159
DQ49
10
DM0
60
VSS
110
C S 0#
160
DQ53
11
DQS0#
61
DQ24
111
VD D
161
VSS
12
VSS
62
DQ28
112
VD D
162
VSS
13
DQS0
63
DQ25
113
C AS#
163
NC
14
DQ6
64
DQ29
114
OTD0
164
C K1
15
VSS
65
VSS
115
C S 1#*
165
VSS
16
DQ7
66
VSS
116
A 13
166
C K 1#
17
DQ2
67
DM3
117
VD D
167
DQS6#
18
VSS
68
DQS3#
118
VD D
168
VSS
19
DQ3
69
NC
119
ODT1*
169
DQS6
20
DQ12
70
DQS3
120
NC
170
DM6
21
VSS
71
VSS
121
VSS
171
VSS
22
DQ13
72
VSS
122
VSS
172
VSS
23
DQ8
73
DQ26
123
DQ32
173
DQ50
24
VSS
74
DQ30
124
DQ36
174
DQ54
25
DQ9
75
DQ27
125
DQ33
175
DQ51
26
DM1
76
DQ31
126
DQ37
176
DQ55
27
VSS
77
VSS
127
VSS
177
VSS
28
VSS
78
VSS
128
VSS
178
VSS
29
DQS1#
79
C KE0
129
DQS4#
179
DQ56
30
C K0
80
C K E 1*
130
DM4
180
DQ60
31
DQS1
81
VDD
131
DQS4
181
DQ57
32
C K 0#
82
VDD
132
VSS
182
DQ61
33
VSS
83
NC
133
VSS
183
VSS
34
VSS
84
NC
134
DQ38
184
VSS
35
DQ10
85
BA2
135
DQ34
185
DM7
36
DQ14
86
NC
136
DQ39
186
DQS7#
37
DQ11
87
VDD
137
DQ35
187
VSS
38
DQ15
88
VDD
138
VSS
188
DQS7
39
VSS
89
A 12
139
VSS
189
DQ58
40
VSS
90
A11
140
DQ44
190
VSS
41
VSS
91
A9
141
DQ40
191
DQ59
42
VSS
92
A7
142
DQ45
192
DQ62
43
DQ16
93
A8
143
DQ41
193
VSS
44
DQ20
94
A6
144
VSS
194
DQ63
45
DQ17
95
VDD
145
VSS
195
SD A
46
DQ21
96
VDD
146
DQS5#
196
VSS
47
VSS
97
A5
147
DM5
197
SC L
48
VSS
98
A4
148
DQS5
198
SA0
49
DQS2#
99
A3
149
VSS
199
VD D SPD
50
NC
100
A2
150
VSS
200
SA1
* These pins are not used in this module.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 10
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
Functional Block Diagram
3
CS0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM CS#DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
U0
DQS1#
DQS1
DM1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
U1
DQS2#
DQS2
DM2
U5
DQS6#
DQS6
DM6
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
U2
U6
DQS7#
DQS7
DM7
DQS3#
DQS3
DM3
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
U3
3
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
ODT0
U4
U5
Serial PD
SCL
BA0-BA2: DDR2 SDRAMs
A0-A13: DDR2 SDRAMs
RAS#:
DDR2 SDRAMs
CAS#:
DDR2 SDRAMs
WE#:
DDR2 SDRAMs
CKE0:
DDR2 SDRAMs
ODT0:
DDR2 SDRAMs
WP A0
A1
U7
100
SDA
U0, U1,
U2, U3
CK0
CK0#
A2
SA0 SA1
VDDSPD
VDD, VDDQ
CK1
DDR2 SDRAMs CK1#
VREF
DDR2 SDRAMs
VSS
DDR2 SDRAMs
NOTE:
1. Unless ot herwise no te d, resistor v alues are 22 Ohms
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 10
100
Serial PD
U4, U5,
U6, U7
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
Command/Address,
RAS#, CAS#, WE#,
C S #, C K E
-40
40
uA
C K, C K#
-20
20
uA
DM
-5
5
uA
DQ, DQS, DQS#
-5
5
uA
-16
16
uA
VIN, VOUT
TSTG
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disabled
IOZ
VREF leakage current; VREF = Valid VREF level
IVREF
0
C
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
VDD
1.7
1.8
1.9
V
1
I/O Supply voltage
VD D Q
1.7
1.8
1.9
V
4
VDDL Supply voltage
VD DL
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Supply voltage
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 10
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
Operating Temperature Condition
Parameter
Symbol
Rating
TOPER
-40 - +85
Operating temperature
Units
0
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At -40 - +850C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85 °C < TOPER <= 95 °C
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
VIH(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage DDR2-667
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
VIL(AC)
-
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667
VIL(AC)
-
VREF - 0.200
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
12
20
pF
Input capacitance (CKE0), (ODT0)
CIN2
12
20
pF
Input capacitance (CS0#)
CIN3
12
20
pF
Input capacitance (CK0, CK0#, CK1, CK1#)
CIN4
8
12
pF
Input/Output capacitance (DM0 ~ DM7), (DQ0 ~ DQ63), (DQS0 ~ DQS7)
CIO
6.5
8
pF
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 10
Product Specifications
VL470T2863B-E6S/D5S/CCS-I
PART NO:
REV: 1.1
IDD Specification
Condition
Symbol
-E6
-D5
-CC
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0
680
560
560
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1
800
760
720
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P
56
56
56
mA
Precharge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q
320
320
280
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N
320
320
280
mA
Active pow er-dow n current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
240
240
240
mA
IDD3P
80
80
80
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N
440
360
320
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W
1080
1000
840
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R
1080
1000
840
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5
1720
1680
1640
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6
56
56
56
mA
IDD7
2240
2160
2080
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note: IDD specification is based on Samsung components. Other DRAM Manufacturers specification may be different.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 10
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
AC Timing Parameters & Specifications
Parameter
Clock
Data
-E6
-D5
-CC
Min
Max
Min
Max
Min
Max
Unit
CL=5
tCK (5)
3000
8000
-
-
-
-
ps
CL=4
tCK (4)
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK (3)
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
D ata-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
D ata-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
D Q and DM input setup time relative to DQS
tDS
100
100
150
D Q and DM input hold time relative to DQS
tDH
225
225
275
D Q and DM input pulse width (for each input)
tDIPW
0.35
0.35
0.35
D ata hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
D ata valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
tCK
D QS input low pulse width
tDQSL
0.35
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-400
D QS falling edge to CK rising – setup time
tDSS
0.2
0.2
0.2
tCK
D QS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
D QS write preamble setup time
tWPRES
0
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock cycle time
Data Strobe
Symbol
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
340
+400
MIN
(tCH,tCL)
tAC (MAX)
tAC (MIN)
400
-450
240
+450
tCK
450
-500
300
+500
ps
ps
350
ps
0.9
1.1
tCK
0.4
0.6
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 10
ps
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
AC Timing Parameters & Specifications ( cont')
Parameter
Power-Down
ODT
Self Refresh
Command and Address
Address and control input pulse width for each
input
Symbol
-E6
Min
-D5
Max
Min
-CC
Max
Min
Max
Unit
tIPW
0.6
0.6
Address and control input setup time
tIS
200
250
250
ps
Address and control input hold time
tIH
275
375
475
ps
0.6
tCK
C AS# to CAS# command delay
tCCD
2
2
2
ps
ACTIVE to ACTIVE (same bank) command
tRC
55
60
65
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
15
15
ns
Four Bank Activate period
tFAW
37.5
37.5
ACTIVE to PRECHARGE command
tRAS
40
70,000
Internal READ to precharge command delay
tRTP
7.5
37.5
37.5
40
70,000
7.5
37.5
37.5
ns
40
70,000
ns
7.5
ns
Write recovery time
tWR
15
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
7.5
10
ns
PRECHARGE command period
tRP
15
15
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
2
2
2
tCK
C KE low to CK,CK# uncertainty
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
REFRESH to Active or Refresh to Refresh
command interval
tRFC
105
Average periodic refresh interval
tREFI
70,000
105
7.8
70,000
105
7.8
70,000
ns
7.8
us
Exit self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exit self refresh to READ
tXSRD
200
200
200
tCK
Exit self refresh timing reference
tISXR
tIS
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
Exit precharge power-down to any non-READ
command.
tXP
2
2
2
tCK
C KE minimum high/low time
tCKE
3
3
3
tCK
ODT turn-on (power-down mode)
tIS
tIS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 10
ps
Product Specifications
REV: 1.1
VL470T2863B-E6S/D5S/CCS-I
PART NO:
Package Dimensions
FRONT VIEW
3.40
MAX
67.60
4.00 +/- 0.10 (2X)
30.00
1.80 (2X)
TYP
20.00 TYP
6.00 TYP
2.55 TYP
1.00 +/- 0.10
2.15 TYP
0.45 TYP
1.00 TYP
PIN 1
0.60 TYP
PIN 199
63.60 TYP
BACK VIEW
4.20 TYP
PIN 200
47.40 TYP
PIN 2
11.40 TYP
0.604 (15.35)
TYP
NOTE:
All dimesions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 10
Product Specifications
PART NO:
VL470T2863B-E6S/D5S/CCS-I
Revision History:
Date
Rev.
P ag e
C h an g es
05/07/09
1.0
All
Spec release
08/25/10
1.1
All
Update data
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 10
REV: 1.1
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