User manual | DS STM32L062K8

STM32L062K8
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M0+, 64 KB
Flash, 8 KB SRAM, 2 KB EEPROM,USB, ADC, DAC, AES
Datasheet - preliminary data
Features
•
•
•
•
Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 to 105/125 °C temperature range
– 0.27 µA Standby mode (2 wakeup pins)
– 0.4 µA Stop mode (16 wakeup lines)
– 0.8 µA Stop mode + RTC + 8 KB RAM retention
– 139 µA/MHz Run mode at 32 MHz
– 3.5 µs wakeup time (from RAM)
– 5 µs wakeup time (from Flash)
Core: ARM® 32-bit Cortex®-M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 26 DMIPS peak (Dhrystone 2.1)
Reset and supply management
– Ultra-safe, low-power BOR (brownout reset)
with 5 selectable thresholds
– Ultralow power POR/PDR
– Programmable voltage detector (PVD)
Clock sources
– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC
(+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– Internal self calibration of 48 MHz RC for USB
– PLL for CPU clock
•
Pre-programmed bootloader
– USART, SPI supported
•
Development support
– Serial wire debug supported
•
Up to 51 fast I/Os (45 I/Os 5V tolerant)
•
Memories
– 64 KB Flash with ECC
– 8 KB RAM
– 2 KB of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation
April 2014
UFQFPN32 5x5 mm
•
Rich Analog peripherals (down to 1.8 V)
– 12-bit ADC 1.14 Msps up to 16 channels
– 12-bit 1 channel DAC with output buffers
– 2x ultra-low-power comparators (window mode
and wake up capability)
•
Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
•
7-channel DMA controller, supporting ADC, SPI,
I2C, USART, DAC, Timers, AES
•
8x peripherals communication interface
•
1x USB 2.0 crystal-less, battery charging detection
and LPM
•
2x USART (ISO 7816, IrDA), 1x UART (low power)
•
2x SPI 16 Mbits/s
•
2x I2C (SMBus/PMBus)
•
9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
timer, 1x SysTick, 1x RTC, 1x 16-bit basic for DAC,
and 2x watchdogs (independent/window)
•
CRC calculation unit, 96-bit unique ID
•
True RNG and firewall protection
• Hardware Encryption Engine AES 128-bit
•
All packages are ECOPACK®2
DocID025937 Rev 2
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change without notice.
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Contents
STM32L062K8
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
ARM® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.1
2/104
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14
System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1
General-purpose timers (TIM2, TIM21 and TIM22) . . . . . . . . . . . . . . . . 29
3.17.2
Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.3
Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID025937 Rev 2
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3.18
Contents
3.17.4
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.5
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.6
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18.1
I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.18.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 32
3.18.3
Low-power universal asynchronous receiver transmitter (LPUART) . . . 32
3.18.4
Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 33
3.18.5
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.20
Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 34
3.21
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 47
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DocID025937 Rev 2
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Contents
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STM32L062K8
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.15
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.16
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.17
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.18
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.20
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.1.1
7.2
UFQFPN32 5 x 5 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Ultra-low-power STM32L062K8 device features and peripheral counts. . . . . . . . . . . . . . . 10
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32L0xX peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive sensing GPIOs available on STM32L062K8 devices . . . . . . . . . . . . . . . . . . . . 28
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32L062K8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L062K8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 47
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Current consumption in Run mode, code with data processing running from Flash. . . . . . 50
Current consumption in Run mode, code with data processing running from RAM . . . . . . 51
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Current consumption in Low-power Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current consumption in Low-power Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 55
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 59
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 71
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
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I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFQFPN32, 5 x 5 mm, 32-pin package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
STM32L062K8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DocID025937 Rev 2
STM32L062K8
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
STM32L062K8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32L062K8 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IDD vs VDD, at TA= 25/55/ 85/105 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IDD vs VDD, at TA= 25/55/ 85/105 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
IDD vs VDD, at TA= 25/55/85/105 °C, Stop mode with RTC disabled,
all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 67
VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFQFPN32, 5 x 5 mm, 32-pin package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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7
Introduction
1
STM32L062K8
Introduction
The ultra-low-power STM32L062K8 includes devices in a 32-pin package. Depending on
the device chosen, different sets of peripherals are included, the description below gives an
overview of the complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L062K8 microcontroller suitable for a wide
range of applications:
•
Medical and hand-held equipment
•
Application control and user interface
•
PC peripherals, gaming, GPS and sport equipment
•
Alarm systems, wired and wireless sensors, Video intercom
•
Utility metering
This STM32L062K8 datasheet should be read in conjunction with the STM32L0x2xx
reference manual (RM0376).
For information on the ARM® Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
8/104
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STM32L062K8
2
Description
Description
The ultra-low-power STM32L062K8 incorporates the connectivity power of the universal
serial bus (USB 2.0 crystal-less) with the high-performance ARM® Cortex®-M0+ 32-bit RISC
core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed
embedded memories (64 Kbytes of Flash program memory, 2 Kbytes of data EEPROM and
8 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
The STM32L062K8 device provides high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage
adaptation and several low-power modes.
The STM32L062K8 device offers several analog features, one 12-bit ADC, one DAC, two
ultra-low-power comparators, AES, several timers, one low-power timer (LPTIM), three
general-purpose 16-bit timers and one basic timer, one RTC and one SysTick which can be
used as timebases. It also features two watchdogs, one watchdog with independent clock
and window capability and one window watchdog based on bus clock.
Moreover, the STM32L062K8 device embeds standard and advanced communication
interfaces: up to two I2Cs, two SPIs, two I2S, three USARTs and a crystal-less USB. The
devices offer up to 24 capacitive sensing channels to simply add touch sensing functionality
to any application.
It also includes a real-time clock and a set of backup registers that remain powered in
Standby mode.
The ultra-low-power STM32L062K8 device operates from a 1.8 to 3.6 V power supply
(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without
BOR option. It is available in the -40 to +105 °C temperature range, extended to 125 °C in
low-power dissipation state. A comprehensive set of power-saving modes allows the design
of low-power applications.
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34
Description
2.1
STM32L062K8
Device overview
Table 1. Ultra-low-power STM32L062K8 device features and peripheral counts
Peripheral
STM32L062K8
Flash (Kbytes)
64
Data EEPROM (Kbytes)
2
RAM (Kbytes)
8
AES
1
Timers
General-purpose
3
Basic
1
LPTIMER
1
1/1/1/1
RTC/SYSTICK/IWDG/WWDG
2/(1)
SPI/(I2S)
Communication
interfaces
I2C
2
USART
2
LPUART
1
1/(1)
USB/(USB_VDD)
37
GPIOs
0/1/1/1/1
Clocks: HSE/LSE/HSI/MSI/LSI
1
10
12-bit synchronized ADC
Number of channels
1
16
12-bit DAC
Number of channels
1
1
Comparators
2
17
Capacitive sensing channels
Operating voltage
Operating temperatures
24
32 MHz
Max. CPU frequency
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR
option
1.65 V to 3.6 V without BOR option
Ambient temperature: –40 to +105 °C
Junction temperature: –40 to +125 °C
UFQFPN32
Packages
10/104
51
DocID025937 Rev 2
STM32L062K8
Description
Figure 1. STM32L062K8 block diagram
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DocID025937 Rev 2
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34
Description
2.2
STM32L062K8
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of core and features, from proprietary 8-bit
core to up ARM® Cortex®-M3, including ARM® Cortex®-M0+. The STM32Lx series are the
best choice to answer your needs in terms of ultra-low-power features. The STM32 Ultralow-power series are the best solution for applications such as gaz/water meter,
keyboard/mouse or fitness and healthcare application. Several built-in features like LCD
drivers, dual-bank memory, low-power Run mode, operational amplifiers, AES 128-bit, DAC,
crystal-less USB and many other definitely help you building a highly cost optimized
application by reducing BOM cost. STMicroelectronics, as a reliable and long-term
manufacturer, ensures as much as possible pin-to-pin compatibility between all STM8Lx
and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other hand.
Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.
12/104
DocID025937 Rev 2
STM32L062K8
Functional overview
3
Functional overview
3.1
Low-power modes
The ultra-low-power STM32L062K8 supports dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
•
Range 1 (VDD range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
•
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•
Range 3 (full VDD range), with a maximum CPU frequency limited to 4.2 MHz
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both
limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
•
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC and HSI RC oscillators are disabled. The LSE or LSI is still running. The
voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
DocID025937 Rev 2
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34
Functional overview
STM32L062K8
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.
•
Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC and LSE
crystal oscillators are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.
•
Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC and HSI RC oscillators are also switched off. The LSE
or LSI is still running. After entering Standby mode, the RAM and register contents are
lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE
Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire VCORE domain is powered off. The
PLL, MSI RC, HSI and LSI RC and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz oscillator,
RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 2. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power
supply range
14/104
DAC and ADC
operation
Dynamic
voltage scaling
range
I/O operation
USB
VDD = 1.65 to 1.71 V
Not functional
Range 2 or
range 3
Degraded speed
performance
Not functional
VDD = 1.71 to 1.8 V(1)
Not functional
Range 1, range 2
or range 3
Degraded speed
performance
Functional(2)
DocID025937 Rev 2
STM32L062K8
Functional overview
Table 2. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power
supply range
DAC and ADC
operation
Dynamic
voltage scaling
range
I/O operation
USB
VDD = 1.8 to 2.0 V(1)
Conversion time Range1, range 2
up to 1.14 Msps
or range 3
Degraded speed
performance
Functional(2)
VDD = 2.0 to 2.4 V
Conversion time
Range 1, range 2
up to
or range 3
1.14 Msps
Full speed operation
Functional(2)
VDD = 2.4 to 3.6 V
Conversion time
Range 1, range 2
up to
or range 3
1.14 Msps
Full speed operation
Functional(2)
1. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
2. To be USB compliant from the I/O voltage standpoint, the minimum VDD_USB is 3.0 V.
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34
Functional overview
STM32L062K8
Table 3. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
32 kHz to 4.2 MHz (0ws)
Range 3
Table 4. Functionalities depending on the working mode
(from Run/active down to standby) (1)
Standby
Run/Active
Sleep
CPU
Y
--
Y
--
--
--
Flash memory
O
O
O
O
--
--
RAM
Y
Y
Y
Y
Y
--
Backup registers
Y
Y
Y
Y
Y
Y
EEPROM
O
O
O
O
--
--
Brown-out reset
(BOR)
O
O
O
O
O
DMA
O
O
O
O
--
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
-
Power-on/down
reset (POR/PDR)
Y
Y
Y
Y
Y
Y
Y
High Speed
Internal (HSI)
O
O
--
--
(2)
--
Low Speed Internal
(LSI)
O
O
O
O
O
O
Low Speed
External (LSE)
O
O
O
O
O
O
Multi-Speed
Internal (MSI)
O
O
Y
Y
--
--
Inter-Connect
Controller
Y
Y
Y
Y
Y
--
RTC
O
O
O
O
O
O
O
RTC Tamper
O
O
O
O
O
O
O
IPs
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DocID025937 Rev 2
Lowpower
sleep
Stop
Lowpower
run
Wakeup
capability
O
Wakeup
capability
O
O
--
Y
O
STM32L062K8
Functional overview
Table 4. Functionalities depending on the working mode
(from Run/active down to standby) (continued)(1)
Standby
Run/Active
Sleep
Auto WakeUp
(AWU)
O
O
O
O
O
O
O
USB
O
O
--
--
--
O
--
USART
O
O
O
O
O(3)
O
--
(3)
O
--
IPs
Lowpower
sleep
Stop
Lowpower
run
Wakeup
capability
LPUART
O
O
O
O
O
SPI
O
O
O
O
--
Wakeup
capability
--
I2C
O
O
O
O
O(4)
ADC
O
O
O
O
--
--
DAC
O
O
O
O
O
--
Temperature
sensor
O
O
O
O
O
--
Comparators
O
O
O
O
O
16-bit timers
O
O
O
O
--
LPTIMER
O
O
O
O
O
O
IWDG
O
O
O
O
O
O
WWDG
O
O
O
O
--
--
Touch sensing
controller (TSC)
O
O
--
--
--
--
SysTick Timer
O
O
O
O
GPIOs
O
O
O
O
0 µs
0.36 µs
3 µs
32 µs
Wakeup time to
Run mode
O
O
O
--
---
O
O
-O
O
3.5 µs
2 pins
50 µs
0.28 µA (No
0.4 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to
140 µA/MHz
(from Flash)
Down to
37 µA/MHz
(from Flash)
Down to
8 µA
0.65 µA (with
0.8 µA (with
Down to RTC) VDD=1.8 V RTC) VDD=1.8 V
4.5 µA
0.4 µA (No
0.29 µA (No
RTC) VDD=3.0 V RTC) VDD=3.0 V
0.85 µA (with
1 µA (with RTC)
RTC) VDD=3.0 V
VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
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Functional overview
STM32L062K8
3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup on
address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running
the HSI clock.
4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Table 5. STM32L0xX peripherals interconnect matrix
Lowpower
sleep
Stop
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Timer triggered by Auto
wake-up
-
-
-
-
-
LPTIM
Timer triggered by RTC
event
Y
Y
Y
Y
Y
All clock
source
TIMx
Clock source used as
input channel for RC
measurement and
trimming
Y
Y
Y
Y
-
USB
CRS/HSI48
the clock recovery
system trims the HSI48
based on USB SOF
Y
Y
-
-
-
TIMx
Timer input channel and
trigger
Y
Y
Y
Y
-
LPTIM
Timer input channel and
trigger
Y
Y
Y
Y
Y
ADC,DAC
Conversion trigger
Y
Y
Y
Y
-
Interconnect
source
Interconnect action
Run
TIM2,TIM21,
TIM22
Timer input channel,
trigger from analog
signals comparison
Y
Y
LPTIM
Timer input channel,
trigger from analog
signals comparison
Y
TIMx
Timer triggered by other
timer
TIM21
COMPx
TIMx
RTC
GPIO
18/104
LowSleep power
run
Interconnect
destination
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STM32L062K8
3.3
Functional overview
ARM® Cortex®-M0+ core with MPU
The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
•
a simple architecture that is easy to learn and program
•
ultra-low power, energy-efficient operation
•
excellent code density
•
deterministic, high-performance interrupt handling
•
upward compatibility with Cortex-M processor family
•
platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded ARM core, the STM32L062K8 are compatible with all ARM tools
and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L062K8 embeds a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
•
includes a Non-Maskable Interrupt (NMI)
•
provides zero jitter interrupt option
•
provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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Functional overview
STM32L062K8
3.4
Reset and supply management
3.4.1
Power supply schemes
3.4.2
•
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
•
VDD_USB = 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
VDD_USB must be above 3.0V. If USB is not used this pin must be tied to VDD.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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STM32L062K8
3.4.3
Functional overview
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
3.4.4
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).
Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1(PA9, PA10), USART2(PA2, PA3), SPI1(PA4, PA5, PA6, PA7) or
SPI2(PB12, PB13, PB14, PB15). See STM32™ microcontroller system memory boot mode
AN2606 for details.
3.5
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
•
Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
•
Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
•
System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
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Functional overview
STM32L062K8
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
•
Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the real-time clock:
•
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
RTC clock source
The LSI, LSE sources can be chosen to clock the RTC , whatever the system clock.
•
USB clock source
A 48 MHz clock trimmed through the USB SOF supplies the USB interface.
•
Startup clock
After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
•
Clock security system (CSS)
This feature can be enabled by software.
Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.
•
Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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STM32L062K8
Functional overview
Figure 2. Clock tree
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34
Functional overview
3.6
STM32L062K8
Low-power real-time clock and backup registers
The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
•
•
•
•
•
•
•
•
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
Two programmable alarms with wake up from Stop and Standby mode capability
Periodic wakeup from Stop and Standby with programmable resolution and period
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
•
•
•
•
3.7
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 37 kHz)
The high-speed external clock
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 28 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 12 other lines are connected to PVD, RTC,
USB, USARTs, LPUART, LPTIMER or comparator events.
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STM32L062K8
3.8
Functional overview
Memories
The STM32L062K8 device has the following features:
•
8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
32 or 64 Kbytes of embedded Flash program memory
–
2 Kbytes of data EEPROM
–
Information block containing 32 user and factory options bytes plus 4 Kbytes of
system memory
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
•
Level 0: no protection
•
Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
•
Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the nonvolatile data segment is 256 bytes (Flash or EEPROM) against 64 bytes for the volatile data
segment (RAM).
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.9
Direct memory access (DMA)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: AES, SPI, I2C, USART, LPUART,
general-purpose timers, DAC, and ADC.
3.10
Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L062K8 devices. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference). It performs conversions in singleshot or scan mode. In scan mode, automatic conversion is performed on a selected group of
analog inputs.
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Functional overview
STM32L062K8
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
3.11
Temperature sensor
The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 6. Temperature sensor calibration values
Calibration value name
3.11.1
Description
Memory address
TSENSE_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3 V
0x1FF8 007A - 0x1FF8 007B
TSENSE_CAL2
TS ADC raw data acquired at
temperature of 130 °C
VDDA= 3 V
0x1FF8 007E - 0x1FF8 007F
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value . The precise voltage of VREFINT is individually
measured for each part by ST during production test and stored in the system memory area.
It is accessible in read-only mode.
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Functional overview
Table 7. Internal voltage reference measured values
Calibration value name
Description
Raw data acquired at
temperature of 30 °C
VDDA = 3 V
VREFINT_CAL
3.12
Memory address
0x1FF8 0078 - 0x1FF8 0079
Digital-to-analog converter (DAC)
One 12-bit buffered DAC can be used to convert digital signal into analog voltage signal
output. An optional amplifier can be used to reduce the output signal impedance.
This digital Interface supports the following features:
•
One data holding register
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
DMA capability (including the underrun interrupt)
•
External triggers for conversion
Four DAC trigger inputs are used in the STM32L062K8. The DAC channel is triggered
through the timer update outputs that are also connected to different DMA channels.
3.13
Ultra-low-power comparators and reference voltage
The STM32L062K8 embeds two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
•
One comparator with ultra low consumption
•
One comparator with rail-to-rail inputs, fast or slow mode.
•
The threshold can be one of the following:
–
DAC output
–
External I/O pins
–
Internal reference voltage (VREFINT)
–
submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.14
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
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Functional overview
STM32L062K8
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21, TIM22 and LPTIM timer input captures. It also controls the
routing of internal analog signals to the USB internal oscillator, ADC, COMP1 and COMP2
and the internal reference voltage VREFINT.
3.15
Touch sensing controller (TSC)
The STM32L062K8 provides a simple solution for adding capacitive sensing functionality to
any application. These devices offer up to 24 capacitive sensing channels distributed over 8
analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 8. Capacitive sensing GPIOs available on STM32L062K8 devices
Group
1
2
3
4
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Capacitive sensing
signal name
Pin
name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
Capacitive sensing
signal name
Pin
name
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
PA3
TSC_G5_IO4
PB7
TSC_G2_IO1
PA4
TSC_G6_IO1
PB11
TSC_G2_IO2
PA5
TSC_G6_IO2
PB12
TSC_G2_IO3
PA6
TSC_G6_IO3
PB13
TSC_G2_IO4
PA7
TSC_G6_IO4
PB14
TSC_G3_IO1
PC5
TSC_G7_IO1
PC0
TSC_G3_IO2
PB0
TSC_G7_IO2
PC1
TSC_G3_IO3
PB1
TSC_G7_IO3
PC2
TSC_G3_IO4
PB2
TSC_G7_IO4
PC3
TSC_G4_IO1
PA9
TSC_G8_IO1
PC6
TSC_G4_IO2
PA10
TSC_G8_IO2
PC7
TSC_G4_IO3
PA11
TSC_G8_IO3
PC8
TSC_G4_IO4
PA12
TSC_G8_IO4
PC9
DocID025937 Rev 2
Group
5
6
7
8
STM32L062K8
3.16
Functional overview
AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26).
•
Key scheduler
•
Key derivation for decryption
•
128-bit data block processed
•
128-bit key length
•
213 clock cycles to encrypt/decrypt one 128-bit block
•
Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR)
supported by hardware.
The AES can be served by the DMA controller.
3.17
Timers and watchdogs
The ultra-low-power STM32L062K8 device includes three general-purpose timers, one lowpower timer (LPTM), one basic timer, two watchdog timers and the SysTick timer.
Table 9 compares the features of the general-purpose and basic timers.
Table 9. Timer feature comparison
Timer
Counter
resolution
Counter type
Prescaler factor
DMA
request
generation
TIM2
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM21,
TIM22
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM6
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.17.1
Capture/compare Complementary
channels
outputs
General-purpose timers (TIM2, TIM21 and TIM22)
There are three synchronizable general-purpose timers embedded in the STM32L062K8
device (see Table 9 for differences).
TIM2
TIM2 is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It
features four independent channels each for input capture/output compare, PWM or onepulse mode output.
The TIM2 general-purpose timers can work together or with the TIM21 and TIM22 generalpurpose timers via the Timer Link feature for synchronization or event chaining. Their
counter can be frozen in debug mode. Any of the general-purpose timers can be used to
generate PWM outputs.
TIM2 have independent DMA request generation.
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Functional overview
STM32L062K8
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
TIM21 and TIM22
TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit
prescaler. They have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work together and be synchronized with the TIM2, fullfeatured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.17.2
Low-power Timer (LPTIM)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.17.3
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / one shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source
–
Internal clock source: LSE, LSI, HSI or APB clock
–
External clock source over LPTIM input (working even with no internal clock
source running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Basic timer (TIM6)
This timer can be used as a generic 16-bit timebase. It is mainly used for DAC trigger
generation.
3.17.4
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
3.17.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
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3.17.6
Functional overview
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.18
Communication interfaces
3.18.1
I2C bus
Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and
Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital
noise filters.
Table 10. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. I2C1 also has a clock domain independent from the CPU
clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 11 for the differences between I2C1 and I2C2.
Table 11. STM32L062K8 I2C implementation
I2C features(1)
I2C1
I2C2
7-bit addressing mode
X
X
10-bit addressing mode
X
X
Standard mode (up to 100 kbit/s)
X
X
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X(2)
Independent clock
X
-
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Functional overview
STM32L062K8
Table 11. STM32L062K8 I2C implementation (continued)
I2C features(1)
I2C1
I2C2
SMBus
X
-
Wakeup from STOP
X
-
1. X = supported.
2. See for the list of I/Os that feature Fast Mode Plus capability
3.18.2
Universal synchronous/asynchronous receiver transmitter (USART)
The two USART interfaces (USART1 and USART2) are able to communicate at speeds of
up to 4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE)
signals, multiprocessor communication mode, master synchronous communication and
single-wire half-duplex communication mode. The support also SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has
a clock domain independent from the CPU clock, allowing to wake up the MCU from Stop
mode.
All USART interfaces can be served by the DMA controller.
Refer to Table 12 for the supported modes and features of USART1 and USART2.
Table 12. USART implementation
USART modes/features(1)
USART1 and USART2
Hardware flow control for modem
X
Continuous communication using DMA
X
Multiprocessor communication
X
Synchronous mode
X
Smartcard mode
X
Single-wire half-duplex communication
X
IrDA SIR ENDEC block
X
LIN mode
X
Dual clock domain and wakeup from Stop mode
X
Receiver timeout interrupt
X
Modbus communication
X
Auto baud rate detection (4 modes)
X
Driver Enable
X
1. X = supported.
3.18.3
Low-power universal asynchronous receiver transmitter (LPUART)
The device embeds one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
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Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wake up the
system from Stop mode. The Wakeup events from Stop mode are programmable and can
be:
•
Start bit detection
•
Or any received data frame
•
Or a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
3.18.4
Serial peripheral interface (SPI)/Inter-integrated sound (I2S)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or
slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output
channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the
I2S interfaces is configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
The SPIs can be served by the DMA controller.
Refer to Table 13 for the differences between SPI1 and SPI2.
Table 13. SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
Rx/Tx FIFO
X
X
NSS pulse mode
X
X
I2S mode
-
X
TI mode
X
X
1. X = supported.
3.18.5
Universal serial bus (USB)
The STM32L062K8 embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up to 1 KB and suspend/resume support. It requires a precise
48 MHz clock which can be generated by the internal 48 MHz oscillator in automatic
trimming mode. The synchronization for this oscillator can be taken from the USB data
stream itself (SOF signalization) which allows crystal-less operation.
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Functional overview
3.19
STM32L062K8
Clock recovery system (CRS)
The STM32L062K8 embeds a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.20
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.21
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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4
Pin descriptions
Pin descriptions
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Figure 3. STM32L062K8 UFQFPN32 pinout
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1. The above figure shows the package top view.
Table 14. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TC
Standard 3.3V I/O
B
RST
Notes
Pin functions
Definition
Dedicated BOOT0 pin
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
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Pin descriptions
STM32L062K8
Table 15. STM32L062K8 pin definitions
PC14OSC32_IN
I/O
FT
OSC32_IN
3
PC15OSC32_OUT
I/O
TC
OSC32_OUT
4
NRST
I/O
RST
5
VDDA
S
6
7
8
9
36/104
PA0
PA1
PA2
PA3
I/O
I/O
I/O
I/O
Notes
I/O structure
2
UFQFPN32
Pin name
(function after
reset)
Pin type
Pin
Number
Alternate functions
Additional functions
TC
TIM2_CH1,
TSC_G1_IO1,
USART2_CTS,
TIM2_ETR,
COMP1_OUT
COMP1_INM6,
ADC_IN0,
RTC_TAMP2/WKUP1
FT
EVENTOUT,
TIM2_CH2,
TSC_G1_IO2,
USART2_RTS,
TIM21_ETR
COMP1_INP,
ADC_IN1
FT
TIM21_CH1,
TIM2_CH3,
TSC_G1_IO3,
USART2_TX,
COMP2_OUT
COMP2_INM6,
ADC_IN2
FT
TIM21_CH2,
TIM2_CH4,
TSC_G1_IO4,
USART2_RX
COMP2_INP,
ADC_IN3
SPI1_NSS,
TSC_G2_IO1,
USART2_CK,
TIM22_ETR
COMP1_INM4,
COMP2_INM4,
ADC_IN4, DAC_OUT
SPI1_SCK, TIM2_ETR,
TSC_G2_IO2,
TIM2_CH1
COMP1_INM5,
COMP2_INM5,
ADC_IN5
10
PA4
I/O
TC
11
PA5
I/O
TC
(1)
DocID025937 Rev 2
STM32L062K8
Pin descriptions
Table 15. STM32L062K8 pin definitions (continued)
12
PA6
I/O
Notes
I/O structure
Pin name
(function after
reset)
Pin type
UFQFPN32
Pin
Number
Alternate functions
Additional functions
FT
SPI1_MISO,
TSC_G2_IO3,
USART3_CTS,
TIM22_CH1,
EVENTOUT,
COMP1_OUT
ADC_IN6
ADC_IN7
13
PA7
I/O
FT
SPI1_MOSI,
TSC_G2_IO4,
TIM22_CH2,
EVENTOUT,
COMP2_OUT
14
PB0
I/O
FT
EVENTOUT,
TSC_G3_IO2
ADC_IN8,
VREF_OUT
15
PB1
I/O
FT
TSC_G3_IO3,
USART3_RTS
ADC_IN9,
VREF_OUT
16
PB2
I/O
FT
LPTIM1_OUT,
TSC_G3_IO4
17
VDD
S
18
PA8
I/O
FT
MCO,
USB_CRS_SYNC,
EVENTOUT,
USART1_CK
19
PA9
I/O
FT
MCO, TSC_G4_IO1,
USART1_TX
20
PA10
I/O
FT
TSC_G4_IO2,
USART1_RX
FT
SPI1_MISO,
EVENTOUT,
TSC_G4_IO3,
USART1_CTS,
COMP1_OUT
USB_DM
FT
SPI1_MOSI,
EVENTOUT,
TSC_G4_IO4,
USART1_RTS,
COMP2_OUT
USB_DP
21
22
PA11(2)
PA12(2)
I/O
I/O
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Pin descriptions
STM32L062K8
Table 15. STM32L062K8 pin definitions (continued)
PA13
I/O
FT
SWDIO, USB_OE
24
PA14
I/O
FT
SWCLK, USART2_TX
Notes
I/O structure
23
UFQFPN32
Pin name
(function after
reset)
Pin type
Pin
Number
Alternate functions
Additional functions
25
PA15
I/O
FT
SPI1_NSS, TIM2_ETR,
EVENTOUT,
USART2_RX,
TIM2_CH1
26
PB3
I/O
FT
SPI1_SCK, TIM2_CH2,
TSC_G5I_O1,
EVENTOUT
COMP2_INN
FT
SPI1_MISO,
EVENTOUT,
TSC_G5_IO2,
TIM22_CH1
COMP2_INP
FT
SPI1_MOSI,
LPTIM1_IN1,
I2C1_SMBA,
TIM22_CH2
COMP2_INP
FTf
USART1_TX,
I2C1_SCL,
LPTIM1_ETR,
TSC_G5_IO3
COMP2_INP
USART1_RX,
I2C1_SDA,
LPTIM1_IN2,
TSC_G5_IO4
COMP2_INP,
PVD_IN
27
28
29
PB4
PB5
PB6
I/O
I/O
I/O
30
PB7
I/O
FTf
31
BOOT0
I
B
32
PB8
I/O
FTf
-
VSS
S
1
VDD
S
TSC_SYNC, I2C1_SCL
1. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
2. These pins are powered by VDD_USB. For all characteristics that refer to VDD, VDD_USB must be used
instead.
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AF0
Port
SPI1/SPI2/I2S2/
USART1/2/3/
USB/LPTIM/
SPI1/SPI2/I2S2/
TSC/TIM2/21/22 I2C1/TIM2/21
/EVENOUT/
SYS_AF
PA0
DocID025937 Rev 2
Port A
AF1
AF2
AF3
AF4
SPI2/I2S2/
USART3/USB/
LPTIM/TIM2/
EVENOUT/
SYS_AF
I2C1/TSC/
EVENOUT
TIM2_CH1
TSC_G1_IO1
USART2_CTS
TIM2_ETR
TIM21_ETR
I2C1/USART1/2
SPI2/I2S2/I2C2/
/3/TIM22/
TIM2/21/22
EVENOUT
PA1
EVENTOUT
TIM2_CH2
TSC_G1_IO2
USART2_RTS
PA2
TIM21_CH1
TIM2_CH3
TSC_G1_IO3
USART2_TX
PA3
TIM21_CH2
TIM2_CH4
TSC_G1_IO4
USART2_RX
PA4
SPI1_NSS
TSC_G2_IO1
USART2_CK
PA5
SPI1_SCK
PA6
SPI1_MISO
TSC_G2_IO3
PA7
SPI1_MOSI
TSC_G2_IO4
PA8
MCO
PA9
MCO
TIM2_ETR
USB_CRS_
SYNC
PA10
AF5
TSC_G2_IO2
AF6
AF7
I2C2/TIM21/
EVENOUT
COMP1/2
COMP1_OUT
COMP2_OUT
TIM22_ETR
TIM2_CH1
USART3_CTS
EVENTOUT
USART1_CK
TSC_G4_IO1
USART1_TX
TSC_G4_IO2
USART1_RX
TIM22_CH1
EVENTOUT
COMP1_OUT
TIM22_CH2
EVENTOUT
COMP2_OUT
SPI1_MISO
EVENTOUT
TSC_G4_IO3
USART1_CTS
COMP1_OUT
PA12
SPI1_MOSI
EVENTOUT
TSC_G4_IO4
USART1_RTS
COMP2_OUT
PA13
SWDIO
USB_OE
PA14
SWCLK
PA15
SPI1_NSS
USART2_TX
EVENTOUT
USART2_RX
TIM2_CH1
Pin descriptions
39/104
PA11
TIM2_ETR
STM32L062K8
Table 16. Alternate functions for port A
AF0
Port
PB0
SPI1/SPI2/I2S2
/USART1/2/3/
USB/LPTIM/
TSC/TIM2/21/22/
EVENOUT/SYS_AF
AF1
AF2
AF3
AF4
SPI1/SPI2/I2S2
/I2C1/TIM2/21
SPI2/I2S2/
USART3/USB/
LPTIM/TIM2/
EVENOUT/
SYS_AF
I2C1/TSC/
EVENOUT
I2C1/USART1/2/3/
TIM22/EVENOUT
EVENTOUT
TSC_G3_IO2
PB1
TSC_G3_IO3
DocID025937 Rev 2
Port B
PB2
LPTIM1_OUT
TSC_G3_IO4
USART3_RTS
PB3
SPI1_SCK
TIM2_CH2
TSC_G5I_O1
EVENTOUT
PB4
SPI1_MISO
EVENTOUT
TSC_G5_IO2
TIM22_CH1
PB5
SPI1_MOSI
LPTIM1_IN1
I2C1_SMBA
TIM22_CH2
PB6
USART1_TX
LPTIM1_ETR
TSC_G5_IO3
PB7
USART1_RX
LPTIM1_IN2
TSC_G5_IO4
PB8
Pin descriptions
40/104
Table 17. Alternate functions for port B
TSC_SYNC
I2C1_SCL
STM32L062K8
STM32L062K8
5
Memory mapping
Memory mapping
Figure 4. Memory map
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41
Electrical characteristics
STM32L062K8
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 5.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 6.
Figure 5. Pin loading conditions
Figure 6. Pin input voltage
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STM32L062K8
6.1.6
Electrical characteristics
Power supply scheme
Figure 7. Power supply scheme
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Figure 8. Current consumption measurement scheme
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97
Electrical characteristics
6.2
STM32L062K8
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics, and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 18. Voltage characteristics
Symbol
VDD–VSS
VIN(2)
Ratings
Min
Max
–0.3
4.0
Input voltage on FT and FTf pins
VSS − 0.3
VDD+4.0
Input voltage on TC pins
VSS − 0.3
4.0
Input voltage on BOOT0
VSS
VDD + 4.0
VSS − 0.3
4.0
External main supply voltage
(including VDDA, VDD_USB, VDD)(1)
Input voltage on any other pin
|ΔVDD|
Variations between different VDD/VDDA power
pins(3)
-
50
|ΔVSS|
Variations between all different ground pins
-
50
VESD(HBM)
Electrostatic discharge voltage
(human body model)
Unit
V
mV
see Section 6.3.11
1. All main power (VDD, VDD_USB, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2.
VIN maximum must always be respected. Refer to Table 19 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. VDD_USB is independent
from VDD and VDDA: its value does not need to respect this rule.
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Electrical characteristics
Table 19. Current characteristics
Symbol
Ratings
Max.
ΣIVDD(2)
Total current into sum of all VDD power lines (source)(1)
105
ΣIVSS(2)
(1)
105
Total current out of sum of all VSS ground lines (sink)
(1)
IVDD(PIN)
Maximum current into each VDD power pin (source)
100
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk by any I/O and control pin except FTf
pins
16
Output current sunk by FTf pins
22
Output current sourced by any I/O and control pin
-16
Total output current sunk by sum of all IOs and control
pins(2)
90
Total output current sourced by sum of all IOs and control
pins(2)
-90
IIO
ΣIIO(PIN)
IINJ(PIN)
ΣIINJ(PIN)
Injected current on FT, FFf, RST and B pins
Unit
mA
-5/+0(3)
Injected current on TC pin
± 5(4)
Total injected current (sum of all I/O and control pins)(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 18 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 20. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DocID025937 Rev 2
Value
Unit
–65 to +150
°C
150
°C
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6.3
Operating conditions
6.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled,
at power on
1.8
3.6
BOR detector disabled,
after power on
1.65
3.6
1.65
3.6
VDD
VDDA(1)
VDD_USB
Standard operating voltage
Analog operating voltage
(ADC and DAC not used)
Must be the same voltage
as VDD(2)
Analog operating voltage
(ADC or DAC used)
Input voltage on FT, FTf and RST pins(4)
VIN
PD
TA
TJ
3.6
1.65
3.6
2.0 V ≤ VDD ≤ 3.6 V
-0.3
5.5
1.65 V ≤ VDD ≤ 2.0 V
-0.3
5.2
Input voltage on BOOT0 pin
-
0
5.5
Input voltage on TC pin
-
-0.3
VDD+0.3
-
351
Maximum power
dissipation (range 6)
–40
85
Maximum power
dissipation (range 7)
–40
105
Low-power dissipation
(range 7) (6)
–40
125
Junction temperature range (range 6)
-40 °C ≤ TA ≤ 85 °
–40
105
Junction temperature range (range 7)
-40 °C ≤ TA ≤ 105 °C
–40
125
Power dissipation at TA = 85 °C (range 6)
UFQFPN32
or TA =105 °C (rage 7) (5)
Temperature range
MHz
V
V
1.8
Standard operating voltage, USB
domain(3)
Unit
V
V
mW
°C
1. When the ADC is used, refer to Table 53: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and normal operation.
3. For for USB compliance, VDD_USB must remain higher than 3.0 V.
4. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 71: Thermal characteristics
on page 101).
6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Table 71:
Thermal characteristics on page 101).
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6.3.2
Electrical characteristics
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 21.
Table 22. Embedded reset and power control block characteristics
Symbol
Parameter
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1) Reset temporization
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
Conditions
Min
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
VDD rising, BOR
DocID025937 Rev 2
disabled(2)
Unit
µs/V
ms
V
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Table 22. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst
Hysteresis voltage
Min
Typ
Max
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD thresholds
excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
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6.3.3
Electrical characteristics
Embedded internal reference voltage
The parameters given in Table 24 are based on characterization results, unless otherwise
specified.
Table 23. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VDDA= 3 V
VREFINT_CAL
0x1FF8 0078 - 0x1FF8 0079
Table 24. Embedded internal reference voltage
Symbol
Conditions
Min
Typ
Max
Unit
Internal reference voltage
– 40 °C < TJ < +125 °C
1.202
1.224
1.242
V
Internal reference current
consumption
-
-
1.4
2.3
µA
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA voltage during VREFINT
factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Accuracy of factory-measured
VREF value(2)
Including uncertainties
due to ADC and
VDDAvalues
-
-
±5
mV
–40 °C < TJ < +125 °C
-
20
50
0 °C < TJ < +50 °C
-
-
20
VREFINT out
Parameter
(1)
IREFINT
TCoeff(3)
Temperature coefficient
ACoeff(3)
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
VDDCoeff(3)
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
ppm/°C
TS_vrefint(3)(4)
ADC sampling time when
reading the internal reference
voltage
-
5
10
-
µs
TADC_BUF(3)
Startup time of reference
voltage buffer for ADC
-
-
-
10
µs
IBUF_ADC(3)
Consumption of reference
voltage buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(3)
VREF_OUT output current(5)
-
-
-
1
µA
CVREF_OUT(3)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference
voltage buffer for VREF_OUT
and COMP
-
-
730
1200
nA
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
ILPBUF(3)
%
VREFINT
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
DocID025937 Rev 2
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Electrical characteristics
STM32L062K8
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
5. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 8: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 21: General operating
conditions unless otherwise specified.
The MCU is placed under the following conditions:
•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time and prefetch is adjusted depending on fHCLK
frequency and voltage range to provide the best CPU performance unless otherwise
specified.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAPB
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used)
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise
The parameters given in Table 40, Table 21 and Table 22 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 21.
Table 25. Current consumption in Run mode, code with data processing running from Flash(1)
Symbol
IDD
(Run
from
Flash)
Parameter
Supply
current in
Run mode,
code
executed
from Flash
fHCLK
Typ
Max(2)
Range 2, VOS[1:0]=10,
VCORE=1.5 V
16 MHz
2.6
2.9
Range 1, VOS[1:0]=01,
VCORE=1.8 V
32 MHz
6.25
7
65 kHz
36.5
110
524 kHz
99.5
190
4.2 MHz
620
700
Conditions
HSI16 clock source
(16 MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
Range 3, VOS[1:0]=11,
VCORE=1.2 V
mA
1. CoreMark, Fibonacci and while(1) conditions are given for current consumption estimates compared to Dhrystone.
2. Guaranteed by characterization results, not tested in production, unless otherwise specified.
50/104
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Unit
µA
STM32L062K8
Electrical characteristics
Figure 9. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS
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Table 26. Current consumption in Run mode, code with data processing running from RAM
Symbol
IDD (Run
from
RAM)
Parameter
Supply current in
Run mode, code
executed from
RAM, Flash
switched off
fHCLK
Typ
Max(1)
Range 2,
VOS[1:0]=10,
VCORE=1.5 V
16 MHz
2.1
2.3
Range 1,
VOS[1:0]=01,
VCORE=1.8 V
32 MHz
5.1
5.6
65 kHz
34.5
75
524 kHz
83
120
4.2 MHz
485
540
Conditions
HSI16 clock source
(16 MHz)
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
Range 3,
VOS[1:0]=11,
VCORE=1.2 V
Unit
mA
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
Table 27. Current consumption in Sleep mode
Symbol
IDD (Sleep)
Parameter
Conditions
Range 2,
VOS[1:0]=10,
HSI16 clock source VCORE=1.5 V
Range 1,
Supply current (16 MHz)
VOS[1:0]=01,
in Sleep
VCORE=1.8 V
mode, Flash
OFF
MSI clock, 65 kHz
Range 3,
MSI clock, 524 kHz VOS[1:0]=11,
VCORE=1.2 V
MSI clock, 4.2 MHz
DocID025937 Rev 2
fHCLK
Typ
Max(1)
16 MHz
665
830
32 MHz
1750
2100
65 kHz
18
65
524 kHz
31.5
75
4.2 MHz
140
210
Unit
µA
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Electrical characteristics
STM32L062K8
Table 27. Current consumption in Sleep mode (continued)
Symbol
Parameter
Conditions
Range 2,
VOS[1:0]=10,
Supply current
in Sleep
HSI16 clock source VCORE=1.5 V
mode, Flash
(16 MHz)
Range 1,
ON
VOS[1:0]=01,
IDD (Sleep)
fHCLK
Typ
Max(1)
16 MHz
680
950
32 MHz
1750
2100
VCORE=1.8 V
Supply current MSI clock, 65 kHz
in Sleep
Range 3,
MSI clock, 524 kHz
mode, code
VOS[1:0]=11,
executed from
VCORE=1.2V
MSI clock, 4.2 MHz
Flash
µA
65 kHz
29.5
110
524 kHz
44.5
130
4.2 MHz
150
270
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
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Unit
STM32L062K8
Electrical characteristics
Table 28. Current consumption in Low-power Run mode(1)
Symbol
Parameter
Typ
Max(2)
TA = -40 °C to 25 °C
8.5
10
TA = 85 °C
11.5
48
TA = 105 °C
15.5
53
TA = 125 °C
TBD
130
10
15
TA = 85 °C
15.5
50
TA = 105 °C
19.5
54
TA = 125 °C
-
130
TA = -40 °C to 25 °C
20
25
TA = 55 °C
23
50
TA = 85 °C
25.5
55
TA = 105 °C
29.5
64
TA = 125 °C
-
140
TA = -40 °C to 25 °C
22
28
TA = 85 °C
26
68
TA = 105 °C
31
75
TA = 125 °C
-
95
TA = -40 °C to 25 °C
27.5
33
TA = 85 °C
31.5
73
TA = 105 °C
36.5
80
TA = 125 °C
-
100
TA = -40 °C to 25 °C
39
46
TA = 55 °C
41
80
TA = 85 °C
44
86
TA = 105 °C
49.5
100
TA = 125 °C
-
120
-
TBD
Conditions
MSI clock, 65 kHz
fHCLK = 32 kHz
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
TA =-40 °C to 25 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
Supply
IDD
current in
(LP Run) Low-power
run mode
MSI clock, 65 kHz
fHCLK = 32 kHz
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
Max allowed
VDD from
IDD max current in
1.65 V to
(LP Run) Low-power
3.6 V
run mode
-
-
Unit
µA
1. TBD stands for “to be defined”.
2. Guaranteed by characterization results, not tested in production, unless otherwise specified.
DocID025937 Rev 2
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Electrical characteristics
STM32L062K8
Figure 10. IDD vs VDD, at TA= 25/55/ 85/105 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
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Table 29. Current consumption in Low-power Sleep mode(1)
Symbol
Parameter
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
IDD
(LP Sleep)
Supply
All peripherals
current in
OFF, VDD from
Low-power
1.65 V to 3.6 V
sleep mode
Typ
Max(2)
TA = -40 °C to 25 °C
4.7
TBD
TA = -40 °C to 25 °C
17
23
TA = 85 °C
19.5
63
TA = 105 °C
23
69
TA = 125 °C
-
90
TA = -40 °C to 25 °C
17
23
TA = 85 °C
20
63
TA = 105 °C
23.5
69
TA = 125 °C
-
90
19.5
36
20.5
64
22.5
66
26
72
-
95
TBD
TBD
Conditions
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
TA = -40 °C to 25 °C
T = 55 °C
MSI clock, 131 kHz A
TA = 85 °C
fHCLK = 131 kHz,
Flash ON
TA = 105 °C
TA = 125 °C
IDD max
(LP Sleep)
Max
allowed
VDD from 1.65 V
current in
to 3.6 V
Low-power
sleep mode
-
-
1. TBD stands for “to be defined”.
2. Guaranteed by characterization results, not tested in production, unless otherwise specified.
54/104
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µA
STM32L062K8
Electrical characteristics
Table 30. Typical and maximum current consumptions in Stop mode(1)
Symbol
Parameter
Conditions
1.1
1.9
TA = -40°C to 25°C
1.35
2.9
TA = 55°C
1.55
3.2
TA= 85°C
2.65
5.6
TA = 105°C
5
11
TA = 125 °C
-
26
TA = -40°C to 25°C
VDD = 1.8V
0.815
-
TA = -40°C to 25°C
VDD = 3.0V
1
-
TA = -40°C to 25°C
VDD = 3.6V
1.15
-
TA = 55°C
1.3
-
TA = 85°C
2.4
-
TA = 105°C
4.8
-
TA = 125°C
-
-
TA = -40°C to 25°C
1.4
-
TA = 55°C
1.85
-
LSE high drive TA= 85°C
3.05
-
TA = 105°C
5.5
-
TA = 125°C
-
-
Supply current
IDD (Stop in Stop mode
with RTC) with RTC
enabled
LSE low drive
RTC clocked by LSE
external quartz
(32.768kHz), regulator in
LP mode, HSI OFF (no
independent
watchdog(3)(4)
Max(2) Unit
TA = -40°C to 25°C
VDD = 1.8 V
RTC clocked by LSI,
regulator in LP mode,
HSI, LSE OFF (no
independent watchdog)
Supply current
IDD (Stop in Stop mode
with RTC) with RTC
enabled
Typ
DocID025937 Rev 2
µA
µA
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Electrical characteristics
STM32L062K8
Table 30. Typical and maximum current consumptions in Stop mode(1) (continued)
Symbol
Parameter
Conditions
Typ
TA = -40°C to 25°C
TBD
2.2
TA = 55°C
-
3.5
TA= 85°C
-
5.7
TA = 105°C
-
11
TA = 125°C
-
26
LPTIM1 enabled, regulator in LP mode,
HSI/LSE/LSI OFF (no independent
watchdog), 0 Hz external clock on
LPTIM1_IN1
-
-
LPTIM1 enabled, regulator in LP mode,
HSI/LSE/LSI OFF (no independent
watchdog), 100 Hz external clock on
LPTIM1_IN1
0.415
-
0.415
-
6
-
LPUART1 enabled, LSE Low drive
0.785
-
LPTIM1 and LPUART1 enabled LSE Low
drive
0.805
-
TA = -40°C to 25°C
0.415
1
TA = 55°C
0.63
2.1
TA= 85°C
1.7
4.5
TA = 105°C
4.05
9.6(5)
TA = 125°C
-
24
Reg in LP mode, LSE/HS OFF,
independent watchdog with LSI enabled
Supply current LPTIM1 enabled, regulator in LP mode,
HSI/LSE/LSI OFF (no independent
IDD (Stop) in Stop mode
(RTC disabled) watchdog), 100 KHz external clock on
LPTIM1_IN1
TA = -40°C to 25°C
LPTIM1 enabled. regulator in LP mode,
HS/LSE/LSI OFF (no independent
watchdog), 1 MHz external clock on
LPTIM1_IN1
Regulator in Low power mode,
LSI/LSE/HSI OFF (no independent
watchdog)
56/104
Max(2) Unit
DocID025937 Rev 2
µA
STM32L062K8
Electrical characteristics
Table 30. Typical and maximum current consumptions in Stop mode(1) (continued)
Symbol
Parameter
Conditions
Typ
TA = -40°C to 25°C
Regulator in Low power mode, HSI OFF,
LSE Bypass and independent watchdog
with LSI enabled
Supply current
in Stop mode
(LPTIM1
enabled)
Regulator in Low power mode, LSI/HSI
OFF, LSE Bypass (no independent
watchdog)
IDD (Stop)
TBD
-
TA = 55°C
-
-
TA= 85°C
-
-
TA = 105°C
-
-
TA = 125°C
-
-
TA = -40°C to 25°C
0.76
-
TA = 55°C
1.05
-
TA= 85°C
2.1
-
TA = 105°C
4.45
-
TA = 125°C
-
-
TBD
-
TA = 55°C
-
-
TA= 85°C
-
-
TA = 105°C
-
-
TA = 125°C
-
-
TA = -40°C to 25°C
0.785
-
TA = 55°C
1.05
-
TA= 85°C
2.15
-
TA = 105°C
4.45
-
TA = 125°C
-
-
TBD
-
TBD
-
TBD
-
TA = -40°C to 25°C
Regulator in Low power mode, HSI OFF,
LSE Bypass and independent watchdog
with LSI enabled
Supply current
in Stop mode
(LPUART1
enabled)
Regulator in Low power mode, LSI/HSI
OFF, LSE Bypass (no independent
watchdog)
Supply current MSI = 4.2 MHz
IDD
during wakeup
(WU from
MSI = 1.05 MHz
from Stop
Stop)
mode
MSI = 65 kHz(6)
Max(2) Unit
TA = -40°C to 25°C
µA
mA
1. TBD stands for “to be defined”.
2. Guaranteed by characterization results, not tested in production, unless otherwise specified.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
4. LSE Low drive unless otherwise specified.
5. Guaranteed by test in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part of
the wakeup period, the current corresponds the Run mode current.
DocID025937 Rev 2
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97
Electrical characteristics
STM32L062K8
Figure 11. IDD vs VDD, at TA= 25/55/ 85/105 °C, Stop mode with RTC enabled
and running on LSE Low drive
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Figure 12. IDD vs VDD, at TA= 25/55/85/105 °C, Stop mode with RTC disabled,
all clocks OFF
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58/104
DocID025937 Rev 2
STM32L062K8
Electrical characteristics
Table 31. Typical and maximum current consumptions in Standby mode(1)
Symbol
Parameter
Typ
Max(2)
TA = -40 °C to 25 °C,
VDD = 1.8 V
0.93
1.6
TA = -40 °C to 25 °C
1.2
1.9
TA = 55 °C
1.2
2.2
TA= 85 °C
1.4
3.2
TA = 105 °C
1.8
4
TA = 125 °C
-
9
TA = -40 °C to 25 °C,
VDD = 1.8 V
TBD
-
TA = -40 °C to 25 °C
TBD
TBD
-
TBD
-
TBD
TA = 105 °C
-
TBD
TA = 125 °C
-
TBD
0.285
TBD
0.29
TBD
0.32
TBD
0.5
TBD
TA = 105 °C
0.94
TBD
TA = 125 °C
-
TBD
TA = -40 °C to 25 °C,
VDD = 1.8 V
0.655
-
TA = -40 °C to 25 °C
0.845
-
TA = 55 °C
0.94
-
TA= 85 °C
1.15
-
TA = 105 °C
1.6
-
TA = 125 °C
-
-
TA = -40 °C to 25 °C,
VDD = 1.8 V
1
-
TA = -40 °C to 25 °C
1.2
-
TA = 55 °C
1.5
-
TA= 85 °C
1.8
-
TA = 105 °C
2.3
-
TA = 125 °C
-
-
Conditions
RTC clocked by LSI (no
independent watchdog)
RTC clocked by LSI (with T = 55 °C
A
independent watchdog)
TA= 85 °C
TA = -40 °C to 25 °C,
VDD = 1.8 V
TA = -40 °C to 25 °C,
IDD
RTC clocked by LSE (no
Supply current in Standby
(Standby
independent watchdog), TA = 55 °C
mode with RTC enabled
with RTC)
oscillator bypassed (3)
TA= 85 °C
RTC clocked by LSE
32.768 KHz external
quartz (no independent
watchdog), LSE low
drive(3)
RTC clocked by LSE
32.768 KHz external
quartz (no independent
watchdog), LSE high
drive(3)
DocID025937 Rev 2
Unit
µA
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97
Electrical characteristics
STM32L062K8
Table 31. Typical and maximum current consumptions in Standby mode(1) (continued)
Symbol
Parameter
Typ
Max(2)
TBD
1.7
TA = 55 °C
-
2.9
TA= 85 °C
-
3.3
TA = 105 °C
-
4.1
TA = 125 °C
-
8.5
TA = -40 °C to 25 °C
0.29
0.6
TA = 55 °C
0.32
0.9
TA = 85 °C
0.5
2.3
TA = 105 °C
0.94
3
TA = 125 °C
-
7
TBD
-
TBD
-
Conditions
TA = -40 °C to 25 °C
Supply current in Standby Independent watchdog
IDD
(Standby) mode (RTC disabled)
and LSI enabled
IDD
Supply current in Standby Independent watchdog
(Standby) mode (RTC disabled)
and LSI OFF
RMS supply current
IDD
during wakeup time when
(WU from
exiting from Standby
Standby)
mode
VDD = 3.6 V
VDD = 3.0 V
TA = -40 °C to 25 °C
Unit
µA
mA
1. TBD stands for “to be defined”.
2. Guaranteed by characterization results, not tested in production, unless otherwise specified
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
60/104
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
DocID025937 Rev 2
STM32L062K8
Electrical characteristics
Table 32. Peripheral current consumption(1)(2)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low-power
sleep and
run
WWDG
TBD
TBD
TBD
TBD
SPI2
TBD
TBD
TBD
TBD
LPUART
TBD
TBD
TBD
TBD
I2C1
TBD
TBD
TBD
TBD
I2C2
TBD
TBD
TBD
TBD
USB
TBD
TBD
TBD
TBD
DAC1
TBD
TBD
TBD
TBD
USART2
TBD
TBD
TBD
TBD
COMP1
TBD
TBD
TBD
TBD
COMP2
TBD
TBD
TBD
TBD
ADC1(3)
TBD
TBD
TBD
TBD
SPI1
TBD
TBD
TBD
TBD
USART1
TBD
TBD
TBD
TBD
TIM2
TBD
TBD
TBD
TBD
TIM21
TBD
TBD
TBD
TBD
TIM22
TBD
TBD
TBD
TBD
TIM6
TBD
TBD
TBD
TBD
GPIOA
TBD
TBD
TBD
TBD
GPIOB
Cortex-M0+
GPIOC
core I/O port
GPIOD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
GPIOH
TBD
TBD
TBD
TBD
CRC
TBD
TBD
TBD
TBD
FLASH
TBD
TBD
TBD
TBD
DMA1
TBD
TBD
TBD
TBD
All enabled
TBD
TBD
TBD
TBD
SYSCFG & RI
TBD
TBD
TBD
TBD
PWR
TBD
TBD
TBD
TBD
Peripheral
APB1
APB2
AHB
DocID025937 Rev 2
Unit
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
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97
Electrical characteristics
STM32L062K8
Table 32. Peripheral current consumption(1)(2) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
IDD (RTC)
TBD
IDD (ADC)(4)
TBD
IDD (DAC)(5)
TBD
IDD (COMP1)
TBD
IDD (COMP2)
IDD (PVD / BOR)
Slow mode
TBD
Fast mode
TBD
(6)
TBD
Low-power
sleep and
run
Unit
µA
TBD
IDD (IWDG)
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. TBD stands for “to be defined”.
3. HSI oscillator is OFF for this measure.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 21.
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DocID025937 Rev 2
STM32L062K8
Electrical characteristics
Table 33. Low-power mode wakeup timings
Symbol
tWUSLEEP
tWUSLEEP_LP
Parameter
Wakeup from Sleep mode
Max(1) Unit
TBD
-
fHCLK = 262 kHz
Flash enabled
TBD
-
fHCLK = 262 kHz
Flash switched OFF
TBD
-
fHCLK = fMSI = 4.2 MHz
TBD
-
fHCLK = fHSI = 16 MHz
TBD
-
fHCLK = fHSI/4 = 4 MHz
TBD
-
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
TBD
TBD
fHCLK = fMSI = 4.2 MHz
Voltage range 3
TBD
TBD
fHCLK = fMSI = 2.1 MHz
TBD
TBD
fHCLK = fMSI = 1.05 MHz
TBD
TBD
fHCLK = fMSI = 524 kHz
TBD
TBD
fHCLK = fMSI = 262 kHz
TBD
TBD
fHCLK = fMSI = 131 kHz
TBD
TBD
fHCLK = MSI = 65 kHz
TBD
TBD
fHCLK = fHSI = 16 MHz
TBD
-
fHCLK = fHSI/4 = 4 MHz
TBD
-
fHCLK = fHSI = 16 MHz
TBD
TBD
fHCLK = fHSI/4 = 4 MHz
TBD
TBD
fHCLK = fMSI = 4.2 MHz
TBD
TBD
Wakeup from Standby mode
FWU bit = 1
fHCLK = MSI = 2.1 MHz
TBD
TBD
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
TBD
TBD
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
Wakeup from Stop mode,
regulator in low-power mode
Wakeup from Stop mode,
regulator in low-power mode,
code running from RAM
tWUSTDBY
Typ
fHCLK = 32 MHz
Wakeup from Stop mode,
regulator in Run mode
tWUSTOP
Conditions
µs
ms
1. Guaranteed by characterization results, not tested in production, unless otherwise specified
6.3.6
External clock source characteristics
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97
Electrical characteristics
STM32L062K8
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 21.
Table 34. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSE)
tw(LSE)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
CIN(LSE)
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
-
-
10
-
-
0.6
-
pF
-
45
-
55
%
VSS ≤ VIN ≤ VDD
-
-
±1
µA
OSC32_IN input capacitance
DuCy(LSE) Duty cycle
IL
Min
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production
Figure 13. Low-speed external clock source AC timing diagram
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 35. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
64/104
DocID025937 Rev 2
STM32L062K8
Electrical characteristics
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 35. LSE oscillator characteristics(1)
Symbol
fLSE
Gm
Conditions(2)
Min(2)
Typ
Max
Unit
-
32.768
-
kHz
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
LSEDRV[1:0]= 01
medium low driving capability
-
-
0.75
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.7
LSEDRV[1:0]=11
higher driving capability
-
-
2.7
VDD is stabilized
-
2
-
Parameter
LSE oscillator frequency
Maximum critical crystal
transconductance
tSU(LSE)(3) Startup time
µA/V
s
1. Guaranteed by design, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST
microcontrollers”.
3. Guaranteed by characterization results, not tested in production. tSU(LSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a
high- driver mode.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 14. Typical application with a 32.768 kHz crystal
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Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DocID025937 Rev 2
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97
Electrical characteristics
6.3.7
STM32L062K8
Internal clock source characteristics
The parameters given in Table 36 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 21.
High-speed internal 16 MHz (HSI16) RC oscillator
Table 36. 16 MHz HSI16 oscillator characteristics
Symbol
fHSI16
TRIM
(1)(2)
ACCHSI16
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI16 usertrimmed resolution
Trimming code is not a multiple of 16
-
± 0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
factory-calibrated
HSI16 oscillator
-
± 1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C
-4
-
3
%
tSU(HSI16)(2)
HSI16 oscillator
startup time
-
-
3.7
6
µs
IDD(HSI16)(2)
HSI16 oscillator
power consumption
-
-
100
140
µA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
Figure 15. HSI16 minimum and maximum value versus temperature
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DocID025937 Rev 2
STM32L062K8
Electrical characteristics
High-speed internal 48 MHz (HSI48) RC oscillator
Table 37. HSI48 oscillator characteristics(1)(2)
Symbol
fHSI48
TRIM
Parameter
Conditions
Frequency
Min
Typ
Max
Unit
-
48
-
MHz
(3)
HSI48 user-trimming step
0.09
DuCy(HSI48) Duty cycle
0.14
(3)
%
(3)
%
0.2
(3)
-
55
-4(4)
-
4(4)
%
45
ACCHSI48
Accuracy of the HSI48
oscillator (factory calibrated
before CRS calibration)
tsu(HSI48)
HSI48 oscillator startup time
-
-
6(3)
µs
HSI48 oscillator power
consumption
-
TBD
380(3)
µA
IDDA(HSI48)
TA = 25 °C
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. TBD stands for “to be defined”.
3. Guaranteed by design, not tested in production.
4. Guaranteed by characterization results, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 38. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI(1)
LSI frequency
26
38
56
kHz
DLSI(2)
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
-10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
tsu(LSI)(3)
IDD(LSI)
(3)
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
DocID025937 Rev 2
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97
Electrical characteristics
STM32L062K8
Multi-speed internal (MSI) RC oscillator
Table 39. MSI oscillator characteristics
Symbol
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
fMSI
ACCMSI
IDD(MSI)(2)
tSU(MSI)
68/104
Parameter
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI oscillator power consumption
MSI oscillator startup time
DocID025937 Rev 2
Max Unit
kHz
MHz
µA
µs
STM32L062K8
Electrical characteristics
Table 39. MSI oscillator characteristics (continued)
Symbol
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
Typ
Max Unit
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
µs
MHz
6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results, not tested in production.
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97
Electrical characteristics
6.3.8
STM32L062K8
PLL characteristics
The parameters given in Table 40 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 21.
Table 40. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
Worst case PLL lock time
PLL input = 2 MHz
PLL VCO = 96 MHz
-
TBD
TBD
µs
Jitter
Cycle-to-cycle jitter
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
µA
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 41. RAM and hardware registers
Symbol
VRM
Parameter
Conditions
Data retention mode(1)
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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STM32L062K8
Electrical characteristics
Flash memory and data EEPROM
Table 42. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
TBD
TBD
µA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
TBD
TBD
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming time for
word or half-page
IDD
ms
1. Guaranteed by design, not tested in production.
Table 43. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC(2)
Parameter
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
tRET(2)
Data retention (EEPROM data memory)
after 100 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
Conditions
TA = -40°C to
105 °C
Min(1) Typ Max
10
-
Unit
kcycles
100
-
-
30
-
-
30
-
-
TRET = +85 °C
years
10
-
-
10
-
-
TRET = +105 °C
1. Guaranteed by characterization results, not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
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Electrical characteristics
6.3.10
STM32L062K8
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 3.3 V, LQFP100, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
72/104
DocID025937 Rev 2
STM32L062K8
Electrical characteristics
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 45. EMI characteristics
Max vs. frequency range
Symbol Parameter
SEMI
6.3.11
Conditions
VDD = 3.3 V,
TA = 25 °C,
Peak level LQFP100 package
compliant with IEC
61967-2
Monitored
frequency band
4 MHz
16 MHz 32 MHz
voltage voltage voltage
range 3 range 2 range 1
0.1 to 30 MHz
3
-6
-5
30 to 130 MHz
18
4
-7
130 MHz to 1GHz
15
5
-7
SAE EMI Level
2.5
2
1
Unit
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 46. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
TA = +25 °C,
Electrostatic discharge
conforming to
voltage (human body model)
ANSI/JEDEC JS-001
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C,
conforming to
ANSI/ESD STM5.3.1.
Class
Maximum
value(1)
2
2000
Unit
V
C4
500
1. Guaranteed by characterization results, not tested in production.
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97
Electrical characteristics
STM32L062K8
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 47. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 48.
Table 48. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Injected current on BOOT0
IINJ
Injected current on all FT pins
Injected current on any other pin
Negative
injection
Positive
injection
-0
NA
-5 (1)
NA
(1)
+5
-5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
74/104
DocID025937 Rev 2
Unit
mA
STM32L062K8
6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 21. All I/Os are CMOS and TTL
compliant.
Table 49. I/O static characteristics(1)
Symbol
VIL
VIH
Vhys
Ilkg
RPU
Parameter
Input low level voltage
Conditions
Min
Typ
Max
TC, FT, FTf, RST
I/Os
-
-
0.3VDD
BOOT0 pin
-
-
0.14VDD(2)
All I/Os
0.7 VDD
-
-
Standard I/Os
-
10% VDD(4)
-
BOOT0 pin
-
0.01
-
VSS ≤ VIN ≤ VDD
I/Os with analog
switches
-
-
±50
VSS ≤ VIN ≤ VDD
I/Os with USB
-
-
250
VSS ≤ VIN ≤ VDD
Standard I/Os
-
-
±50
nA
FT I/O
VDD≤ VIN ≤ 5 V
-
-
±10
µA
VIN = VSS
30
45
60
kΩ
VIN = VDD
30
45
60
kΩ
-
-
5
-
pF
Input high level voltage
I/O Schmitt trigger voltage hysteresis
(3)
Input leakage current
(5)
Weak pull-up equivalent resistor(6)
RPD
Weak pull-down equivalent
CIO
I/O pin capacitance
resistor(6)
Unit
V
1. TBD stands for “to de defined’.
2. Guaranteed by characterization, not tested in production
3. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production.
4. With a minimum of 200 mV. Guaranteed by characterization results, not tested in production.
5. The max. value may be exceeded if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics
STM32L062K8
Figure 16. VIH/VIL versus VDD (CMOS I/Os)
9,/9,+9
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DOOS 9 '' 3+
3&
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9 ,+PLQ 3&
7
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9,/9,+9
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DOO
3+
'
'
9
3&
9 ,+PLQ W%227 IRU
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard VOL/VOH specifications given in Table 50.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
76/104
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 19).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 19).
DocID025937 Rev 2
STM32L062K8
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 21. All I/Os are CMOS and TTL compliant.
Table 50. Output voltage characteristics
Symbol
Parameter
VOL(1)
Output low level voltage for an I/O
pin
VOH(3)
Output high level voltage for an I/O
pin
Conditions
Min
Max
CMOS port(2),
IIO = +8 mA
2.7 V ≤ VDD ≤ 3.6 V
-
0.4
VDD-0.4
-
(1)
Output low level voltage for an I/O
pin
TTL port(2),
IIO =+ 8 mA
2.7 V ≤ VDD ≤ 3.6 V
-
0.4
(3)(4)
Output high level voltage for an I/O
pin
TTL port(2),
IIO = -6 mA
2.7 V ≤ VDD ≤ 3.6 V
2.4
-
VOL(1)(4)
Output low level voltage for an I/O
pin
IIO = +15 mA
2.7 V ≤ VDD ≤ 3.6 V
-
1.3
VOH(3)(4)
Output high level voltage for an I/O
pin
IIO = -15 mA
2.7 V ≤ VDD ≤ 3.6 V
VDD-1.3
-
VOL(1)(4)
Output low level voltage for an I/O
pin
IIO = +4 mA
1.65 V ≤ VDD < 3.6 V
-
0.45
VOH(3)(4)
Output high level voltage for an I/O
pin
IIO = -4 mA
V -0.45
1.65 V ≤ VDD ≤ 3.6 V DD
VOL
VOH
Output low level voltage for an FTf
VOLFM+(1)(4)
I/O pin in Fm+ mode
Unit
V
-
IIO = 20 mA
2.7 V ≤ VDD ≤ 3.6 V
-
0.4
IIO = 10 mA
1.65 V ≤ VDD ≤ 3.6 V
-
0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 19.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 19. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN).
4. Guaranteed by characterization results, not tested in production.
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97
Electrical characteristics
STM32L062K8
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 21.
Table 51. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
Fm+
configuration
(4)
-
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
TBD
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
TBD
-
TBD
-
TBD
-
TBD
Conditions
fmax(IO)out
tf(IO)out
tr(IO)out
Min
Parameter
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
Output fall time
CL = 50 pF
tr(IO)out
Output rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
-
8
-
2. Guaranteed by design. Not tested in production.
3. The maximum frequency is defined in Figure 18.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed
description of Fm+ I/O configuration.
DocID025937 Rev 2
kHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO
Port configuration register.
78/104
Unit
STM32L062K8
Electrical characteristics
Figure 18. I/O AC characteristics definition
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6.3.14
DLG
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU , except when it is internally driven low (see Table 52).
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 21.
Table 52. NRST pin characteristics(1)
Symbol
VIL(NRST)
(2)
Parameter
Conditions
Min
Typ
NRST input low level voltage
-
VSS
-
0.8
-
1.4
-
VDD
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
-
-
10%VDD(3)
-
mV
Weak pull-up equivalent
resistor(4)
VIN = VSS
30
45
60
kΩ
NRST input filtered pulse
-
-
-
TBD
ns
NRST input not filtered pulse
-
TBD
-
-
ns
VIH(NRST)(1) NRST input high level voltage
NRST output low level
VOL(NRST)(1)
voltage
Vhys(NRST)(1)
RPU
VF(NRST)(1)
VNF(NRST)
(1)
NRST Schmitt trigger voltage
hysteresis
Max Unit
V
0.4
1. TBD stands for “to be defined”.
2. Guaranteed by design, not tested in production.
3. 200 mV minimum value
4. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
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Electrical characteristics
STM32L062K8
Figure 19. Recommended NRST pin protection
9''
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DLF
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 53 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 53. ADC characteristics(1)
Symbol
VDDA
IDDA (ADC)
Parameter
Conditions
Analog supply voltage for
ADC ON
Min
Typ
Max
Unit
1.8
-
3.6
V
Current consumption of the
ADC on VDDA
1.14 Msps
-
200
-
10 ksps
-
40
-
Current consumption of the
ADC on VDD(2)
1.14 Msps
-
70
-
10 ksps
-
1
-
µA
fADC
ADC clock frequency
0.6
-
16
MHz
fS(3)
Sampling rate
0.05
-
1.14
MHz
-
-
941
kHz
-
-
17
1/fADC
0
-
VDDA
V
-
-
50
kΩ
fADC = 16 MHz
fTRIG(3)
External trigger frequency
VAIN
Conversion voltage range
RAIN(3)
External input impedance
RADC(3)
Sampling switch resistance
-
-
1
kΩ
CADC(3)
Internal sample and hold
capacitor
-
-
8
pF
tCAL(3)
Calibration time
80/104
See Equation 1 and
Table 54 for details
fADC = 16 MHz
DocID025937 Rev 2
5.2
µs
83
1/fADC
STM32L062K8
Electrical characteristics
Table 53. ADC characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
ADC clock = HSI14
WLATENCY
tlatr
(3)
JitterADC
ADC_DR register write
latency
Trigger conversion latency
fADC = fPCLK/2 = 16 MHz
0.172
µs
fADC = fPCLK/2
5.5
1/fPCLK
fADC = fPCLK/4 = 8 MHz
0.172
µs
fADC = fPCLK/4
10.5
1/fPCLK
fADC = fHSI16 = 16 MHz
TBD
-
TBD
µs
fADC = fHSI14
-
1
-
1/fHSI14
fADC = 16 MHz
0.093
-
15
µs
1.5
-
239.5
1/fADC
0
0
1
µs
15.75
µs
ADC jitter on trigger
conversion
tS(3)
Sampling time
tSTAB(3)
Power-up time
tCONV(3)
Total conversion time
(including sampling time)
fADC = 16 MHz
1
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. TBD stands for “to be defined”.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 32: Peripheral current
consumption).
3. Guaranteed by design, not tested in production.
Equation 1: RAIN max formula
TS
- – R ADC
R AIN < ------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
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STM32L062K8
Table 54. RAIN max for fADC = 14 MHz
Ts (cycles)
tS (µs)
RAIN max (kΩ)(1)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 55. ADC accuracy(1)(2)(3)
Symbol
Parameter
Min
Typ
Max
ET
Total unadjusted error
-
2
4
EO
Offset error
-
1
2.5
EG
Gain error
-
1
2
EL
Integral linearity error
-
1.5
2.5
ED
Differential linearity error
-
1
1.5
ENOB
Effective number of bits
10.2
11
-
SINAD
Signal-to-noise distortion
63
69
-
SNR
Signal-to-noise ratio
63
69
-
THD
Total harmonic distortion
-85
-73
Unit
LSB
bits
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
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Electrical characteristics
Figure 20. ADC accuracy characteristics
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Figure 21. Typical connection diagram using the ADC
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1. Refer to Table 53: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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Electrical characteristics
6.3.16
STM32L062K8
DAC electrical specifications
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 56. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.8
-
3.6
V
VDDA
Analog supply voltage
IDDA(1)
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
-
340
340
-
340
340
RL(1)
Resistive load
5
-
-
kΩ
-
-
50
pF
DAC output buffer OFF
6
8
10
kΩ
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
1.5
3
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
1.5
3
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
2
4
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
±10
±25
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
±5
±8
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
±1.5
±5
-20
-10
0
CL
(1)
Capacitive load
RO
Output impedance
DNL
Differential non
linearity(2)
(1)
(1)
INL
Offset(1)
Offset1(1)
Integral non
linearity(3)
Offset error at code
0x800 (4)
Offset error at code
0x001(5)
DAC output buffer ON
VDDA = 3.3V
TA = 0 to 50 °C
Offset error temperature DAC output buffer OFF
dOffset/dT(1)
coefficient (code 0x800) V
= 3.3V
µA
LSB
µV/°C
DDA
TA = 0 to 50 °C
DAC output buffer ON
Gain(1)
dGain/dT(1)
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Gain error(6)
Gain error temperature
coefficient
0
20
50
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
+0.1 / -0.2%
+0.2 / -0.5%
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
+0 / -0.2%
+0 / -0.4%
VDDA = 3.3V
TA = 0 to 50 °C
DAC output buffer OFF
-10
-2
0
VDDA = 3.3V
TA = 0 to 50 °C
DAC output buffer ON
-40
DocID025937 Rev 2
%
µV/°C
-8
0
STM32L062K8
Electrical characteristics
Table 56. DAC characteristics (continued)
Symbol
Min
Typ
Max
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
12
30
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
-
8
12
tSETTLING
Settling time (full scale:
for a 12-bit code
transition between the
lowest and the highest
CL ≤ 50 pF, RL ≥ 5 kΩ
input codes till
DAC_OUT reaches final
value ±1LSB
-
7
12
µs
Update rate
Max frequency for a
correct DAC_OUT
change (95% of final
value) with 1 LSB
variation in the input
code
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
tWAKEUP
Wakeup time from off
state (setting the ENx bit
CL ≤ 50 pF, RL ≥ 5 kΩ
in the DAC Control
(7)
register)
-
9
15
µs
PSRR+
VDDA supply rejection
ratio (static DC
measurement)
-
-60
-35
dB
TUE(1)
Parameter
Conditions
Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
Unit
LSB
1. Connected between DAC_OUT and VSSA.
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x800) and the ideal value = /2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
7. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 22. 12-bit buffered/non-buffered DAC
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Electrical characteristics
6.3.17
STM32L062K8
Temperature sensor characteristics
Table 57. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3 V
0x1FF8 007A - 0x1FF8 007B
TS_CAL2
TS ADC raw data acquired at
temperature of 130 °C
VDDA= 3 V
0x1FF8 007E - 0x1FF8 007F
Table 58. Temperature sensor characteristics
Symbol
Parameter
TL(1)
VSENSE linearity with temperature
Avg_Slope(1)
Average slope
V130
Voltage at 130°C
I
±5°C(2)
Min
Typ
Max
Unit
-
±1
±2
°C
1.48
1.61
1.75
mV/°C
640
670
700
mV
µA
Current consumption
-
3.4
6
tSTART(3)
Startup time
-
-
10
TS_temp(4)(3)
ADC sampling time when reading the
temperature
10
-
-
(3)
DDA(TEMP)
µs
1. Guaranteed by characterization results, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
6.3.18
Comparators
Table 59. Comparator 1 characteristics
Symbol
Conditions
Min(1)
Typ
Max(1)
Unit
3.6
V
VDDA
Analog supply voltage
-
1.65
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input
voltage range
-
0.6
-
VDDA
Comparator startup time
-
-
7
10
VIN
tSTART
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Parameter
(2)
td
Propagation delay
-
-
3
10
Voffset
Comparator offset
-
-
±3
±10
DocID025937 Rev 2
kΩ
V
µs
mV
STM32L062K8
Electrical characteristics
Table 59. Comparator 1 characteristics (continued)
Symbol
dVoffset/dt
ICOMP1
Min(1)
Typ
Max(1)
Unit
VDDA = 3.6 V
Comparator offset
VIN+ = 0 V
variation in worst voltage
VIN- = VREFINT
stress conditions
TA = 25 °C
0
1.5
10
mV/1000 h
Current consumption(3)
-
160
260
nA
Parameter
Conditions
-
1. Guaranteed by characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 60. Comparator 2 characteristics
Symbol
VDDA
VIN
Parameter
Min
Analog supply voltage
-
1.65
-
3.6
V
Comparator 2 input voltage range
-
0
-
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V ≤ VDDA ≤ 2.7 V
-
1.8
3.5
2.7 V ≤ VDDA ≤ 3.6 V
-
2.5
6
1.65 V ≤ VDDA ≤ 2.7 V
-
0.8
2
2.7 V ≤ VDDA ≤ 3.6 V
-
1.2
4
-
±4
±20
mV
VDDA = 3.3V
TA = 0 to 50 °C
V- =VREFINT,
3/4 VREFINT,
1/2 VREFINT,
1/4 VREFINT.
-
15
30
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
tSTART
Comparator startup time
td slow
Propagation delay(2) in slow mode
td fast
Propagation delay(2) in fast mode
Voffset
Comparator offset error
dThreshold/ Threshold voltage temperature
dt
coefficient
ICOMP2
Typ Max(1) Unit
Conditions
Current consumption(3)
µs
µA
1. Guaranteed by characterization results, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
6.3.19
Timer characteristics
TIM timer characteristics
The parameters given in the Table 61 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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Table 61. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
fTIMxCLK = 32 MHz
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz
Timer resolution
-
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
-
tMAX_COUNT Maximum possible count
Min
Max
Unit
1
-
tTIMxCLK
31.25
-
ns
0
fTIMxCLK/2
MHz
0
16
MHz
16
bit
65536
tTIMxCLK
2048
µs
1
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.
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6.3.20
Electrical characteristics
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm) : with a bit rate up to 100 kbit/s
•
Fast-mode (Fm) : with a bit rate up to 400 kbit/s
•
Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The I2C timing requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual for details). The SDA and SCL I/O requirements
are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.
When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
All I2C SDA and SCL I/Os embed an analog filter (see Table 62 for the analog filter
characteristics).
Table 62. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
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Electrical characteristics
STM32L062K8
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 21.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 63. SPI characteristics in voltage Range 1 (1)
Symbol
Parameter
Conditions
Min
Typ
-
-
Slave mode Transmitter
1.71<VDD<3.6V
-
-
12(2)
Slave mode Transmitter
2.7<VDD<3.6V
-
-
16(2)
Master mode
Slave mode receiver
fSCK
1/tc(SCK)
SPI clock frequency
Max
16
16
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
8.5
-
-
Slave mode
8.5
-
-
Master mode
6
-
-
Slave mode
1
-
-
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO
Data output access time
Slave mode
15
-
36
tdis(SO)
Data output disable time
Slave mode
10
-
30
Slave mode 1.71<VDD<3.6V
-
29
41
Slave mode 2.7<VDD<3.6V
-
22
28
Master mode
-
10
17
Slave mode
9
-
-
Master mode
3
-
-
tv(SO)
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
Unit
MHz
%
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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Electrical characteristics
Table 64. SPI characteristics in voltage Range 2 (1)
Symbol
Parameter
Conditions
Min
Typ
Master mode
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode Transmitter
1.65<VDD<3.6V
Max
8
-
-
Slave mode Transmitter
2.7<VDD<3.6V
8
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
12
-
-
Slave mode
11
-
-
Master mode
6.5
-
-
Slave mode
2
-
-
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO
Data output access time
Slave mode
18
-
52
tdis(SO)
Data output disable time
Slave mode
12
-
42
tv(SO)
Data output valid time
40
55
tv(MO)
th(SO)
Data output hold time
Slave mode
MHz
8(2)
Duty(SCK)
tsu(MI)
Unit
-
Master mode
-
16
26
Slave mode
12
-
-
Master mode
4
-
-
%
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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Electrical characteristics
STM32L062K8
Table 65. SPI characteristics in voltage Range 3 (1)
Symbol
Parameter
Min
Typ
fSCK
1/tc(SCK)
SPI clock frequency
-
-
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
28.5
-
-
Slave mode
22
-
-
Master mode
7
-
-
Slave mode
5
-
-
tsu(MI)
Conditions
Data input setup time
tsu(SI)
th(MI)
Data input hold time
th(SI)
Master mode
Slave mode
Max
2
Data output access time
Slave mode
30
-
70
tdis(SO)
Data output disable time
Slave mode
40
-
80
tv(SO)
Data output valid time
Slave mode
-
53
86
Master mode
-
30
54
Slave mode
18
-
-
Master mode
8
-
-
Data output hold time
th(SO)
MHz
2(2)
ta(SO
tv(MO)
Unit
%
ns
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 23. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
tSU(NSS)
SCK Input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
B I T1 IN
LSB IN
th(SI)
ai14134c
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Electrical characteristics
Figure 24. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA=1
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
th(SO)
MS B O UT
tsu(SI)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Figure 25. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
CPHA= 0
CPOL=0
SCK Input
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTPUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
STM32L062K8
I2S characteristics
Table 66. I2S characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
-
256 x 8K
256xFs (2)
MHz
fCK
I2S clock frequency
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
DCK
I2S clock frequency duty
cycle
Slave receiver
30
70
tv(WS)
WS valid time
Master mode
-
15
th(WS)
WS hold time
Master mode
11
-
tsu(WS)
WS setup time
Slave mode
6
-
th(WS)
WS hold time
Slave mode
2
-
Master receiver
18
-
Slave receiver
16
-
Master receiver
11
-
Slave receiver
0
-
Slave transmitter (after enable edge)
-
77
Master transmitter (after enable edge)
-
26
Slave transmitter (after enable edge)
8
-
Master transmitter (after enable edge)
3
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
MHz
%
ns
1. Guaranteed by characterization results, not tested in production.
2. 256xFs maximum value is equal to the maximum clock frequency.
Note:
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Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Electrical characteristics
Figure 26. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 27. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. Guaranteed by characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
STM32L062K8
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 67. USB startup time
Symbol
tSTARTUP
(1)
Parameter
USB transceiver startup time
Max
Unit
1
µs
1. Guaranteed by design, not tested in production.
Table 68. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
-
3.0
3.6
V
0.2
-
Input levels
VDD
USB operating voltage
VDI(2)
Differential input sensitivity
VCM(2)
Differential common mode range Includes VDI range
0.8
2.5
VSE(2)
Single ended receiver threshold
1.3
2.0
-
0.3
2.8
3.6
I(USB_DP, USB_DM)
-
V
Output levels
VOL(3)
VOH
(3)
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(4)
RL of 15 kΩ to
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
4. RL is the load connected on the USB drivers.
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V
STM32L062K8
Electrical characteristics
Figure 28. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tr
tf
ai14137
Table 69. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
CL = 50 pF
4
20
ns
tf
Time(2)
CL = 50 pF
4
20
ns
tr/tf
90
110
%
1.3
2.0
V
trfm
VCRS
Fall
Rise/ fall time matching
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
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97
Package characteristics
STM32L062K8
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at http://www.st.com.
ECOPACK® is an ST trademark.
7.1.1
UFQFPN32 5 x 5 mm package
Figure 29. UFQFPN32, 5 x 5 mm, 32-pin package outline
!"?-%?6
1. Drawing is not to scale.
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Package characteristics
Table 70. UFQFPN32, 5 x 5 mm, 32-pin package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
A3
-
0.200
-
-
0.0079
-
b
0.180
0.250
0.300
0.0071
0.0098
0.0118
D
4.900
5.000
5.100
0.1929
0.1969
0.2008
D2
3.200
3.450
3.700
0.1260
0.1358
0.1457
E
4.900
5.000
5.100
0.1929
0.1969
0.2008
E2
3.200
3.450
3.700
0.1260
0.1358
0.1457
e
-
0.500
-
-
0.0197
-
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 30. UFQFPN32 recommended footprint
$%B)3B9
1. Dimensions are expressed in millimeters.
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Package characteristics
STM32L062K8
Device marking
Figure 31. UFQFPN32 marking (package top view)
(QJLQHHULQJVDPSOH
PDUNLQJ
(
'DWHFRGH <HDUZHHN
<HDU
:HHN
$GGLWLRQDOLQIRUPDWLRQ
ILHOGLQFOXGLQJUHYLVLRQ
FRGH
069
1. Samples marked "E" are to be considered as "Engineering Samples": i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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7.2
Package characteristics
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 71. Thermal characteristics
Symbol
ΘJA
Parameter
Thermal resistance junction-ambient
UFQFPN32 - 5 x 5 mm / 0.5 mm pitch
Value
Unit
38
°C/W
Figure 32. Thermal resistance
)RUELGGHQDUHD7-!7-PD[
3' P :
/4)3[PP
7HPSHUDWXUHƒ&
06Y9
7.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Ordering information
8
STM32L062K8
Ordering information
Table 72. STM32L062K8 ordering information scheme
Example:
STM32 L 062
K
8
T
6
D xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
062 = USB + AES
Pin count
K = 32 pins
Flash memory size
8 = 64 Kbytes
Package
U = UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Revision history
Revision history
Table 73. Document revision history
Date
Revision
19-Feb-2014
1
Initial release.
2
HSE clock removed in the whole document.
Updated Table 4: Functionalities depending on the working mode (from
Run/active down to standby). Added Section 3.2: Interconnect matrix.
Replaced TTa I/O structure by TC, updated PA0/4/5, PC5/14, BOOT0
and NRST I/O structure, and added note 2. in Table 15: STM32L062K8
pin definitions.
Updated Table 18: Voltage characteristics and Table 19: Current
characteristics.
Updated Table 25: Current consumption in Run mode, code with data
processing running from Flash and Table 26: Current consumption in
Run mode, code with data processing running from RAM, Table 27:
Current consumption in Sleep mode, Table 28: Current consumption in
Low-power Run mode, Table 29: Current consumption in Low-power
Sleep mode, Table 30: Typical and maximum current consumptions in
Stop mode and Table 31: Typical and maximum current consumptions in
Standby mode. Added Figure 9: IDD vs VDD, at TA= 25/55/85/105 °C,
Run mode, code running from Flash memory, Range 2, HSI16, 1WS,
Figure 10: IDD vs VDD, at TA= 25/55/ 85/105 °C, Low-power run mode,
code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS,
Figure 11: IDD vs VDD, at TA= 25/55/ 85/105 °C, Stop mode with RTC
enabled and running on LSE Low drive and Figure 12: IDD vs VDD, at
TA= 25/55/85/105 °C, Stop mode with RTC disabled, all clocks OFF.
Updated Table 35: LSE oscillator characteristics. Added Figure 15:
HSI16 minimum and maximum value versus temperature.
Updated Table 46: ESD absolute maximum ratings, Table 48: I/O
current injection susceptibility and Table 49: I/O static characteristics,
and added Figure 16: VIH/VIL versus VDD (CMOS I/Os) and Figure 17:
VIH/VIL versus VDD (TTL I/Os). Updated Table 50: Output voltage
characteristics, Table 51: I/O AC characteristics and Figure 18: I/O AC
characteristics definition.
Updated Table 53: ADC characteristics, Table 55: ADC accuracy, and
Figure 21: Typical connection diagram using the ADC. Updated
Table 58: Temperature sensor characteristics.
Updated Table 63: SPI characteristics in voltage Range 1 and Table 66:
I2S characteristics.
Added Figure 32: Thermal resistance.
29-Apr-2014
Changes
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