datasheet for R32C/117A by Renesas Electronics Corporation

datasheet for R32C/117A by Renesas Electronics Corporation

R32C/117A Group Datasheet

Datasheet

R32C/117A Group

RENESAS MCU

REJ03B0298-0100

Rev.1.00

Jul 16, 2010

1.

Overview

1.1

Features

The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields.

The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture, multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of onchip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I

2

C, and WDT enables to minimize external components.

The R32C/100 Series, in particular, provides the R32C/117A Group as a standard product. This product, provided as a 144/176-pin plastic molded LQFP package, configures 11 channels of serial interface, one channel of multi-master I

2

C-bus interface, and one channel of CAN module.

1.1.1

Applications

Car audio, audio, printer, office/industrial equipment, etc.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 1 of 113

R32C/117A Group 1. Overview

1.1.2

Performance Overview

Table 1.1 to Table 1.4 show the performance overview of the R32C/117A Group.

Table 1.1

R32C/117A Group Performance for the 176 pin-Package (1/2)

CPU

Unit

Memory

Voltage

Detector

Function

Central processing unit

Low voltage detector

Performance

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit $ 64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit $ 64-bit

• IEEE-754 floating point standard: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional

(1)

)

Flash memory: 512 Kbytes to 1 Mbyte

RAM: 96 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for memory size of each product group

Optional

(1)

Low voltage detection interrupt

Clock

External Bus

Expansion

Interrupts

Watchdog Timer

Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/re-oscillation detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

Bus and memory expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16/32 bits)

Interrupt vectors: 261

External interrupt inputs: NMI, INT × 9, key input × 4

Interrupt priority levels: 7 levels

DMA DMAC

15 bits × 1 (selectable input frequency from prescaler output)

• Automatic timer start function is available

4 channels

• Cycle-steal transfer mode

• Request sources: 61

• 2 transfer modes: Single transfer, repeat transfer

I/O Ports

DMAC II

Programmable

I/O ports

• Can be activated by any peripheral interrupt source

• 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer

• 2 input-only ports

• 156 CMOS inputs/outputs

• 52 ports are 5 V tolerant

• A pull-up resistor is selectable for every 4 input ports (except 5 V tolerant inputs)

Note:

1.

Please contact a Renesas Electronics sales office to use the optional feature.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 2 of 113

R32C/117A Group 1. Overview

Table 1.2

Timer

Unit

Serial

Interface

A/D Converter

D/A Converter

CRC Calculator

X-Y Converter

Intelligent I/O

CAN Module

Flash Memory

R32C/117A Group Performance for the 176-pin Package (2/2)

Function

Timer A

Timer B

Three-phase motor control timer

UART0 to

UART10

Performance

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3

16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Multi-master I

2

C-bus Interface

Asynchronous/synchronous serial interface × 11 channels

• I

2

C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional

(1)

) (UART0 to UART6)

10-bit resolution × 34 channels

Sample and hold functionality integrated

Self test/Open-circuit detection assist

8-bit resolution × 2

CRC-CCITT (X

16

+ X

12

+ X

5

+ 1)

16 bits × 16 bits

Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 24

Serial interface: Variable-length synchronous serial I/O mode, IEBus mode (optional

(1)

)

1 channel

1 channel

CAN functionality compliant with ISO11898-1

32 mailboxes

Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Suspend/resume function available

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

64 MHz/VCC = 3.0 to 5.5 V Operating Frequency/Supply

Voltage

Operating Temperature

Current Consumption

Package

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

176-pin plastic molded LQFP (PLQP0176KB-A)

Note:

1.

Please contact a Renesas Electronics sales office to use the optional feature.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 3 of 113

R32C/117A Group 1. Overview

Table 1.3

R32C/117A Group Performance for the 144-pin Package (1/2)

CPU

Unit

Memory

Voltage

Detector

Function

Central processing unit

Low voltage detector

Performance

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit $ 64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit $ 64-bit

• IEEE-754 floating point standard: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode, microprocessor mode (optional

(1)

)

Flash memory: 512 Kbytes to 1 Mbyte

RAM: 96 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for memory size of each product group

Optional

(1)

Low voltage detection interrupt

Clock

External Bus

Expansion

Interrupts

Watchdog Timer

Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/re-oscillation detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

Bus and memory expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width selectable (8/16/32 bits)

Interrupt vectors: 261

External interrupt inputs: NMI, INT × 9, key input × 4

Interrupt priority levels: 7 levels

DMA DMAC

15 bits × 1 (selectable input frequency from prescaler output)

Automatic timer start function is available

4 channels

• Cycle-steal transfer mode

• Request sources: 61

• 2 transfer modes: Single transfer, repeat transfer

I/O Ports

DMAC II

Programmable

I/O ports

• Can be activated by any peripheral interrupt source

• 3 transfer functions: Immediate data transfer, calculation transfer, chained transfer

• 2 input-only ports

• 124 CMOS inputs/outputs

• 40 ports are 5 V tolerant

• A pull-up resistor is selectable for every 4 input ports (except 5 V tolerant inputs)

Note:

1.

Please contact a Renesas Electronics sales office to use the optional feature.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 4 of 113

R32C/117A Group 1. Overview

Table 1.4

Timer

Unit

Serial

Interface

A/D Converter

D/A Converter

CRC Calculator

X-Y Converter

Intelligent I/O

CAN Module

Flash Memory

R32C/117A Group Performance for the 144-pin Package (2/2)

Function

Timer A

Timer B

Three-phase motor control timer

UART0 to

UART10

Performance

16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (twophase encoder input) × 3

16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Multi-master I

2

C-bus Interface

Asynchronous/synchronous serial interface × 11 channels

• I

2

C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional

(1)

) (UART0 to UART6)

10-bit resolution × 34 channels

Sample and hold functionality integrated

Self test/Open-circuit detection assist

8-bit resolution × 2

CRC-CCITT (X

16

+ X

12

+ X

5

+ 1)

16 bits × 16 bits

Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 24

Serial interface: Variable-length synchronous serial I/O mode, IEBus mode (optional

(1)

)

1 channel

1 channel

CAN functionality compliant with ISO11898-1

32 mailboxes

Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Suspend/resume function available

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

64 MHz/VCC = 3.0 to 5.5 V Operating Frequency/Supply

Voltage

Operating Temperature

Current Consumption

Package

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

144-pin plastic molded LQFP (PLQP0144KA-A)

Note:

1.

Please contact a Renesas Electronics sales office to use the optional feature.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 5 of 113

R32C/117A Group 1. Overview

1.2

Product Information

Table 1.5 lists the product information and Figure 1.1 shows the details of the part number.

Table 1.5

R32C/117A Group Product List

Part Number

R5F6417JANFE

R5F6417JADFE

R5F6417JAPFE

R5F6417JANFD

R5F6417JADFD

R5F6417JAPFD

R5F6417KANFE

R5F6417KADFE

R5F6417KAPFE

R5F6417KANFD

R5F6417KADFD

R5F6417KAPFD

R5F6417LANFE

R5F6417LADFE

R5F6417LAPFE

R5F6417LANFD

R5F6417LADFD

R5F6417LAPFD

R5F6417MANFE

R5F6417MADFE

R5F6417MAPFE

R5F6417MANFD

R5F6417MADFD

R5F6417MAPFD

(D): Under development

(P): On planning phase

(D)

(P)

(D)

(D)

(D)

(D)

(P)

(D)

(P)

(D)

(D)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

(P)

Package Code

(1)

PLQP0176KB-A

PLQP0144KA-A

PLQP0176KB-A

PLQP0144KA-A

PLQP0176KB-A

PLQP0144KA-A

PLQP0176KB-A

PLQP0144KA-A

ROM Capacity

(2)

RAM Capacity

512 Kbytes

+ 8 Kbytes

640 Kbytes

+ 8 Kbytes

768 Kbytes

+ 8 Kbytes

1 Mbyte

+ 8 Kbytes

96 Kbytes

96 Kbytes

96 Kbytes

96 Kbytes

Notes:

1.

The old package codes are as follows:PLQP0144KA-A: 144P6Q-A, PLQP0176KB-A: 176P6Q-A

2.

Data flash memory provides an additional 8 Kbytes of ROM capacity.

As of July, 2010

Remarks

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

-20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 6 of 113

R32C/117A Group

Part Number

R5 F 64 17 M A P XXX FE

Package Code

FD : PLQP0144KA-A

FE : PLQP0176KB-A

ROM Number

Omitted in the flash memory version

Temperature Code

N : -20°C to 85°C

D : -40°C to 85°C

P : -40°C to 85°C

ROM/RAM Capacity

J : 512 KB/96 KB

K : 640 KB/96 KB

L : 768 KB/96 KB

M : 1 MB/96 KB

R32C/117A Group

R32C/100 Series

Memory Type

F : Flash memory version

Figure 1.1

Part Numbering

1. Overview

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 7 of 113

R32C/117A Group

1.3

Block Diagram

Figure 1.2 shows a block diagram of the R32C/117A Group.

8 8 8 8 8 8 8 8

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7

Peripheral functions

Timer:

Timer A 16 bits × 5 timers

Timer B 16 bits × 6 timers

Three-phase motor controller

Serial interface:

11

channels

Multi-master I

2

C-bus interface:

1 channel

Intelligent I/O

Time Measurement: 16

Wave generation: 24

Serial interface:

- Variable-length

synchronous serial I/O

- IEBus

CAN module:

1

channels

A/D converter:

10 bits × 1 circuit

Standard: 10 inputs

Maximum: 34 inputs

D/A converter:

8 bits × 2 channels

X-Y converter:

16 bits × 16 bits

CRC calculator (CCITT)

X

16

+ X

12

+ X

5

+ 1

R32C/100 Series CPU Core

R2R0

R3R1

R6R4

R7R5

A0

A1

A2

A3

FB

SB

SB

FLG

INTB

ISP

USP

PC

SVF

SVP

VCT

Clock generator:

4 circuits

- XIN-XOUT

- XCIN-XCOUT

- On-chip oscillator

- PLL frequency synthesizer

Watchdog timer:

15 bits

DMAC

DMAC II

Memory

ROM

RAM

Multiplier

Floating-point unit

Port P19 Port P18 Port P17 Port P16 Port P15 Port P14 P14_1 Port P13

8 8 8 8 8

(Note 1)

Note:

1. Ports P16 to P19 are available in the 176-pin package only.

5

Figure 1.2

R32C/117A Group Block Diagram

8

1. Overview

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 8 of 113

R32C/117A Group 1. Overview

1.4

Pin Assignments

Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.6 to Table 1.13 show the pin

characteristics.

(Note 1) (Note 2)

IIO0_0 / IIO1_0 / D8 / P1_0

AN0_7 / D7 / P0_7

AN0_6 / D6 / P0_6

AN0_5 / D5 / P0_5

AN0_4 / D4 / P0_4

P19_1

WR3 / BC3 / P11_4

P19_0

IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3

IIO1_2 / RXD8 / CS2 / P11_2

IIO1_1 / CLK8 / CS1 / P11_1

IIO1_0 / TXD8 / CS0 / P11_0

P18_7

P18_6

P18_5

P18_4

P18_3

P18_2

AN0_3 / D3 / P0_3

AN0_2 / D2 / P0_2

AN0_1 / D1 / P0_1

AN0_0 / D0 / P0_0

IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7

IIO0_6 / CLK6 / AN15_6 / P15_6

IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5

IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4

IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3

IIO0_2 / RXD7 / AN15_2 / P15_2

IIO0_1 / CLK7 / AN15_1 / P15_1

VSS

IIO0_0 / TXD7 / AN15_0 / P15_0

VCC

KI3 / AN_7 / P10_7

KI2 / AN_6 / P10_6

KI1 / AN_5 / P10_5

KI0 / AN_4 / P10_4

AN_3 / P10_3

AN_2 / P10_2

AN_1 / P10_1

AVSS

AN_0 / P10_0

VREF

AVCC

STXD4 / SCL4 / RXD4 / ADTRG / P9_7

(Note 3)

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

R32C/117A GROUP

PLQP0176KB-A

(176P6Q-A)

(Top view)

69

68

67

66

65

64

63

62

61

60

59

58

79

78

77

76

75

74

73

72

71

70

57

56

55

54

53

52

51

50

49

48

47

46

45

85

84

83

82

81

80

88

87

86

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

P4_5 / CS2 / A21 / CLK6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P19_2

P17_0

P17_1

P17_2

P17_3

P19_3

P12_5 / D21

P12_6 / D22

P12_7 / D23

P5_0 / WR0 / WR

P5_1 / WR1 / BC1

P5_2 / RD

P5_3 / CLKOUT / BCLK

P13_0 / D24 / OUTC2_4

P13_1 / D25 / OUTC2_5

VCC

P13_2 / D26 / OUTC2_6

VSS

P13_3 / D27 / OUTC2_3

(Note 2)

P5_4 / HLDA / CS1 / TXD7

P5_5 / HOLD / CLK7

P5_6 / ALE / CS2 / RXD7

P5_7 / RDY / CS3 / CTS7 / RTS7

P19_4

P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT

P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN

P13_6 / D30 / OUTC2_1 / ISCLK2

P13_7 / D31 / OUTC2_7

P19_5

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P6_1 / TB1IN / CLK0

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_3 / TXD0 / SDA0 / SRXD0

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_5 / CLK1

P11_7

P6_6 / RXD1 / SCL1 / STXD1

P14_7

P6_7 / TXD1 / SDA1 / SRXD1

P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

(Note 2)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3, P12_0 to P12_7, P16_0 to P16_7, and P17_0 to P17_3.

3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.

Figure 1.3

Pin Assignment for the 176-pin Package (top view)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 9 of 113

R32C/117A Group 1. Overview

Table 1.6

Pin Characteristics for the 176-pin Package (1/5)

26

27

28

29

22

23

24

25

30

31

32

33

34

18

19

20

21

14

15

16

17

10

11

12

13

8

9

6

7

3

4

5

1

2

Pin

No.

Control

Pin

Port

P9_6

P9_5

P9_4

P9_3

P9_2

P9_1

P9_0

P19_7

P14_6 INT8

P19_6

P14_5 INT7

P14_4 INT6

P14_3

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

TB4IN

TB3IN

TB2IN

TB1IN

TB0IN

TXD4/SDA4/SRXD4

CLK4

CTS4/RTS4/SS4

CTS3/RTS3/SS3

TXD3/SDA3/SRXD3

RXD3/SCL3/STXD3

CLK3

OUTC2_0/ISTXD2/

IEOUT

ISRXD2/IEIN

VDC0

P14_1

VDC1

NSD

CNVSS

XCIN P8_7

XCOUT P8_6

RESET

XOUT

VSS

XIN

VCC

P8_5

NMI

P8_4

INT2

P8_3

INT1

P8_2

INT0

P8_1

P8_0

P18_1

P18_0

P7_7

TA4IN/U

CAN0IN/CAN0WU

CAN0OUT

CTS5/RTS5/SS5

TA4OUT/U RXD5/SCL5/STXD5

TA3IN CLK5/CAN0IN/

CAN0WU

IIO1_5/UD0B/UD1B

UD0A/UD1A

IIO1_4/UD0B/UD1B

35

36

P7_6

P7_5

TA3OUT TXD5/SDA5/SRXD5/

CTS8/RTS8/CAN0OUT

IIO1_3/UD0A/UD1A

TA2IN/W RXD8 IIO1_2

Analog

Pin

Bus Control

Pin

ANEX1

ANEX0

DA1

DA0

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 10 of 113

R32C/117A Group 1. Overview

65

66

67

68

61

62

63

64

69

70

71

72

57

58

59

53

54

55

56

49

50

51

52

46

47

48

Table 1.7

39

40

41

42

37

38

Pin

No.

43

44

45

Control

Pin

Pin Characteristics for the 176-pin Package (2/5)

Port

P7_4

P17_7

P17_6

P17_5

P17_4

P7_3

P7_2

P7_1

P7_0

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

TA2OUT/W CLK8 IIO1_1

TA1IN/V

CTS2/RTS2/SS2/TXD8 IIO1_0

TA1OUT/V CLK2

TB5IN/

TA0IN

RXD2/SCL2/STXD2/

MSCL

TA0OUT TXD2/SDA2/SRXD2/

MSDA

TXD1/SDA1/SRXD1

IIO1_7/OUTC2_2/

ISRXD2/IEIN

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

60

P6_2

P6_1

P6_0

P19_5

P13_7

P13_6

P13_5

P6_7

P14_7

P6_6

P11_7

P6_5

P6_4

P6_3

P13_4

TB2IN

TB1IN

TB0IN

RXD1/SCL1/STXD1

CLK1

CTS1/RTS1/SS1

TXD0/SDA0/SRXD0

RXD0/SCL0/STXD0

CLK0

CTS0/RTS0/SS0

OUTC2_1/ISCLK2

OUTC2_7

OUTC2_1/ISCLK2

OUTC2_2/ISRXD2/

IEIN

OUTC2_0/ISTXD2/

IEOUT

VSS

VCC

P19_4

P5_7

P5_6

P5_5

P5_4

P13_3

P13_2

P13_1

P13_0

P5_3

CTS7/RTS7

RXD7

CLK7

TXD7

OUTC2_3

OUTC2_6

OUTC2_5

OUTC2_4

73

74

P5_2

P5_1

Analog

Pin

Bus Control

Pin

D31

D30

D29

D28

RDY/CS3

ALE/CS2

HOLD

HLDA/CS1

D27

D26

D25

D24

CLKOUT/

BCLK

RD

WR1/BC1

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 11 of 113

R32C/117A Group 1. Overview

102

103

104

105

98

99

100

101

94

95

96

97

90

91

92

93

110

111

112

113

114

106

107

108

109

Table 1.8

85

86

87

88

89

81

82

83

84

77

78

79

80

75

76

Pin

No.

Control

Pin

Pin Characteristics for the 176-pin Package (3/5)

Port

P17_0

P19_2

P4_7

P4_6

P4_5

P4_4

P4_3

P5_0

P12_7

P12_6

P12_5

P19_3

P17_3

P17_2

P17_1

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

TXD6/SDA6/SRXD6

RXD6/SCL6/STXD6

CLK6

CTS6/RTS6/SS6

TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/

IEOUT

P16_4

P3_7

P3_6

P3_5

P3_4

P16_3

P16_2

P16_1

P11_6

P4_2

P11_5

P4_1

P4_0

P16_7

P16_6

P16_5

P16_0

P3_3

P3_2

P3_1

P12_4

P12_3

P12_2

P12_1

P12_0

TA4IN/U

TA4OUT/U

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA3OUT

RXD3/SCL3/STXD3

CLK3

CTS3/RTS3/SS3

TXD10

RXD10

CLK10

CTS10/RTS10

TXD9

RXD9

CLK9

CTS9/RTS9

CTS6/RTS6/SS6

RXD6/SCL6/STXD6

CLK6

TXD6/SDA6/SRXD6

ISRXD2/IEIN

UD0B/UD1B

Analog

Pin

Bus Control

Pin

WR0/WR

D23

D22

D21

CS0/A23

CS1/A22

CS2/A21

CS3/A20

A19

A18

A17

A16

A15(/D15)

A14(/D14)

A13(/D13)

A12(/D12)

A11(/D11)

A10(/D10)

A9(/D9)

D20

D19

D18

D17

D16

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 12 of 113

R32C/117A Group 1. Overview

P11_1

P11_0

P18_7

P18_6

P18_5

P18_4

P18_3

P18_2

P0_3

P0_2

P0_1

P0_0

P15_7

P0_6

P0_5

P0_4

P19_1

P11_4

P19_0

P11_3

P11_2

P1_7

INT5

P1_6

INT4

P1_5

INT3

P1_4

P1_3

P1_2

P1_1

P1_0

P0_7

149

150

151

152

153

154

155

145

146

147

148

141

142

143

144

137

138

139

140

133

134

135

136

126

127

128

129

130

131

132

Table 1.9

Pin Characteristics for the 176-pin Package (4/5)

121

122

123

124

Pin

No.

Control

Pin

115 VCC

116

Port

P3_0

117 VSS

118

119

120

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

TA0OUT

TXD10

RXD10

CLK10

CTS10/RTS10

TXD9

RXD9

CLK9

UD0A/UD1A

125 P2_0

CTS9/RTS9

IIO0_7/IIO1_7

IIO0_6/IIO1_6

IIO0_5/IIO1_5

IIO0_4/IIO1_4

IIO0_3/IIO1_3

IIO0_2/IIO1_2

IIO0_1/IIO1_1

IIO0_0/IIO1_0

Analog

Pin

Bus Control

Pin

A8(/D8)

AN2_7 A7(/D7)

AN2_6 A6(/D6)

AN2_5 A5(/D5)

AN2_4 A4(/D4)

AN2_3 A3(/D3)

AN2_2 A2(/D2)

AN2_1 A1(/D1)/

BC2(/D1)

AN2_0 A0(/D0)/

BC0(/D0)

D15

D14

D13

D12

D11

D10

D9

D8

AN0_7 D7

AN0_6 D6

AN0_5 D5

AN0_4 D4

CTS8/RTS8

RXD8

CLK8

TXD8

CTS6/RTS6/SS6

IIO1_3

IIO1_2

IIO1_1

IIO1_0

IIO0_7

BC3/WR3

AN0_3 D3

AN0_2 D2

AN0_1 D1

AN0_0 D0

AN15_7

CS3/WR2

CS2

CS1

CS0

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 13 of 113

R32C/117A Group 1. Overview

Table 1.10

Pin Characteristics for the 176-pin Package (5/5)

Pin

No.

156

157

158

159

160

161

Control

Pin

166

167

168

169

162 VSS

163

164 VCC

165

Port

P15_6

P15_5

P15_4

P15_3

P15_2

P15_1

P15_0

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

P10_2

P10_1

170

171

172 AVSS

173

174 VREF

175 AVCC

176

P10_0

P9_7

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

CLK6

RXD6/SCL6/STXD6

TXD6/SDA6/SRXD6

CTS7/RTS7

RXD7

CLK7

IIO0_6

IIO0_5

IIO0_4

IIO0_3

IIO0_2

IIO0_1

TXD7

RXD4/SCL4/STXD4

IIO0_0

AN_7

AN_6

AN_5

AN_4

AN_3

AN_2

AN_1

Analog

Pin

Bus Control

Pin

AN15_6

AN15_5

AN15_4

AN15_3

AN15_2

AN15_1

AN15_0

AN_0

ADTRG

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 14 of 113

R32C/117A Group

(Note 1) (Note 2)

1. Overview

IIO0_0 / IIO1_0 / D8 / P1_0

AN0_7 / D7 / P0_7

AN0_6 / D6 / P0_6

AN0_5 / D5 / P0_5

AN0_4 / D4 / P0_4

WR3 / BC3 / P11_4

IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3

IIO1_2 / RXD8 / CS2 / P11_2

IIO1_1 / CLK8 / CS1 / P11_1

IIO1_0 / TXD8 / CS0 / P11_0

AN0_3 / D3 / P0_3

AN0_2 / D2 / P0_2

AN0_1 / D1 / P0_1

AN0_0 / D0 / P0_0

IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7

IIO0_6 / CLK6 / AN15_6 / P15_6

IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5

IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4

IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3

IIO0_2 / RXD7 / AN15_2 / P15_2

IIO0_1 / CLK7 / AN15_1 / P15_1

VSS

IIO0_0 / TXD7 / AN15_0 / P15_0

VCC

KI3 / AN_7 / P10_7

KI2 / AN_6 / P10_6

KI1 / AN_5 / P10_5

KI0 / AN_4 / P10_4

AN_3 / P10_3

AN_2 / P10_2

AN_1 / P10_1

AVSS

AN_0 / P10_0

VREF

AVCC

STXD4 / SCL4 / RXD4 / ADTRG / P9_7

(Note 3)

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

R32C/117A GROUP

PLQP0144KA-A

(144P6Q-A)

(Top view)

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

69

68

67

66

65

64

63

62

61

60

59

58

72

71

70

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

P4_5 / CS2 / A21 / CLK6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P12_5 / D21

P12_6 / D22

P12_7 / D23

P5_0 / WR0 / WR

P5_1 / WR1 / BC1

P5_2 / RD

P5_3 / CLKOUT / BCLK

P13_0 / D24 / OUTC2_4

P13_1 / D25 / OUTC2_5

VCC

P13_2 / D26 / OUTC2_6

VSS

P13_3 / D27 / OUTC2_3

P5_4 / HLDA / CS1 / TXD7

P5_5 / HOLD / CLK7

(Note 2)

P5_6 / ALE / CS2 / RXD7

P5_7 / RDY / CS3 / CTS7 / RTS7

P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT

P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN

P13_6 / D30 / OUTC2_1 / ISCLK2

P13_7 / D31 / OUTC2_7

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P6_1 / TB1IN / CLK0

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_3 / TXD0 / SDA0 / SRXD0

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_5 / CLK1

P11_7

P6_6 / RXD1 / SCL1 / STXD1

P14_7

P6_7 / TXD1 / SDA1 / SRXD1

P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

(Note 2)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3, P12_0 to P12_7.

3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.

Figure 1.4

Pin Assignment for the 144-pin Package (top view)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 15 of 113

R32C/117A Group 1. Overview

31

32

33

34

35

36

Table 1.11

Pin Characteristics for the 144-pin Package (1/4)

18

19

20

21

14

15

16

17

10

11

12

13

8

9

6

7

26

27

28

29

30

22

23

24

25

3

4

5

1

2

Pin

No.

Control

Pin

Port

P9_6

P9_5

P9_4

P9_3

P9_2

P9_1

P9_0

P14_6 INT8

P14_5 INT7

P14_4 INT6

P14_3

Interrupt

Pin

Timer Pin UART/CAN Module Pin Intelligent I/O Pin

TB4IN

TB3IN

TB2IN

TB1IN

TB0IN

TXD4/SDA4/SRXD4

CLK4

CTS4/RTS4/SS4

CTS3/RTS3/SS3

TXD3/SDA3/SRXD3

RXD3/SCL3/STXD3

CLK3

OUTC2_0/ISTXD2/

IEOUT

ISRXD2/IEIN

VDC0

P14_1

VDC1

NSD

CNVSS

XCIN P8_7

XCOUT P8_6

RESET

XOUT

VSS

XIN

VCC

P8_5

NMI

P8_4

INT2

P8_3

INT1

P8_2

INT0

P8_1

P8_0

P7_7

TA4IN/U

TA3IN

CAN0IN/CAN0WU

CAN0OUT

CTS5/RTS5/SS5

TA4OUT/U RXD5/SCL5/STXD5

CLK5/CAN0IN/

CAN0WU

IIO1_5/UD0B/UD1B

UD0A/UD1A

IIO1_4/UD0B/UD1B

P7_6

P7_5

P7_4

P7_3

P7_2

P7_1

TA3OUT TXD5/SDA5/SRXD5/

CTS8/RTS8/CAN0OUT

IIO1_3/UD0A/UD1A

TA2IN/W RXD8 IIO1_2

TA2OUT/W CLK8

TA1IN/V

IIO1_1

CTS2/RTS2/SS2/TXD8 IIO1_0

TA1OUT/V CLK2

TB5IN/

TA0IN

RXD2/SCL2/STXD2/

MSCL

IIO1_7/OUTC2_2/

ISRXD2/IEIN

Analog

Pin

Bus Control

Pin

ANEX1

ANEX0

DA1

DA0

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 16 of 113

R32C/117A Group 1. Overview

67

68

69

70

63

64

65

66

71

72

73

74

56

57

58

59

52

53

54

55

60

61

62

42

43

44

45

38

39

40

41

46

47

48

49

50

Table 1.12

Pin Characteristics for the 144-pin Package (2/4)

Pin

No.

37

Control

Pin

Port

P7_0

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

TA0OUT TXD2/SDA2/SRXD2/

MSDA

TXD1/SDA1/SRXD1

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

51

P6_7

P14_7

P6_6

P11_7

P6_5

P6_4

P6_3

P6_2

P6_1

P6_0

P13_7

P13_6

P13_5

P13_4

TB2IN

TB1IN

TB0IN

RXD1/SCL1/STXD1

CLK1

CTS1/RTS1/SS1

TXD0/SDA0/SRXD0

RXD0/SCL0/STXD0

CLK0

CTS0/RTS0/SS0

OUTC2_1/ISCLK2

OUTC2_7

OUTC2_1/ISCLK2

OUTC2_2/ISRXD2/

IEIN

OUTC2_0/ISTXD2/

IEOUT

P5_7

P5_6

P5_5

P5_4

P13_3

CTS7/RTS7

RXD7

CLK7

TXD7

OUTC2_3

VSS

VCC

P13_2

P13_1

P13_0

P5_3

OUTC2_6

OUTC2_5

OUTC2_4

P5_2

P5_1

P5_0

P12_7

P12_6

P12_5

P4_7

P4_6

P4_5

P4_4

P4_3

P11_6

TXD6/SDA6/SRXD6

RXD6/SCL6/STXD6

CLK6

CTS6/RTS6/SS6

TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/

IEOUT

Analog

Pin

Bus Control

Pin

D26

D25

D24

CLKOUT/

BCLK

RD

WR1/BC1

WR0/WR

D23

D22

D21

CS0/A23

CS1/A22

CS2/A21

CS3/A20

A19

D31

D30

D29

D28

RDY/CS3

ALE/CS2

HOLD

HLDA/CS1

D27

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 17 of 113

R32C/117A Group 1. Overview

102

103

104

105

106

107

108

109

110

111

Table 1.13

Pin Characteristics for the 144-pin Package (3/4)

93

94

95

96

89

90

91

92

97

98

99

100

85

86

87

88

81

82

83

84

77

78

79

80

75

76

Pin

No.

Control

Pin

VCC

VSS

Port

P3_0

P2_7

P2_6

P2_5

P2_4

P2_3

P2_2

P2_1

P3_3

P3_2

P3_1

P12_4

P12_3

P12_2

P12_1

P12_0

P4_2

P11_5

P4_1

P4_0

P3_7

P3_6

P3_5

P3_4

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

RXD3/SCL3/STXD3 ISRXD2/IEIN

TA4IN/U

TA4OUT/U

TA2IN/W

TA2OUT/W

TA1IN/V

TA1OUT/V

TA3OUT

TA0OUT

CLK3

CTS3/RTS3/SS3

CTS6/RTS6/SS6

RXD6/SCL6/STXD6

CLK6

TXD6/SDA6/SRXD6

TXD10

RXD10

CLK10

CTS10/RTS10

TXD9

RXD9

CLK9

UD0B/UD1B

UD0A/UD1A

101 P2_0

P1_7

INT5

P1_6

INT4

P1_5

INT3

P1_4

P1_3

P1_2

P1_1

P1_0

P0_7

P0_6

CTS9/RTS9

IIO0_7/IIO1_7

IIO0_6/IIO1_6

IIO0_5/IIO1_5

IIO0_4/IIO1_4

IIO0_3/IIO1_3

IIO0_2/IIO1_2

IIO0_1/IIO1_1

IIO0_0/IIO1_0

Analog

Pin

Bus Control

Pin

A18

A8(/D8)

AN2_7 A7(/D7)

AN2_6 A6(/D6)

AN2_5 A5(/D5)

AN2_4 A4(/D4)

AN2_3 A3(/D3)

AN2_2 A2(/D2)

AN2_1 A1(/D1)/

BC2(/D1)

AN2_0 A0(/D0)/

BC0(/D0)

D15

D14

D13

D12

D11

D10

D9

D8

AN0_7 D7

AN0_6 D6

A17

A16

A15(/D15)

A14(/D14)

A13(/D13)

A12(/D12)

A11(/D11)

A10(/D10)

A9(/D9)

D20

D19

D18

D17

D16

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 18 of 113

R32C/117A Group 1. Overview

Table 1.14

Pin Characteristics for the 144-pin Package (4/4)

Control

Pin

126

127

128

129

130 VSS

131

132 VCC

133

134

135

136

137

138

139

140 AVSS

141

142 VREF

143 AVCC

144

122

123

124

125

118

119

120

121

114

115

116

117

Pin

No.

112

113

Port

P0_2

P0_1

P0_0

P15_7

P15_6

P15_5

P15_4

P15_3

P15_2

P15_1

P0_5

P0_4

P11_4

P11_3

P11_2

P11_1

P11_0

P0_3

P15_0

P10_7 KI3

P10_6 KI2

P10_5 KI1

P10_4 KI0

P10_3

P10_2

P10_1

P10_0

P9_7

Interrupt

Pin

Timer Pin UART/CAN Module Pin

Intelligent I/O Pin

CTS8/RTS8

RXD8

CLK8

TXD8

CTS6/RTS6/SS6

CLK6

RXD6/SCL6/STXD6

TXD6/SDA6/SRXD6

CTS7/RTS7

RXD7

CLK7

TXD7

RXD4/SCL4/STXD4

IIO1_3

IIO1_2

IIO1_1

IIO1_0

IIO0_7

IIO0_6

IIO0_5

IIO0_4

IIO0_3

IIO0_2

IIO0_1

IIO0_0

Analog

Pin

Bus Control

Pin

AN0_5 D5

AN0_4 D4

BC3/WR3

CS3/WR2

CS2

CS1

CS0

AN0_3 D3

AN0_2 D2

AN0_1 D1

AN0_0 D0

AN15_7

AN15_6

AN15_5

AN15_4

AN15_3

AN15_2

AN15_1

AN15_0

AN_7

AN_6

AN_5

AN_4

AN_3

AN_2

AN_1

AN_0

ADTRG

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 19 of 113

R32C/117A Group 1. Overview

1.5

Pin Definitions and Functions

Table 1.15 to Table 1.19 show the pin definitions and functions.

Table 1.15

Pin Definitions and Functions (1/4)

Function

Power supply

Connecting pins for decoupling capacitor

Analog power supply

Reset input

CNVSS

Debug port

Main clock input

Main clock output XOUT

Sub clock input

Sub clock output

BCLK output

Clock output

Symbol

VCC, VSS

VDC0, VDC1

AVCC, AVSS

RESET

CNVSS

NSD

XIN

XCIN

XCOUT

BCLK

CLKOUT

I/O Description

I

I

I

I/O

I

I

O

Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V

A decoupling capacitor for internal voltage should be connected between VDC0 and VDC1

Power supply for the A/D converter. AVCC and AVSS should be connected to VCC and VSS, respectively

The MCU is reset when this pin is driven low

This pin should be connected to VSS via a resistor

This pin is to communicate with a debugger. It should be connected to VCC via a resistor of 1 to 4.7 k

Ω

Input/output for the main clock oscillator. A crystal, or a ceramic resonator should be connected between pins XIN and XOUT. An external clock should be input at the XIN while leaving the XOUT open

I

O

Input/output for the sub clock oscillator. A crystal oscillator should be connected between pins XCIN and XCOUT. An external clock should be input at the XCIN while leaving the

XCOUT open

O BCLK output

O

Output of the clock with the same frequency as low speed clocks, f8, or f32

Input for external interrupts

I

External interrupt input

INT0 to INT8

NMI input P8_5/NMI

Key input interrupt KI0 to KI3

Bus control pins D0 to D7

D8 to D15

D16 to D31

A0 to A23

A0/D0 to A7/D7

A8/D8 to

A15/D15

I

I

I/O

I/O

Input for NMI

Input for the key input interrupt

Input/output of data (D0 to D7) while accessing an external memory space with a separate bus

Input/output of data (D8 to D15) while accessing an external memory space with 16-bit or 32-bit separate bus

I/O

Input/output of data (D16 to D31) while accessing an external memory space with 32-bit separate bus

O Output of address bits A0 to A23

I/O

I/O

Output of address bits (A0 to A7) and input/output of data

(D0 to D7) by time-division while accessing an external memory space with multiplexed bus

Output of address bits (A8 to A15) and input/output of data

(D8 to D15) by time-division while accessing an external memory space with 16-bit or 32-bit multiplexed bus

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R32C/117A Group 1. Overview

Table 1.16

Pin Definitions and Functions (2/4)

Function Symbol

Bus control pins

BC0/D0, BC2

/

D1

CS0 to CS3

WR0/WR1/WR2/

WR3,

WR/BC0/BC1/

BC2/BC3,

RD

I/O

I/O

O Chip select output

Description

Output of byte control (BC0 and BC2) and input/output of data (D0 and D1) by time-division while accessing an external memory space with multiplexed bus

Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program.

Data is read when RD is low.

O

• When WR0, WR1, WR2, WR3, and RD are selected, data is written to the following address:

4n+0, when WR0 is low

4n+1, when WR1 is low

4n+2, when WR2 is low

4n+3, when WR3 is low on 32-bit external data bus or an even address, when WR0 is low an odd address, when WR1 is low on 16-bit external data bus

ALE

HOLD

HLDA

RDY

• When WR, BC0, BC1, BC2, BC3, and RD are selected, data is written, when WR is low and the following address is accessed:

4n+0, when BC0 is low

4n+1, when BC1 is low

4n+2, when BC2 is low

4n+3, when BC3 is low on 32-bit external data bus or an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus

O Latch enable signal in multiplexed bus format

I The MCU is in a hold state while this pin is held low

O This pin is driven low while the MCU is held in a hold state

I

Bus cycle is extended by the CPU if this pin is low on the falling edge of the BCLK

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Page 21 of 113

R32C/117A Group 1. Overview

Table 1.17

Pin Definitions and Functions (3/4)

Function

I/O port

(1)

Input port

Symbol

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_0 to P4_7,

P5_0 to P5_7,

P6_0 to P6_7,

P7_0 to P7_7,

P8_0 to P8_4,

P8_6, P8_7,

P9_0 to P9_7,

P10_0 to P10_7,

P11_0 to P11_7,

P12_0 to P12_7,

P13_0 to P13_7,

P14_3 to P14_7,

P15_0 to P15_7,

P16_0 to P16_7,

P17_0 to P17_7,

P18_0 to P18_7,

P19_0 to P19_7

P14_1

I/O

I/O

Description

I/O ports in CMOS. Each port can be programmed to input or output under the control of the direction register.

Some ports are 5 V tolerant inputs.

Pull-up resistors and N-channel open drain setting can be

enabled on some ports. Refer to Table 1.19 “Pin

Specifications” for details

Timer A

I

I/O

Input port in CMOS

Pull-up resistor is selectable.

Refer to Table 1.19 “Pin Specifications” for details

Timers A0 to A4 input/output

Timer B

Three-phase motor control timer output

Serial interface

TA0OUT to

TA4OUT

TA0IN to TA4IN

TB0IN to TB5IN

U, U, V, V, W, W

I

I

O

Timers A0 to A4 input

Timers B0 to B5 input

Three-phase motor control timer output

I

2

C bus

(simplified)

Serial interface special functions

CTS0 to CTS10

RTS0 to RTS10

CLK0 to CLK10

RXD0 to RXD10

TXD0 to TXD10

SDA0 to SDA6

SCL0 to SCL6

STXD0 to

STXD6

SRXD0 to

SRXD6

SS0 to SS6

I Handshake input

O Handshake output

I/O Transmit/receive clock input/output

I Serial data input

O Serial data output

I/O Serial data input/output

I/O Transmit/receive clock input/output

Serial data output in slave mode

O

I

I

Serial data input in slave mode

Input to control serial interface special functions

Note:

1.

Ports P16 to P19 are available in the 176-pin package only.

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R32C/117A Group 1. Overview

Table 1.18

Pin Definitions and Functions (4/4)

Function

A/D converter

Symbol

AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to

AN15_7

ADTRG

I/O

I

Description

Analog input for the A/D converter

D/A converter

ANEX0

ANEX1

DA0, DA1

Reference voltage input

VREF

Intelligent I/O IIO0_0 to IIO0_7

IIO1_0 to IIO1_7

I

I/O

External trigger input for the A/D converter

Expanded analog input for the A/D converter and output in external op-amp connection mode

I Expanded analog input for the A/D converter

O Output for the D/A converter

I

I

I/O

I/O

Reference voltage input for the A/D converter and D/A converter

Input/output for the Intelligent I/O group 0. Either input capture or output compare is selectable

Input/output for the Intelligent I/O group 1. Either input capture or output compare is selectable

Input for the two-phase encoder

Multi-master I bus

CAN Module

2

C-

UD0A, UD0B,

UD1A, UD1B

OUTC2_0 to

OUTC2_7

ISCLK2

ISRXD2

ISTXD2

IEIN

IEOUT

MSDA

MSCL

CAN0IN

CAN0OUT

CAN0WU

O

Output for OC (output compare) of the Intelligent I/O group

2

I/O Clock input/output for the serial interface

I Receive data input for the serial interface

O Transmit data output for the serial interface

I Receive data input for the serial interface

O Transmit data output for the serial interface

I/O Serial data input/output

I/O Transmit/receive clock input/output

I Receive data input for the CAN communications

O Transmit data output for the CAN communications

I Input for the CAN wake-up interrupt

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Page 23 of 113

R32C/117A Group 1. Overview

Table 1.19

Pin Specifications

Pin names

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_3

P5_4 to P5_7

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_3

P8_4, P8_6, P8_7

P9_0 to P9_7

P10_0 to P10_7

P11_0 to P11_3

P11_4 to P11_7

P12_0 to P12_7

P13_0 to P13_7

P14_1, P14_3

P14_4 to P14_7

P15_0 to P15_7

P16_0 to P16_7

P17_0 to P17_3

P17_4 to P17_7

P18_0 to P18_7

P19_0 to P19_7

Package

176pin

144pin

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Selectable Functions

Pull-up resistor

(1)

N-channel open drain

(2)

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

5 V tolerant input

R

R

R

R

R

R

R

R

(3)

Notes:

1.

Pull-up resistors are selected in 4-pin units, but are only enabled for those pins set as input ports.

2.

N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.

3.

5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.

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R32C/117A Group 2. Central Processing Unit (CPU)

2.

Central Processing Unit (CPU)

The CPU contains registers as shown below. There are two register banks each consisting of registers

R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.

General purpose registers

R2R0

R3R1

R6R4

R7R5 b31

R2H

R3H

R6

R7 b23

R2L

R3L

A0

A1 b15

R0H

R1H

R4

R5 b7

R0L b0

R1L

A2

A3

SB

FB

USP

ISP

INTB

PC

FLG

Data registers

(1)

Address registers

(1)

Static base register

(1)

Frame base register

(1)

User stack pointer

Interrupt stack pointer

Interrupt vector table base register

Program counter

Flag register b31 b24 b23

RND b16 b15

IPL

DP b8 b7

U I O B S Z b0

D C

FO

FU

Blank fields represent reserved.

b31 b0

Fast interrupt registers

SVF

SVP

VCT

Save flag register

Save PC register

Vector register b31 b23 b0

DMAC-associated registers

(2)

DDA0

DDA0

DDR0

DDR0

Notes:

1. There are two banks of these registers.

2. There are four identical sets of DMAC-associated registers.

DMA mode register

DMA terminal count register

DMA terminal count reload register

DMA source address register

DMA source address reload register

DMA destination address register

DMA destination address reload register

Figure 2.1

CPU Registers

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Page 25 of 113

R32C/117A Group 2. Central Processing Unit (CPU)

2.1

General Purpose Registers

2.1.1

Data Registers (R2R0, R3R1, R6R4, and R7R5)

These 32-bit registers are primarily used for transfers and arithmetic/logic operations.

Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into

R2 and R0, R3R0 can be divided into R3 and R1, etc.

Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and

R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).

2.1.2

Address Registers (A0, A1, A2, and A3)

These 32-bit registers have functions similar to data registers. They are also used for address register indirect addressing and address register relative addressing.

2.1.3

Static Base Register (SB)

This 32-bit register is used for SB relative addressing.

2.1.4

Frame Base Register (FB)

This 32-bit register is used for FB relative addressing.

2.1.5

Program Counter (PC)

This 32-bit counter indicates the address of the instruction to be executed next.

2.1.6

Interrupt Vector Table Base Register (INTB)

This 32-bit register indicates the start address of a relocatable vector table.

2.1.7

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack pointer (ISP).

Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt

stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for

details.

To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer

(USP) or the interrupt stack pointer (ISP) to a multiple of 4.

2.1.8

Flag Register (FLG)

This 32-bit register indicates the CPU status.

2.1.8.1

Carry Flag (C flag)

This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic logic unit (ALU).

2.1.8.2

Debug Flag (D flag)

This flag is only for debugging. Only set this bit to 0.

2.1.8.3

Zero Flag (Z flag)

This flag becomes 1 when the result of an operation is 0; otherwise it is 0.

2.1.8.4

Sign Flag (S flag)

This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.

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R32C/117A Group 2. Central Processing Unit (CPU)

2.1.8.5

Register Bank Select Flag (B flag)

This flag selects a register bank. It indicates 0 when the register bank 0 is selected, and 1 when the register bank 1 is selected.

2.1.8.6

Overflow Flag (O flag)

This flag becomes 1 if an overflow occurs in an operation; otherwise it is 0.

2.1.8.7

Interrupt Enable Flag (I flag)

This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.

2.1.8.8

Stack Pointer Select Flag (U flag)

To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set this flag to 1.

It becomes 0 when a hardware interrupts is accepted or when an INT instruction designated by a software interrupt number from 0 to 127 is executed.

2.1.8.9

Floating-point Underflow Flag (FU flag)

This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.10

Floating-point Overflow Flag (FO flag)

This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also becomes 1 when the operand has invalid numbers (subnormal numbers).

2.1.8.11

Processor Interrupt Priority Level (IPL)

The processor interrupt priority level (IPL), consisting of three bits, selects a processor interrupt priority level from level 0 to 7. An interrupt is acceptable when the interrupt request level is higher than the selected IPL.

When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.

2.1.8.12

Fixed-point Radix Point Designation Bit (DP bit)

This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result to take. It is used in the MULX instruction.

2.1.8.13

Floating-point Rounding Mode (RND)

The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.

2.1.8.14

Reserved

Only set this bit to 0. The read value is undefined.

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R32C/117A Group 2. Central Processing Unit (CPU)

2.2

Fast Interrupt Registers

The following three registers are provided to minimize the overhead of interrupt sequence.

2.2.1

Save Flag Register (SVF)

This 32-bit register is used to save the flag register when a fast interrupt is generated.

2.2.2

Save PC Register (SVP)

This 32-bit register is used to save the program counter when a fast interrupt is generated.

2.2.3

Vector Register (VCT)

This 32-bit register is used to indicate a jump address when a fast interrupt is generated.

2.3

DMAC-associated Registers

There are seven types of DMAC-associated registers.

2.3.1

DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)

These 32-bit registers are used to set DMA transfer mode, bit rate, etc.

2.3.2

DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)

These 24-bit registers are used to set DMA transfer counting.

2.3.3

DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)

These 24-bit registers are used to set the reloaded values for DMA terminal count registers.

2.3.4

DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)

These 32-bit registers are used to set DMA source addresses.

2.3.5

DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)

These 32-bit registers are used to set the reloaded value for DMA source address register.

2.3.6

DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)

These 32-bit registers are used to set DMA destination address.

2.3.7

DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and

DDR3)

These 32-bit registers are used to set reloaded values for DMA destination address registers.

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R32C/117A Group 3. Memory

3.

Memory

Figure 3.1 shows the memory map of the R32C/117A Group.

The R32C/117A Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.

The internal ROM is mapped to the end of the memory map with the ending address fixed at FFFFFFFFh.

Therefore, the 1-Mbyte internal ROM is mapped from FFF00000h to FFFFFFFFh.

The fixed interrupt vector table which contains each start address of interrupt handlers is mapped from

FFFFFFDCh to FFFFFFFFh.

The internal RAM is mapped to the beginning of the memory map with the starting address fixed at

00000400h. Therefore, the 96-Kbyte internal RAM is mapped from 00000400h to 000183FFh. Besides being used for data storage, the internal RAM functions as a stack(s) for subroutines and/or interrupt handlers.

Special Function Registers (SFRs), which are control registers for peripheral functions, are mapped from

00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved.

No access is allowed.

In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should not be accessed.

00000000h

00000400h

SFR1

Internal RAM

00018400h

Reserved

Internal ROM

Capacity YYYYYYYYh

512 Kbytes FFF80000h

640 Kbytes FFF60000h

768 Kbytes FFF40000h

1 Mbyte FFF00000h

00040000h

00050000h

00060000h

00062000h

SFR2

Reserved

Internal ROM

(Data space)

(1)

Reserved

00080000h

FFE00000h

External space

Reserved

(3)

(2)

YYYYYYYYh

FFFFFFFFh

Internal ROM

(4)

FFFFFFDCh

FFFFFFFFh

Undefined instruction

Overflow

BRK instruction

Reserved

Reserved

Watchdog timer

(5)

Reserved

NMI

Reset

Notes:

1. Additional two 4-Kbyte spaces (blocks A and B) for storing data are provided in the flash memory version.

2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h to FDFFFFFFh are inaccessible.

3. This space is reserved in memory expansion mode. It can be external space in microprocessor mode.

4. This space can be used in single-chip mode or memory expansion mode. It can be external space in

microprocessor mode.

5. The watchdog timer interrupt shares the vector table with the oscillator stop detection interrupt and low voltage detection interrupt.

Figure 3.1

Memory Map

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Page 29 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

4.

Special Function Registers (SFRs)

SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List

(1) to Table 4.41 SFR List (41) list the SFR details.

Table 4.1

SFR List (1)

Address

000000h

000001h

000002h

Register

000003h

000004h Clock Control Register

000005h

000006h Flash Memory Control Register

000007h Protect Release Register

000008h Flash Memory Rewrite Bus Control Register

000009h

00000Ah

00000Bh

00000Ch

00000Dh

00000Eh

00000Fh

000010h External Bus Control Register 3

000011h

000012h Chip Selects 2 and 3 Boundary Setting Register

000013h

000014h External Bus Control Register 2

000015h

000016h Chip Selects 1 and 2 Boundary Setting Register

000017h

000018h External Bus Control Register 1

000019h

00001Ah Chip selects 0 and 1 Boundary Setting Register

00001Bh

00001Ch External Bus Control Register 0

00001Dh

00001Eh Peripheral Bus Control Register

00001Fh

000020h to

00005Fh

X: Undefined

Blanks are reserved. No access is allowed.

CCR

FMCR

PRR

FEBC

EBC1

CB01

EBC0

PBC

EBC3

CB23

EBC2

CB12

Symbol Reset Value

0001 1000b

0000 0001b

00h

0000h

0000h

00h

0000h

00h

0000h

00h

0000h

0504h

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Page 30 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.2

SFR List (2)

Address

000060h

Register

000061h Timer B5 Interrupt Control Register

000062h UART5 Transmit/NACK Interrupt Control Register

000063h UART2 Receive/ACK Interrupt Control Register/I 2

C Bus Line

Interrupt Control Register

000064h UART6 Transmit/NACK Interrupt Control Register

000065h UART3 Receive/ACK Interrupt Control Register

000066h UART5/6 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

000067h UART4 Receive/ACK Interrupt Control Register

000068h DMA0 Transfer Complete Interrupt Control Register

000069h UART0/3 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

00006Ah DMA2 Transfer Complete Interrupt Control Register

00006Bh A/D Converter 0 Convert Completion Interrupt Control Register

00006Ch Timer A0 Interrupt Control Register

00006Dh Intelligent I/O Interrupt Control Register 0

00006Eh Timer A2 Interrupt Control Register

00006Fh Intelligent I/O Interrupt Control Register 2

000070h Timer A4 Interrupt Control Register

000071h Intelligent I/O Interrupt Control Register 4

000072h UART0 Receive/ACK Interrupt Control Register

000073h Intelligent I/O Interrupt Control Register 6

000074h UART1 Receive/ACK Interrupt Control Register

000075h Intelligent I/O Interrupt Control Register 8

000076h Timer B1 Interrupt Control Register

000077h Intelligent I/O Interrupt Control Register 10

000078h Timer B3 Interrupt Control Register

000079h

00007Ah INT5 Interrupt Control Register

00007Bh CAN0 Wake-up Interrupt Control Register

00007Ch INT3 Interrupt Control Register

00007Dh

00007Eh INT1 Interrupt Control Register

00007Fh

000080h

000081h UART2 Transmit/NACK Interrupt Control Register/I 2

C-Bus

Interrupt Control Register

000082h UART5 Receive/ACK Interrupt Control Register

000083h UART3 Transmit/NACK Interrupt Control Register

000084h UART6 Receive/ACK Interrupt Control Register

000085h UART4 Transmit/NACK Interrupt Control Register

000086h

000087h UART2 Bus Collision, Start Condition/Stop Condition Detection

Interrupt Control Register

X: Undefined

Blanks are reserved. No access is allowed.

Symbol

TB5IC

S5TIC

S2RIC/I2CLIC

Reset Value

XXXX X000b

XXXX X000b

XXXX X000b

S6TIC

S3RIC

XXXX X000b

XXXX X000b

BCN5IC/BCN6IC XXXX X000b

S4RIC

DM0IC

XXXX X000b

XXXX X000b

BCN0IC/BCN3IC XXXX X000b

DM2IC

AD0IC

TA0IC

IIO0IC

TA2IC

IIO2IC

TA4IC

IIO4IC

S0RIC

IIO6IC

S1RIC

IIO8IC

TB1IC

IIO10IC

TB3IC

INT5IC

C0WIC

INT3IC

INT1IC

S2TIC/I2CIC

S5RIC

S3TIC

S6RIC

S4TIC

BCN2IC

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XX00 X000b

XXXX X000b

XX00 X000b

XX00 X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

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Page 31 of 113

R32C/117A Group

Table 4.3

SFR List (3)

Address Register

000088h DMA1 Transfer Complete Interrupt Control Register

000089h UART1/4 Bus Collision, Start Condition/Stop Condition

Detection Interrupt Control Register

00008Ah DMA3 Transfer Complete Interrupt Control Register

00008Bh Key Input Interrupt Control Register

00008Ch Timer A1 Interrupt Control Register

00008Dh Intelligent I/O Interrupt Control Register 1

00008Eh Timer A3 Interrupt Control Register

00008Fh Intelligent I/O Interrupt Control Register 3

000090h UART0 Transmit/NACK Interrupt Control Register

000091h Intelligent I/O Interrupt Control Register 5

000092h UART1 Transmit/NACK Interrupt Control Register

000093h Intelligent I/O Interrupt Control Register 7

000094h Timer B0 Interrupt Control Register

000095h Intelligent I/O Interrupt Control Register 9

000096h Timer B2 Interrupt Control Register

000097h Intelligent I/O Interrupt Control Register 11

000098h Timer B4 Interrupt Control Register

000099h

00009Ah INT4 Interrupt Control Register

00009Bh

00009Ch INT2 Interrupt Control Register

00009Dh

00009Eh INT0 Interrupt Control Register

00009Fh

0000A0h Intelligent I/O Interrupt Request Register 0

0000A1h Intelligent I/O Interrupt Request Register 1

0000A2h Intelligent I/O Interrupt Request Register 2

0000A3h Intelligent I/O Interrupt Request Register 3

0000A4h Intelligent I/O Interrupt Request Register 4

0000A5h Intelligent I/O Interrupt Request Register 5

0000A6h Intelligent I/O Interrupt Request Register 6

0000A7h Intelligent I/O Interrupt Request Register 7

0000A8h Intelligent I/O Interrupt Request Register 8

0000A9h Intelligent I/O Interrupt Request Register 9

0000AAh Intelligent I/O Interrupt Request Register 10

0000ABh Intelligent I/O Interrupt Request Register 11

0000ACh

0000ADh

0000AEh

0000AFh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

INT0IC

IIO0IR

IIO1IR

IIO2IR

IIO3IR

IIO4IR

IIO5IR

IIO6IR

IIO7IR

IIO8IR

IIO9IR

IIO10IR

IIO11IR

DM1IC

Symbol Reset Value

XXXX X000b

BCN1IC/BCN4IC XXXX X000b

DM3IC

KUPIC

TA1IC

IIO1IC

TA3IC

IIO3IC

S0TIC

IIO5IC

S1TIC

IIO7IC

TB0IC

IIO9IC

TB2IC

IIO11IC

TB4IC

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

INT4IC

INT2IC

XX00 X000b

XX00 X000b

XX00 X000b

0000 0XX1b

0000 0XX1b

0000 0X01b

0000 XXX1b

000X 0XX1b

000X 0XX1b

000X 0XX1b

X00X 0XX1b

XX0X 0XX1b

0X00 0XX1b

0X00 0XX1b

0X00 0XX1b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 32 of 113

R32C/117A Group

Table 4.4

SFR List (4)

Address Register

0000B0h Intelligent I/O Interrupt Enable Register 0

0000B1h Intelligent I/O Interrupt Enable Register 1

0000B2h Intelligent I/O Interrupt Enable Register 2

0000B3h Intelligent I/O Interrupt Enable Register 3

0000B4h Intelligent I/O Interrupt Enable Register 4

0000B5h Intelligent I/O Interrupt Enable Register 5

0000B6h Intelligent I/O Interrupt Enable Register 6

0000B7h Intelligent I/O Interrupt Enable Register 7

0000B8h Intelligent I/O Interrupt Enable Register 8

0000B9h Intelligent I/O Interrupt Enable Register 9

0000BAh Intelligent I/O Interrupt Enable Register 10

0000BBh Intelligent I/O Interrupt Enable Register 11

0000BCh

0000BDh

0000BEh

0000BFh

0000C0h

0000C1h CAN0 Transmit Interrupt Control Register

0000C2h

0000C3h CAN0 Error Interrupt Control Register

0000C4h

0000C5h

0000C6h

0000C7h

0000C8h

0000C9h

0000CAh

0000CBh

0000CCh

0000CDh

0000CEh

0000CFh

0000D0h CAN0 Transmit FIFO Interrupt Control Register

0000D1h

0000D2h

0000D3h

0000D4h

0000D5h

0000D6h

0000D7h

0000D8h

0000D9h UART9 Transmit Interrupt Control Register

0000DAh

0000DBh UART10 Transmit Interrupt Control Register

0000DCh

0000DDh UART7 Transmit Interrupt Control Register

0000DEh INT7 Interrupt Control Register

0000DFh UART8 Transmit Interrupt Control Register

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

IIO0IE

Symbol

IIO1IE

IIO2IE

IIO3IE

IIO4IE

IIO5IE

IIO6IE

IIO7IE

IIO8IE

IIO9IE

IIO10IE

IIO11IE

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

Reset Value

C0TIC

C0EIC

XXXX X000b

XXXX X000b

C0FTIC XXXX X000b

S9TIC

S10TIC

S7TIC

INT7IC

S8TIC

XXXX X000b

XXXX X000b

XXXX X000b

XX00 X000b

XXXX X000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 33 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.5

SFR List (5)

Address

0000E0h

Register

0000E1h CAN0 Receive Interrupt Control Register

0000E2h

0000E3h

0000E4h

0000E5h

0000E6h

0000E7h

0000E8h

0000E9h

0000EAh

0000EBh

0000ECh

0000EDh

0000EEh

C0RIC

Symbol

0000EFh

0000F0h CAN0 Receive FIFO Interrupt Control Register

0000F1h

0000F2h

0000F3h

0000F4h

0000F5h

0000F6h

C0FRIC

0000F7h

0000F8h

0000F9h UART9 Receive Interrupt Control Register

0000FAh

0000FBh UART10 Receive Interrupt Control Register

0000FCh INT8 Interrupt Control Register

0000FDh UART7 Receive Interrupt Control Register

0000FEh INT6 Interrupt Control Register

S9RIC

S10RIC

INT8IC

S7RIC

INT6IC

0000FFh UART8 Receive Interrupt Control Register S8RIC

000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0

000101h

000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1

000103h

000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2

000105h

000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3

000107h

X: Undefined

Blanks are reserved. No access is allowed.

Reset Value

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XX00 X000b

XXXX X000b

XX00 X000b

XXXX X000b

XXXXh

XXXXh

XXXXh

XXXXh

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 34 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.6

SFR List (6)

Address Register Symbol

000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4

000109h

00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5

00010Bh

00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6

00010Dh

00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7

00010Fh

000110h Group 1 Waveform Generation Control Register 0

000111h Group 1 Waveform Generation Control Register 1

000112h Group 1 Waveform Generation Control Register 2

000113h Group 1 Waveform Generation Control Register 3

000114h Group 1 Waveform Generation Control Register 4

000115h Group 1 Waveform Generation Control Register 5

000116h Group 1 Waveform Generation Control Register 6

G1POCR0

G1POCR1

G1POCR2

G1POCR3

G1POCR4

G1POCR5

G1POCR6

G1POCR7 000117h Group 1 Waveform Generation Control Register 7

000118h Group 1 Time Measurement Control Register 0

000119h Group 1 Time Measurement Control Register 1

00011Ah Group 1 Time Measurement Control Register 2

00011Bh Group 1 Time Measurement Control Register 3

00011Ch Group 1 Time Measurement Control Register 4

00011Dh Group 1 Time Measurement Control Register 5

00011Eh Group 1 Time Measurement Control Register 6

G1TMCR0

G1TMCR1

G1TMCR2

G1TMCR3

G1TMCR4

G1TMCR5

G1TMCR6

G1TMCR7

G1BT

00011Fh Group 1 Time Measurement Control Register 7

000120h Group 1 Base Timer Register

000121h

000122h Group 1 Base Timer Control Register 0

000123h Group 1 Base Timer Control Register 1

000124h Group 1 Time Measurement Prescaler Register 6

000125h Group 1 Time Measurement Prescaler Register 7

000126h Group 1 Function Enable Register

G1BCR0

G1BCR1

G1TPR6

G1TPR7

G1FE

G1FS 000127h Group 1 Function Select Register

000128h

000129h

00012Ah

00012Bh

00012Ch

00012Dh

00012Eh

00012Fh

000130h to

00013Fh

X: Undefined

Blanks are reserved. No access is allowed.

Reset Value

XXXXh

XXXXh

XXXXh

XXXXh

0000 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

00h

00h

00h

00h

00h

00h

00h

00h

XXXXh

00h

0000 0000b

00h

00h

00h

00h

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 35 of 113

R32C/117A Group

Table 4.7

SFR List (7)

Address Register

000140h Group 2 Waveform Generation Register 0

000141h

000142h Group 2 Waveform Generation Register 1

000143h

000144h Group 2 Waveform Generation Register 2

000145h

000146h Group 2 Waveform Generation Register 3

000147h

000148h Group 2 Waveform Generation Register 4

000149h

00014Ah Group 2 Waveform Generation Register 5

00014Bh

00014Ch Group 2 Waveform Generation Register 6

00014Dh

00014Eh Group 2 Waveform Generation Register 7

00014Fh

000150h Group 2 Waveform Generation Control Register 0

000151h Group 2 Waveform Generation Control Register 1

000152h Group 2 Waveform Generation Control Register 2

000153h Group 2 Waveform Generation Control Register 3

000154h Group 2 Waveform Generation Control Register 4

000155h Group 2 Waveform Generation Control Register 5

000156h Group 2 Waveform Generation Control Register 6

000157h Group 2 Waveform Generation Control Register 7

000158h

000159h

00015Ah

00015Bh

00015Ch

00015Dh

00015Eh

00015Fh

000160h Group 2 Base Timer Register

000161h

000162h Group 2 Base Timer Control Register 0

000163h Group 2 Base Timer Control Register 1

000164h Base Timer Start Register

000165h

000166h Group 2 Function Enable Register

000167h Group 2 RTP Output Buffer Register

000168h

000169h

00016Ah Group 2 Serial Interface Mode Register

00016Bh Group 2 Serial Interface Control Register

00016Ch Group 2 SI/O Transmit Buffer Register

00016Dh

00016Eh Group 2 SI/O Receive Buffer Register

00016Fh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol

G2PO0

G2PO1

G2PO2

G2PO3

G2PO4

G2PO5

G2PO6

G2PO7

G2POCR0

G2POCR1

G2POCR2

G2POCR3

G2POCR4

G2POCR5

G2POCR6

G2POCR7

Reset Value

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

G2BT

G2BCR0

G2BCR1

BTSR

G2FE

G2RTP

G2MR

G2CR

G2TB

G2RB

XXXXh

00h

0000 0000b

XXXX 0000b

00h

00h

00XX X000b

0000 X110b

XXXXh

XXXXh

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 36 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.8

SFR List (8)

Address Register

000170h Group 2 IEBus Address Register

000171h

000172h Group 2 IEBus Control Register

000173h Group 2 IEBus Transmit Interrupt Source Detect Register

000174h Group 2 IEBus Receive Interrupt Source Detect Register

000175h

000176h

000177h

000178h

000179h

00017Ah

00017Bh

00017Ch

00017Dh

00017Eh

IEAR

IECR

IETIF

IERIF

Symbol

00017Fh

000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0

000181h

000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1

000183h

000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2

000185h

000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3

000187h

000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4

000189h

00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5

00018Bh

00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6

00018Dh

00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7

00018Fh

000190h Group 0 Waveform Generation Control Register 0

000191h Group 0 Waveform Generation Control Register 1

000192h Group 0 Waveform Generation Control Register 2

000193h Group 0 Waveform Generation Control Register 3

000194h Group 0 Waveform Generation Control Register 4

000195h Group 0 Waveform Generation Control Register 5

000196h Group 0 Waveform Generation Control Register 6

000197h Group 0 Waveform Generation Control Register 7

000198h Group 0 Time Measurement Control Register 0

000199h Group 0 Time Measurement Control Register 1

00019Ah Group 0 Time Measurement Control Register 2

00019Bh Group 0 Time Measurement Control Register 3

00019Ch Group 0 Time Measurement Control Register 4

00019Dh Group 0 Time Measurement Control Register 5

00019Eh Group 0 Time Measurement Control Register 6

00019Fh Group 0 Time Measurement Control Register 7

X: Undefined

Blanks are reserved. No access is allowed.

G0POCR0

G0POCR1

G0POCR2

G0POCR3

G0POCR4

G0POCR5

G0POCR6

G0POCR7

G0TMCR0

G0TMCR1

G0TMCR2

G0TMCR3

G0TMCR4

G0TMCR5

G0TMCR6

G0TMCR7

Reset Value

XXXXh

00XX X000b

XXX0 0000b

XXX0 0000b

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

00h

00h

00h

00h

00h

00h

00h

00h

0000 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

0X00 X000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 37 of 113

R32C/117A Group

Table 4.9

SFR List (9)

0001AFh

0001B0h

0001B1h

0001B2h

0001B3h

0001B4h

0001B5h

0001B6h

0001B7h

0001B8h

0001B9h

0001BAh

0001BBh

0001BCh

0001BDh

0001BEh

Address Register

0001A0h Group 0 Base Timer Register

0001A1h

0001A2h Group 0 Base Timer Control Register 0

0001A3h Group 0 Base Timer Control Register 1

0001A4h Group 0 Time Measurement Prescaler Register 6

0001A5h Group 0 Time Measurement Prescaler Register 7

0001A6h Group 0 Function Enable Register

0001A7h Group 0 Function Select Register

0001A8h

0001A9h

0001AAh

0001ABh

0001ACh

0001ADh

0001AEh

0001BFh

0001C0h

0001C1h

0001C2h

0001C3h

0001C4h UART5 Special Mode Register 4

0001C5h UART5 Special Mode Register 3

0001C6h UART5 Special Mode Register 2

0001C7h UART5 Special Mode Register

0001C8h UART5 Transmit/Receive Mode Register

0001C9h UART5 Bit Rate Register

0001CAh UART5 Transmit Buffer Register

0001CBh

0001CCh UART5 Transmit/Receive Control Register 0

0001CDh UART5 Transmit/Receive Control Register 1

0001CEh UART5 Receive Buffer Register

0001CFh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

G0BT

Symbol

G0BCR0

G0BCR1

G0TPR6

G0TPR7

G0FE

G0FS

Reset Value

XXXXh

00h

0000 0000b

00h

00h

00h

00h

U5SMR4

U5SMR3

U5SMR2

U5SMR

U5MR

U5BRG

U5TB

U5C0

U5C1

U5RB

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 38 of 113

R32C/117A Group

Table 4.10

SFR List (10)

Address

0001D0h

0001D1h

0001D2h

Register

0001D3h

0001D4h UART6 Special Mode Register 4

0001D5h UART6 Special Mode Register 3

0001D6h UART6 Special Mode Register 2

0001D7h UART6 Special Mode Register

0001D8h UART6 Transmit/Receive Mode Register

0001D9h UART6 Bit Rate Register

0001DAh UART6 Transmit Buffer Register

0001DBh

0001DCh UART6 Transmit/Receive Control Register 0

0001DDh UART6 Transmit/Receive Control Register 1

0001DEh UART6 Receive Buffer Register

0001DFh

0001E0h UART7 Transmit/Receive Mode Register

0001E1h UART7 Bit Rate Register

0001E2h UART7 Transmit Buffer Register

0001E3h

0001E4h UART7 Transmit/Receive Control Register 0

0001E5h UART7 Transmit/Receive Control Register 1

0001E6h UART7 Receive Buffer Register

0001E7h

0001E8h UART8 Transmit/Receive Mode Register

0001E9h UART8 Bit Rate Register

0001EAh UART8 Transmit Buffer Register

0001EBh

0001ECh UART8 Transmit/Receive Control Register 0

0001EDh UART8 Transmit/Receive Control Register 1

0001EEh UART8 Receive Buffer Register

0001EFh

0001F0h UART7, UART8 Transmit/Receive Control Register 2

0001F1h

0001F2h

0001F3h

0001F4h

0001F5h

0001F6h

0001F7h

0001F8h

0001F9h

0001FAh

0001FBh

0001FCh

0001FDh

0001FEh

0001FFh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol

U7C0

U7C1

U7RB

U8MR

U8BRG

U8TB

U8C0

U8C1

U8RB

U78CON

U6SMR4

U6SMR3

U6SMR2

U6SMR

U6MR

U6BRG

U6TB

U6C0

U6C1

U6RB

U7MR

U7BRG

U7TB

Reset Value

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

00h

XXh

XXXXh

00X0 1000b

XXXX 0010b

XXXXh

00h

XXh

XXXXh

00X0 1000b

XXXX 0010b

XXXXh

X000 0000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 39 of 113

R32C/117A Group

Table 4.11

SFR List (11)

Address

000200h to

0002BFh

0002C0h X0 Register/Y0 Register

0002C1h

0002C2h X1 Register/Y1 Register

0002C3h

0002C4h X2 Register/Y2 Register

0002C5h

0002C6h X3 Register/Y3 Register

0002C7h

0002C8h X4 Register/Y4 Register

0002C9h

0002CAh X5 Register/Y5 Register

0002CBh

0002CCh X6 Register/Y6 Register

0002CDh

0002CEh X7 Register/Y7 Register

0002CFh

0002D0h X8 Register/Y8 Register

0002D1h

0002D2h X9 Register/Y9 Register

0002D3h

0002D4h X10 Register/Y10 Register

0002D5h

0002D6h X11 Register/Y11 Register

0002D7h

0002D8h X12 Register/Y12 Register

0002D9h

0002DAh X13 Register/Y13 Register

0002DBh

Register

0002DCh X14 Register/Y14 Register

0002DDh

0002DEh X15 Register/Y15 Register

0002DFh

0002E0h X-Y Control Register

0002E1h

0002E2h

0002E3h

0002E4h UART1 Special Mode Register 4

0002E5h UART1 Special Mode Register 3

0002E6h UART1 Special Mode Register 2

0002E7h UART1 Special Mode Register

0002E8h UART1 Transmit/Receive Mode Register

0002E9h UART1 Bit Rate Register

0002EAh UART1 Transmit Buffer Register

0002EBh

0002ECh UART1 Transmit/Receive Control Register 0

0002EDh UART1 Transmit/Receive Control Register 1

0002EEh UART1 Receive Buffer Register

0002EFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

U1SMR4

U1SMR3

U1SMR2

U1SMR

U1MR

U1BRG

U1TB

U1C0

U1C1

U1RB

Symbol

X8R/Y8R

X9R/Y9R

X10R/Y10R

X11R/Y11R

X12R/Y12R

X13R/Y13R

X14R/Y14R

X15R/Y15R

XYC

X0R/Y0R

X1R/Y1R

X2R/Y2R

X3R/Y3R

X4R/Y4R

X5R/Y5R

X6R/Y6R

X7R/Y7R

Reset Value

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

XXXX XX00b

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

Page 40 of 113

R32C/117A Group

Table 4.12

SFR List (12)

Address

0002F0h

0002F1h

0002F2h

Register

0002F3h

0002F4h UART4 Special Mode Register 4

0002F5h UART4 Special Mode Register 3

0002F6h UART4 Special Mode Register 2

0002F7h UART4 Special Mode Register

0002F8h UART4 Transmit/Receive Mode Register

0002F9h UART4 Bit Rate Register

0002FAh UART4 Transmit Buffer Register

0002FBh

0002FCh UART4 Transmit/Receive Control Register 0

0002FDh UART4 Transmit/Receive Control Register 1

0002FEh UART4 Receive Buffer Register

0002FFh

000300h Count Start Register for Timers B3, B4, and B5

000301h

000302h Timer A1-1 Register

000303h

000304h Timer A2-1 Register

000305h

000306h Timer A4-1 Register

000307h

000308h Three-phase PWM Control Register 0

000309h Three-phase PWM Control Register 1

00030Ah Three-phase Output Buffer Register 0

00030Bh Three-phase Output Buffer Register 1

00030Ch Dead Time Timer

00030Dh Timer B2 Interrupt Generating Frequency Set Counter

00030Eh

00030Fh

000310h Timer B3 Register

000311h

000312h Timer B4 Register

000313h

000314h Timer B5 Register

000315h

000316h

000317h

000318h

000319h

00031Ah

00031Bh Timer B3 Mode Register

00031Ch Timer B4 Mode Register

00031Dh Timer B5 Mode Register

00031Eh

00031Fh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol

TBSR

TA11

TA21

TA41

INVC0

INVC1

IDB0

IDB1

DTT

ICTB2

U4SMR4

U4SMR3

U4SMR2

U4SMR

U4MR

U4BRG

U4TB

U4C0

U4C1

U4RB

TB3

TB4

TB5

TB3MR

TB4MR

TB5MR

Reset Value

00XX 0000b

00XX 0000b

00XX 0000b

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

000X XXXXb

XXXXh

XXXXh

XXXXh

00h

00h

XX11 1111b

XX11 1111b

XXh

XXh

XXXXh

XXXXh

XXXXh

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 41 of 113

R32C/117A Group

Table 4.13

SFR List (13)

Address

000320h

000321h

000322h

Register

000323h

000324h UART3 Special Mode Register 4

000325h UART3 Special Mode Register 3

000326h UART3 Special Mode Register 2

000327h UART3 Special Mode Register

000328h UART3 Transmit/Receive Mode Register

000329h UART3 Bit Rate Register

00032Ah UART3 Transmit Buffer Register

00032Bh

00032Ch UART3 Transmit/Receive Control Register 0

00032Dh UART3 Transmit/Receive Control Register 1

00032Eh UART3 Receive Buffer Register

00032Fh

000330h

000331h

000332h

000333h

000334h UART2 Special Mode Register 4

000335h UART2 Special Mode Register 3

000336h UART2 Special Mode Register 2

000337h UART2 Special Mode Register

000338h UART2 Transmit/Receive Mode Register

000339h UART2 Bit Rate Register

00033Ah UART2 Transmit Buffer Register

00033Bh

00033Ch UART2 Transmit/Receive Control Register 0

00033Dh UART2 Transmit/Receive Control Register 1

00033Eh UART2 Receive Buffer Register

00033Fh

000340h Count Start Register

000341h Clock Prescaler Reset Register

000342h One-shot Start Register

000343h Trigger Select Register

000344h Increment/Decrement Counting Select Register

000345h

000346h Timer A0 Register

000347h

000348h Timer A1 Register

000349h

00034Ah Timer A2 Register

00034Bh

00034Ch Timer A3 Register

00034Dh

00034Eh Timer A4 Register

00034Fh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol Reset Value

U3SMR4

U3SMR3

U3SMR2

U3SMR

U3MR

U3BRG

U3TB

U3C0

U3C1

U3RB

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

TA0

TA1

TA2

TA3

TA4

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

U2BRG

U2TB

U2C0

U2C1

U2RB

TABSR

CPSRF

ONSF

TRGSR

UDF

XXXXh

XXXXh

XXXXh

XXXXh

XXXXh

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

0000 0000b

0XXX XXXXb

0000 0000b

0000 0000b

0000 0000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 42 of 113

R32C/117A Group

Table 4.14

SFR List (14)

Address

000350h Timer B0 Register

000351h

000352h Timer B1 Register

000353h

000354h Timer B2 Register

000355h

000356h Timer A0 Mode Register

Register

000357h Timer A1 Mode Register

000358h Timer A2 Mode Register

000359h Timer A3 Mode Register

00035Ah Timer A4 Mode Register

00035Bh Timer B0 Mode Register

00035Ch Timer B1 Mode Register

00035Dh Timer B2 Mode Register

00035Eh Timer B2 Special Mode Register

00035Fh Count Source Prescaler Register

000360h

000361h

000362h

000363h

000364h UART0 Special Mode Register 4

000365h UART0 Special Mode Register 3

000366h UART0 Special Mode Register 2

000367h UART0 Special Mode Register

000368h UART0 Transmit/Receive Mode Register

000369h UART0 Bit Rate Register

00036Ah UART0 Transmit Buffer Register

00036Bh

00036Ch UART0 Transmit/Receive Control Register 0

00036Dh UART0 Transmit/Receive Control Register 1

00036Eh UART0 Receive Buffer Register

00036Fh

000370h

000371h

000372h

000373h

000374h

000375h

000376h

000377h

000378h

000379h

00037Ah

00037Bh

00037Ch CRC Data Register

00037Dh

00037Eh CRC Input Register

00037Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

TB0

Symbol

TB1

TB2

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

TCSPR

Reset Value

XXXXh

XXXXh

XXXXh

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

00XX 0000b

00XX 0000b

00XX 0000b

XXXX XXX0b

0000 0000b

U0SMR4

U0SMR3

U0SMR2

U0SMR

U0MR

U0BRG

U0TB

U0C0

U0C1

U0RB

00h

00h

00h

00h

00h

XXh

XXXXh

0000 1000b

0000 0010b

XXXXh

CRCD

CRCIN

XXXXh

XXh

Page 43 of 113

R32C/117A Group

Table 4.15

SFR List (15)

Address

000380h A/D0 Register 0

000381h

000382h A/D0 Register 1

000383h

000384h A/D0 Register 2

000385h

000386h A/D0 Register 3

000387h

000388h A/D0 Register 4

000389h

00038Ah A/D0 Register 5

00038Bh

00038Ch A/D0 Register 6

00038Dh

00038Eh A/D0 Register 7

00038Fh

000390h

000391h

000392h A/D0 Control Register 4

000393h A/D0 Control Register 5

000394h A/D0 Control Register 2

000395h A/D0 Control Register 3

000396h A/D0 Control Register 0

000397h A/D0 Control Register 1

000398h D/A Register 0

000399h

00039Ah D/A Register 1

00039Bh

00039Ch D/A Control Register

00039Dh

00039Eh

Register

00039Fh

0003A0h

0003A1h

0003A2h

0003A3h

0003A4h

0003A5h

0003A6h

0003A7h

0003A8h

0003A9h

0003AAh

0003ABh

0003ACh

0003ADh

0003AEh

0003AFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

AD00

Symbol

AD01

AD02

AD03

AD04

AD05

AD06

AD07

Reset Value

00XXh

00XXh

00XXh

00XXh

00XXh

00XXh

00XXh

00XXh

AD0CON4

AD0CON5

AD0CON2

AD0CON3

AD0CON0

AD0CON1

DA0

DA1

DACON

XXXX 00XXb

00h

XX0X X000b

XXXX X000b

00h

00h

XXh

XXh

XXXX XX00b

Page 44 of 113

R32C/117A Group

Table 4.16

SFR List (16)

Address

0003B0h

0003B1h

0003B2h

0003B3h

0003B4h

0003B5h

0003B6h

0003B7h

0003B8h

0003B9h

0003BAh

0003BBh

0003BCh

0003BDh

0003BEh

0003BFh

0003C0h Port P0 Register

0003C1h Port P1 Register

0003C2h Port P0 Direction Register

0003C3h Port P1 Direction Register

0003C4h Port P2 Register

0003C5h Port P3 Register

0003C6h Port P2 Direction Register

0003C7h Port P3 Direction Register

0003C8h Port P4 Register

0003C9h Port P5 Register

0003CAh Port P4 Direction Register

0003CBh Port P5 Direction Register

0003CCh Port P6 Register

0003CDh Port P7 Register

0003CEh Port P6 Direction Register

Register

0003CFh Port P7 Direction Register

0003D0h Port P8 Register

0003D1h Port P9 Register

0003D2h Port P8 Direction Register

0003D3h Port P9 Direction Register

0003D4h Port P10 Register

0003D5h Port P11 Register

0003D6h Port P10 Direction Register

0003D7h Port P11 Direction Register

0003D8h Port P12 Register

0003D9h Port P13 Register

0003DAh Port P12 Direction Register

0003DBh Port P13 Direction Register

0003DCh Port P14 Register

0003DDh Port P15 Register

0003DEh Port P14 Direction Register

0003DFh Port P15 Direction Register

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol Reset Value

P12

P13

PD12

PD13

P14

P15

PD14

PD15

P8

P9

PD8

PD9

P10

P11

PD10

PD11

P4

P5

PD4

PD5

P6

P7

PD6

PD7

P0

P1

PD0

PD1

P2

P3

PD2

PD3

XXh

XXh

00X0 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

Page 45 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.17

SFR List (17)

Address

0003E0h Port P16 Register

0003E1h Port P17 Register

0003E2h Port P16 Direction Register

Register

0003E3h Port P17 Direction Register

0003E4h Port P18 Register

0003E5h Port P19 Register

0003E6h Port P18 Direction Register

0003E7h Port P19 Direction Register

0003E8h

0003E9h

0003EAh

0003EBh

0003ECh

0003EDh

0003EEh

0003EFh

0003F0h Pull-up Control Register 0

0003F1h Pull-up Control Register 1

0003F2h Pull-up Control Register 2

0003F3h Pull-up Control Register 3

0003F4h Pull-up Control Register 4

0003F5h Pull-up Control Register 5

0003F6h

0003F7h

0003F8h

0003F9h

0003FAh

0003FBh

0003FCh

0003FDh

0003FEh

0003FFh Port Control Register

X: Undefined

Blanks are reserved. No access is allowed.

PCR

Note:

1.

The bit 7 is 0 in the 144-pin package and 1 in the 176-pin package.

P16

P17

PD16

PD17

P18

P19

PD18

PD19

Symbol

PUR0

PUR1

PUR2

PUR3

PUR4

PUR5

XXh

Reset Value

XXh

0000 0000b

0000 0000b

XXh

XXh

0000 0000b

0000 0000b

0000 0000b

XXXX X0XXb

X00X XXXXb

00XX 0000b

0XXX 0000b

XXXX 0000b

?0XX 0XX0b

(1)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 46 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.18

SFR List (18)

Address Register

040000h Flash Memory Control Register 0

040001h Flash Memory Status Register 0

040002h

040003h

040004h

040005h

040006h

040007h

040008h Flash Register Protection Unlock Register 0

040009h Flash Memory Control Register 1

04000Ah Block Protect Bit Monitor Register 0

04000Bh Block Protect Bit Monitor Register 1

04000Ch

04000Dh

04000Eh

04000Fh

040010h

040011h Block Protect Bit Monitor Register 2

040012h

040013h

040014h

040015h

040016h

040017h

040018h

040019h

04001Ah

04001Bh

04001Ch

04001Dh

04001Eh

04001Fh

040020h PLL Control Register 0

040021h PLL Control Register 1

040022h

040023h

040024h

040025h

040026h

040027h

040028h

040029h

04002Ah

04002Bh

04002Ch

04002Dh

04002Eh

04002Fh

X: Undefined

Blanks are reserved. No access is allowed.

Note:

1.

The status of protect bit of each block in flash memory is reflected.

Symbol

FMR0

FMSR0

FPR0

FMR1

FBPM0

FBPM1

FBPM2

PLC0

PLC1

Reset Value

0001 XX00b

1000 0000b

00h

0000 0010b

??X? ????b

(1)

XXX? ????b

(1)

???? ????b

(1)

0000 0001b

0001 1111b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 47 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.19

SFR List (19)

Address

040030h to

04003Fh

Register

040040h

040041h

040042h

040043h

040044h Processor Mode Register 0 (1)

Symbol Reset Value

PM0 1000 0000b

(CNVSS pin = Low)

0000 0011b

(CNVSS pin = High)

040045h

040046h System Clock Control Register 0

040047h System Clock Control Register 1

040048h Processor Mode Register 3

040049h

04004Ah Protect Register

04004Bh

04004Ch Protect Register 3

04004Dh Oscillator Stop Detection Register

04004Eh

04004Fh

040050h

040051h

040052h

040053h Processor Mode Register 2

040054h Chip Select Output Pin Setting Register 0

040055h Chip Select Output Pin Setting Register 1

040056h Chip Select Output Pin Setting Register 2

040057h

040058h

040059h

04005Ah Low Speed Mode Clock Control Register

04005Bh

04005Ch

04005Dh

04005Eh

04005Fh

040060h Voltage Regulator Control Register

040061h

040062h Low Voltage Detector Control Register

040063h

040064h Detection Voltage Configuration Register

040065h

040066h

040067h

040068h to

040093h

X: Undefined

Blanks are reserved. No access is allowed.

CM0

CM1

PM3

PRCR

PRCR3

CM2

PM2

CSOP0

CSOP1

CSOP2

CM3

VRCR

LVDC

DVCR

0000 1000b

0010 0000b

00h

XXXX X000b

0000 0000b

00h

00h

1000 XXXXb

01X0 XXXXb

XXXX 0000b

XXXX XX00b

0000 0000b

0000 XX00b

0000 XXXXb

Note:

1.

The value in the PM0 register remains unchanged even after a software reset or watchdog timer reset.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 48 of 113

R32C/117A Group

Table 4.20

SFR List (20)

Address

040094h

040095h

040096h

Register

040097h Three-phase Output Buffer Control Register

040098h Input Function Select Register 0

040099h Input Function Select Register 1

04009Ah Input Function Select Register 2

04009Bh Input Function Select Register 3

04009Ch

04009Dh

04009Eh

04009Fh

0400A0h Port P0_0 Function Select Register

0400A1h Port P1_0 Function Select Register

0400A2h Port P0_1 Function Select Register

0400A3h Port P1_1 Function Select Register

0400A4h Port P0_2 Function Select Register

0400A5h Port P1_2 Function Select Register

0400A6h Port P0_3 Function Select Register

0400A7h Port P1_3 Function Select Register

0400A8h Port P0_4 Function Select Register

0400A9h Port P1_4 Function Select Register

0400AAh Port P0_5 Function Select Register

0400ABh Port P1_5 Function Select Register

0400ACh Port P0_6 Function Select Register

0400ADh Port P1_6 Function Select Register

0400AEh Port P0_7 Function Select Register

0400AFh Port P1_7 Function Select Register

0400B0h Port P2_0 Function Select Register

0400B1h Port P3_0 Function Select Register

0400B2h Port P2_1 Function Select Register

0400B3h Port P3_1 Function Select Register

0400B4h Port P2_2 Function Select Register

0400B5h Port P3_2 Function Select Register

0400B6h Port P2_3 Function Select Register

0400B7h Port P3_3 Function Select Register

0400B8h Port P2_4 Function Select Register

0400B9h Port P3_4 Function Select Register

0400BAh Port P2_5 Function Select Register

0400BBh Port P3_5 Function Select Register

0400BCh Port P2_6 Function Select Register

0400BDh Port P3_6 Function Select Register

0400BEh Port P2_7 Function Select Register

0400BFh Port P3_7 Function Select Register

X: Undefined

Blanks are reserved. No access is allowed.

P2_4S

P3_4S

P2_5S

P3_5S

P2_6S

P3_6S

P2_7S

P3_7S

P2_0S

P3_0S

P2_1S

P3_1S

P2_2S

P3_2S

P2_3S

P3_3S

P0_4S

P1_4S

P0_5S

P1_5S

P0_6S

P1_6S

P0_7S

P1_7S

P0_0S

P1_0S

P0_1S

P1_1S

P0_2S

P1_2S

P0_3S

P1_3S

4. Special Function Registers (SFRs)

IOBC

IFS0

IFS1

IFS2

IFS3

Symbol Reset Value

0XXX XXXXb

X000 0000b

XXXX X0X0b

0000 00X0b

XX00 XX00b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 49 of 113

R32C/117A Group

Table 4.21

SFR List (21)

Address Register

0400C0h Port P4_0 Function Select Register

0400C1h Port P5_0 Function Select Register

0400C2h Port P4_1 Function Select Register

0400C3h Port P5_1 Function Select Register

0400C4h Port P4_2 Function Select Register

0400C5h Port P5_2 Function Select Register

0400C6h Port P4_3 Function Select Register

0400C7h Port P5_3 Function Select Register

0400C8h Port P4_4 Function Select Register

0400C9h Port P5_4 Function Select Register

0400CAh Port P4_5 Function Select Register

0400CBh Port P5_5 Function Select Register

0400CCh Port P4_6 Function Select Register

0400CDh Port P5_6 Function Select Register

0400CEh Port P4_7 Function Select Register

0400CFh Port P5_7 Function Select Register

0400D0h Port P6_0 Function Select Register

0400D1h Port P7_0 Function Select Register

0400D2h Port P6_1 Function Select Register

0400D3h Port P7_1 Function Select Register

0400D4h Port P6_2 Function Select Register

0400D5h Port P7_2 Function Select Register

0400D6h Port P6_3 Function Select Register

0400D7h Port P7_3 Function Select Register

0400D8h Port P6_4 Function Select Register

0400D9h Port P7_4 Function Select Register

0400DAh Port P6_5 Function Select Register

0400DBh Port P7_5 Function Select Register

0400DCh Port P6_6 Function Select Register

0400DDh Port P7_6 Function Select Register

0400DEh Port P6_7 Function Select Register

0400DFh Port P7_7 Function Select Register

0400E0h Port P8_0 Function Select Register

0400E1h Port P9_0 Function Select Register

0400E2h Port P8_1 Function Select Register

0400E3h Port P9_1 Function Select Register

0400E4h Port P8_2 Function Select Register

0400E5h Port P9_2 Function Select Register

0400E6h Port P8_3 Function Select Register

0400E7h Port P9_3 Function Select Register

0400E8h Port P8_4 Function Select Register

0400E9h Port P9_4 Function Select Register

0400EAh

0400EBh Port P9_5 Function Select Register

0400ECh Port P8_6 Function Select Register

0400EDh Port P9_6 Function Select Register

0400EEh Port P8_7 Function Select Register

0400EFh Port P9_7 Function Select Register

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

Reset Value

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

00XX X000b

XXXX X000b

00XX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

X0XX X000b

P7_7S

P8_0S

P9_0S

P8_1S

P9_1S

P8_2S

P9_2S

P8_3S

P9_3S

P8_4S

P9_4S

P7_3S

P6_4S

P7_4S

P6_5S

P7_5S

P6_6S

P7_6S

P6_7S

P5_7S

P6_0S

P7_0S

P6_1S

P7_1S

P6_2S

P7_2S

P6_3S

P5_3S

P4_4S

P5_4S

P4_5S

P5_5S

P4_6S

P5_6S

P4_7S

P4_0S

Symbol

P5_0S

P4_1S

P5_1S

P4_2S

P5_2S

P4_3S

P9_5S

P8_6S

P9_6S

P8_7S

P9_7S

Page 50 of 113

R32C/117A Group

Table 4.22

SFR List (22)

Address Register

0400F0h Port P10_0 Function Select Register

0400F1h Port P11_0 Function Select Register

0400F2h Port P10_1 Function Select Register

0400F3h Port P11_1 Function Select Register

0400F4h Port P10_2 Function Select Register

0400F5h Port P11_2 Function Select Register

0400F6h Port P10_3 Function Select Register

0400F7h Port P11_3 Function Select Register

0400F8h Port P10_4 Function Select Register

0400F9h Port P11_4 Function Select Register

0400FAh Port P10_5 Function Select Register

0400FBh Port P11_5 Function Select Register

0400FCh Port P10_6 Function Select Register

0400FDh Port P11_6 Function Select Register

0400FEh Port P10_7 Function Select Register

0400FFh Port P11_7 Function Select Register

040100h Port P12_0 Function Select Register

040101h Port P13_0 Function Select Register

040102h Port P12_1 Function Select Register

040103h Port P13_1 Function Select Register

040104h Port P12_2 Function Select Register

040105h Port P13_2 Function Select Register

040106h Port P12_3 Function Select Register

040107h Port P13_3 Function Select Register

040108h Port P12_4 Function Select Register

040109h Port P13_4 Function Select Register

04010Ah Port P12_5 Function Select Register

04010Bh Port P13_5 Function Select Register

04010Ch Port P12_6 Function Select Register

04010Dh Port P13_6 Function Select Register

04010Eh Port P12_7 Function Select Register

04010Fh Port P13_7 Function Select Register

040110h

040111h Port P15_0 Function Select Register

040112h

040113h Port P15_1 Function Select Register

040114h

040115h Port P15_2 Function Select Register

040116h Port P14_3 Function Select Register

040117h Port P15_3 Function Select Register

040118h Port P14_4 Function Select Register

040119h Port P15_4 Function Select Register

04011Ah Port P14_5 Function Select Register

04011Bh Port P15_5 Function Select Register

04011Ch Port P14_6 Function Select Register

04011Dh Port P15_6 Function Select Register

04011Eh Port P14_7 Function Select Register

04011Fh Port P15_7 Function Select Register

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

Reset Value

0XXX X000b

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

X0XX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

XXXX X000b

0XXX X000b

00XX X000b

00XX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

XXXX X000b

00XX X000b

P15_0S

P15_1S

P15_2S

P14_3S

P15_3S

P14_4S

P15_4S

P14_5S

P15_5S

P14_6S

P15_6S

P14_7S

P15_7S

P11_7S

P12_0S

P13_0S

P12_1S

P13_1S

P12_2S

P13_2S

P12_3S

P13_3S

P12_4S

P13_4S

P12_5S

P13_5S

P12_6S

P13_6S

P12_7S

P13_7S

Symbol

P10_0S

P11_0S

P10_1S

P11_1S

P10_2S

P11_2S

P10_3S

P11_3S

P10_4S

P11_4S

P10_5S

P11_5S

P10_6S

P11_6S

P10_7S

Page 51 of 113

R32C/117A Group

Table 4.23

SFR List (23)

Address Register

040120h Port P16_0 Function Select Register

040121h Port P17_0 Function Select Register

040122h Port P16_1 Function Select Register

040123h Port P17_1 Function Select Register

040124h Port P16_2 Function Select Register

040125h Port P17_2 Function Select Register

040126h Port P16_3 Function Select Register

040127h Port P17_3 Function Select Register

040128h Port P16_4 Function Select Register

040129h Port P17_4 Function Select Register

04012Ah Port P16_5 Function Select Register

04012Bh Port P17_5 Function Select Register

04012Ch Port P16_6 Function Select Register

04012Dh Port P17_6 Function Select Register

04012Eh Port P16_7 Function Select Register

04012Fh Port P17_7 Function Select Register

040130h Port P18_0 Function Select Register

040131h Port P19_0 Function Select Register

040132h Port P18_1 Function Select Register

040133h Port P19_1 Function Select Register

040134h Port P18_2 Function Select Register

040135h Port P19_2 Function Select Register

040136h Port P18_3 Function Select Register

040137h Port P19_3 Function Select Register

040138h Port P18_4 Function Select Register

040139h Port P19_4 Function Select Register

04013Ah Port P18_5 Function Select Register

04013Bh Port P19_5 Function Select Register

04013Ch Port P18_6 Function Select Register

04013Dh Port P19_6 Function Select Register

04013Eh Port P18_7 Function Select Register

04013Fh Port P19_7 Function Select Register

040140h

040141h

040142h

040143h

040144h

040145h

040146h

040147h

040148h

040149h

04014Ah

04014Bh

04014Ch

04014Dh

04014Eh

04014Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

P17_7S

P18_0S

P19_0S

P18_1S

P19_1S

P18_2S

P19_2S

P18_3S

P19_3S

P18_4S

P19_4S

P18_5S

P19_5S

P18_6S

P19_6S

P18_7S

P19_7S

Symbol

P16_0S

P17_0S

P16_1S

P17_1S

P16_2S

P17_2S

P16_3S

P17_3S

P16_4S

P17_4S

P16_5S

P17_5S

P16_6S

P17_6S

P16_7S

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

XXXX X000b

Reset Value

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

XXXX X000b

X0XX X000b

Page 52 of 113

R32C/117A Group

Table 4.24

SFR List (24)

Address

040150h to

0402FFh

Register

040300h UART9 Transmit/Receive Mode Register

040301h UART9 Bit Rate Register

040302h UART9 Transmit Buffer Register

040303h

040304h UART9 Transmit/Receive Control Register 0

040305h UART9 Transmit/Receive Control Register 1

040306h UART9 Receive Buffer Register

040307h

040308h UART10 Transmit/Receive Mode Register

040309h UART10 Bit Rate Register

04030Ah UART10 Transmit Buffer Register

04030Bh

04030Ch UART10 Transmit/Receive Control Register 0

04030Dh UART10 Transmit/Receive Control Register 1

04030Eh UART10 Receive Buffer Register

04030Fh

040310h UART9, UART10 Transmit/Receive Control Register 2

040311h

040312h

040313h

040314h

040315h

040316h

040317h

040318h to

041FFFh

042000h to

04201Fh

042020h to

04203Fh

042040h to

04205Fh

Protected Area 0

Protected Area 1

Protected Area 2

042060h to

04207Fh

042080h to

04209Fh

Protected Area 3

Protected Area 4

0420A0h to

0420EFh

0420F0h Protected Area Protect Release Register

0420F1h

0420F2h Protected Area Write Access Flag Register

0420F3h

0420F4h

0420F5h

0420F6h

0420F7h

0420F8h to

043FFFh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol

U9MR

U9BRG

U9TB

U9C0

U9C1

U9RB

U10MR

U10BRG

U10TB

U10C0

U10C1

U10RB

U910CON

Reset Value

00h

XXh

XXXXh

00X0 1000b

XXXX 0010b

XXXXh

00h

XXh

XXXXh

00X0 1000b

XXXX 0010b

XXXXh

X000 0000b

PAPR

PAWF

Undefined

Undefined

Undefined

Undefined

Undefined

XXX0 0000b

XXX0 0000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 53 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.25

SFR List (25)

Address

044000h to

04403Fh

044040h

044041h

044042h

044043h

Register

044044h

044045h

044046h

044047h

044048h

044049h

04404Ah

04404Bh

04404Ch Protect Register 4

04404Dh Watchdog Timer Clock Control Register

04404Eh Watchdog Timer Start Register

04404Fh Watchdog Timer Control Register

044050h

044051h

044052h

044053h

044054h

044055h

044056h

044057h

044058h

044059h

04405Ah

04405Bh

04405Ch

04405Dh

04405Eh

04405Fh Protect Register 2

X: Undefined

Blanks are reserved. No access is allowed.

Symbol

PRCR4

WDK

WDTS

WDC

PRCR2

Reset Value

0000 0000b

0000 000?b

(1)

XXXX XXXXb

000X XXXXb

0XXX XXXXb

Note:

1.

The bit 0 is set to 1 when the most recent reset is caused by the watchdog timer. Otherwise, it is set to 0.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 54 of 113

R32C/117A Group

Table 4.26

SFR List (26)

Address

044060h

044061h

044062h

044063h

044064h

044065h

044066h

Register

044067h

044068h

044069h

04406Ah

04406Bh

04406Ch

04406Dh External Interrupt Request Source Select Register 1

04406Eh

04406Fh External Interrupt Request Source Select Register 0

044070h DMA0 Request Source Select Register 2

044071h DMA1 Request Source Select Register 2

044072h DMA2 Request Source Select Register 2

044073h DMA3 Request Source Select Register 2

044074h

044075h

044076h

044077h

044078h DMA0 Request Source Select Register

044079h DMA1 Request Source Select Register

04407Ah DMA2 Request Source Select Register

04407Bh DMA3 Request Source Select Register

04407Ch

04407Dh Wake-up IPL Setting Register 2

04407Eh

04407Fh Wake-up IPL Setting Register 1

044080h

044081h

044082h

044083h

044084h

044085h

044086h

044087h

044088h

044089h

04408Ah

04408Bh

04408Ch

04408Dh

04408Eh

04408Fh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol Reset Value

IFSR1

IFSR0

DM0SL2

DM1SL2

DM2SL2

DM3SL2

DM0SL

DM1SL

DM2SL

DM3SL

RIPL2

RIPL1

X0XX X000b

0000 0000b

XX00 0000b

XX00 0000b

XX00 0000b

XX00 0000b

XXX0 0000b

XXX0 0000b

XXX0 0000b

XXX0 0000b

XX0X 0000b

XX0X 0000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 55 of 113

R32C/117A Group 4. Special Function Registers (SFRs)

Table 4.27

SFR List (27)

Address

044090h to

0443FFh

Register

044400h I 2

C Bus Transmit/Receive Shift Register

044401h

044402h I 2

C Bus Slave Address Register

044403h I

2

C Bus Control Register 0

044404h I 2

C Bus Clock Control Register

044405h I 2

C Bus START Condition/STOP Condition Control

Register

044406h I 2

C Bus Control Register 1

044407h I 2

C Bus Control Register 2

044408h I 2

C Bus Status Register

044409h

04440Ah

04440Bh

04440Ch

04440Dh

04440Eh

04440Fh

044410h I

2

C Bus Mode Register

044411h

044412h

044413h

044414h

044415h

044416h

044417h

044418h

044419h

04441Ah

04441Bh

04441Ch

04441Dh

04441Eh

04441Fh

044420h to

0467FFh

X: Undefined

Blanks are reserved. No access is allowed.

I2CMR

Symbol

I2CTRSR

I2CSAR

I2CCR0

I2CCCR

I2CSSCR

I2CCR1

I2CCR2

I2CSR

Reset Value

XXh

00h

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

0000 0000b

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 56 of 113

R32C/117A Group

Table 4.28

SFR List (28)

Address

046800h to

047BFFh

Register

047C00h CAN0 Mailbox 0: Message Identifier

047C01h

047C02h

047C03h

047C04h

047C05h CAN0 Mailbox 0: Data Length

047C06h CAN0 Mailbox 0: Data Field

047C07h

047C08h

047C09h

047C0Ah

047C0Bh

047C0Ch

047C0Dh

047C0Eh CAN0 Mailbox 0: Time Stamp

047C0Fh

047C10h CAN0 Mailbox 1: Message Identifier

047C11h

047C12h

047C13h

047C14h

047C15h CAN0 Mailbox 1: Data Length

047C16h CAN0 Mailbox 1: Data Field

047C17h

047C18h

047C19h

047C1Ah

047C1Bh

047C1Ch

047C1Dh

047C1Eh CAN0 Mailbox 1: Time Stamp

047C1Fh

047C20h CAN0 Mailbox 2: Message Identifier

047C21h

047C22h

047C23h

047C24h

047C25h CAN0 Mailbox 2: Data Length

047C26h CAN0 Mailbox 2: Data Field

047C27h

047C28h

047C29h

047C2Ah

047C2Bh

047C2Ch

047C2Dh

047C2Eh CAN0 Mailbox 2: Time Stamp

047C2Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB0

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB1

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB2

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 57 of 113

R32C/117A Group

Table 4.29

SFR List (29)

Address Register

047C30h CAN0 Mailbox 3: Message Identifier

047C31h

047C32h

047C33h

047C34h

047C35h CAN0 Mailbox 3: Data Length

047C36h CAN0 Mailbox 3: Data Field

047C37h

047C38h

047C39h

047C3Ah

047C3Bh

047C3Ch

047C3Dh

047C3Eh CAN0 Mailbox 3: Time Stamp

047C3Fh

047C40h CAN0 Mailbox 4: Message Identifier

047C41h

047C42h

047C43h

047C44h

047C45h CAN0 Mailbox 4: Data Length

047C46h CAN0 Mailbox 4: Data Field

047C47h

047C48h

047C49h

047C4Ah

047C4Bh

047C4Ch

047C4Dh

047C4Eh CAN0 Mailbox 4: Time Stamp

047C4Fh

047C50h CAN0 Mailbox 5: Message Identifier

047C51h

047C52h

047C53h

047C54h

047C55h CAN0 Mailbox 5: Data Length

047C56h CAN0 Mailbox 5: Data Field

047C57h

047C58h

047C59h

047C5Ah

047C5Bh

047C5Ch

047C5Dh

047C5Eh CAN0 Mailbox 5: Time Stamp

047C5Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB3

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB4

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB5

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 58 of 113

R32C/117A Group

Table 4.30

SFR List (30)

Address Register

047C60h CAN0 Mailbox 6: Message Identifier

047C61h

047C62h

047C63h

047C64h

047C65h CAN0 Mailbox 6: Data Length

047C66h CAN0 Mailbox 6: Data Field

047C67h

047C68h

047C69h

047C6Ah

047C6Bh

047C6Ch

047C6Dh

047C6Eh CAN0 Mailbox 6: Time Stamp

047C6Fh

047C70h CAN0 Mailbox 7: Message Identifier

047C71h

047C72h

047C73h

047C74h

047C75h CAN0 Mailbox 7: Data Length

047C76h CAN0 Mailbox 7: Data Field

047C77h

047C78h

047C79h

047C7Ah

047C7Bh

047C7Ch

047C7Dh

047C7Eh CAN0 Mailbox 7: Time Stamp

047C7Fh

047C80h CAN0 Mailbox 8: Message Identifier

047C81h

047C82h

047C83h

047C84h

047C85h CAN0 Mailbox 8: Data Length

047C86h CAN0 Mailbox 8: Data Field

047C87h

047C88h

047C89h

047C8Ah

047C8Bh

047C8Ch

047C8Dh

047C8Eh CAN0 Mailbox 8: Time Stamp

047C8Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB6

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB7

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB8

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 59 of 113

R32C/117A Group

Table 4.31

SFR List (31)

Address Register

047C90h CAN0 Mailbox 9: Message Identifier

047C91h

047C92h

047C93h

047C94h

047C95h CAN0 Mailbox 9: Data Length

047C96h CAN0 Mailbox 9: Data Field

047C97h

047C98h

047C99h

047C9Ah

047C9Bh

047C9Ch

047C9Dh

047C9Eh CAN0 Mailbox 9: Time Stamp

047C9Fh

047CA0h CAN0 Mailbox 10: Message Identifier

047CA1h

047CA2h

047CA3h

047CA4h

047CA5h CAN0 Mailbox 10: Data Length

047CA6h CAN0 Mailbox 10: Data Field

047CA7h

047CA8h

047CA9h

047CAAh

047CABh

047CACh

047CADh

047CAEh CAN0 Mailbox 10: Time Stamp

047CAFh

047CB0h CAN0 Mailbox 11: Message Identifier

047CB1h

047CB2h

047CB3h

047CB4h

047CB5h CAN0 Mailbox 11: Data Length

047CB6h CAN0 Mailbox 11: Data Field

047CB7h

047CB8h

047CB9h

047CBAh

047CBBh

047CBCh

047CBDh

047CBEh CAN0 Mailbox 11: Time Stamp

047CBFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB9

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB10

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB11

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 60 of 113

R32C/117A Group

Table 4.32

SFR List (32)

Address Register

047CC0h CAN0 Mailbox 12: Message Identifier

047CC1h

047CC2h

047CC3h

047CC4h

047CC5h CAN0 Mailbox 12: Data Length

047CC6h CAN0 Mailbox 12: Data Field

047CC7h

047CC8h

047CC9h

047CCAh

047CCBh

047CCCh

047CCDh

047CCEh CAN0 Mailbox 12: Time Stamp

047CCFh

047CD0h CAN0 Mailbox 13: Message Identifier

047CD1h

047CD2h

047CD3h

047CD4h

047CD5h CAN0 Mailbox 13: Data Length

047CD6h CAN0 Mailbox 13: Data Field

047CD7h

047CD8h

047CD9h

047CDAh

047CDBh

047CDCh

047CDDh

047CDEh CAN0 Mailbox 13: Time Stamp

047CDFh

047CE0h CAN0 Mailbox 14: Message Identifier

047CE1h

047CE2h

047CE3h

047CE4h

047CE5h CAN0 Mailbox 14: Data Length

047CE6h CAN0 Mailbox 14: Data Field

047CE7h

047CE8h

047CE9h

047CEAh

047CEBh

047CECh

047CEDh

047CEEh CAN0 Mailbox 14: Time Stamp

047CEFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB12

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB13

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB14

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 61 of 113

R32C/117A Group

Table 4.33

SFR List (33)

Address Register

047CF0h CAN0 Mailbox 15: Message Identifier

047CF1h

047CF2h

047CF3h

047CF4h

047CF5h CAN0 Mailbox 15: Data Length

047CF6h CAN0 Mailbox 15: Data Field

047CF7h

047CF8h

047CF9h

047CFAh

047CFBh

047CFCh

047CFDh

047CFEh CAN0 Mailbox 15: Time Stamp

047CFFh

047D00h CAN0 Mailbox 16: Message Identifier

047D01h

047D02h

047D03h

047D04h

047D05h CAN0 Mailbox 16: Data Length

047D06h CAN0 Mailbox 16: Data Field

047D07h

047D08h

047D09h

047D0Ah

047D0Bh

047D0Ch

047D0Dh

047D0Eh CAN0 Mailbox 16: Time Stamp

047D0Fh

047D10h CAN0 Mailbox 17: Message Identifier

047D11h

047D12h

047D13h

047D14h

047D15h CAN0 Mailbox 17: Data Length

047D16h CAN0 Mailbox 17: Data Field

047D17h

047D18h

047D19h

047D1Ah

047D1Bh

047D1Ch

047D1Dh

047D1Eh CAN0 Mailbox 17: Time Stamp

047D1Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB15

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB16

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB17

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 62 of 113

R32C/117A Group

Table 4.34

SFR List (34)

Address Register

047D20h CAN0 Mailbox 18: Message Identifier

047D21h

047D22h

047D23h

047D24h

047D25h CAN0 Mailbox 18: Data Length

047D26h CAN0 Mailbox 18: Data Field

047D27h

047D28h

047D29h

047D2Ah

047D2Bh

047D2Ch

047D2Dh

047D2Eh CAN0 Mailbox 18: Time Stamp

047D2Fh

047D30h CAN0 Mailbox 19: Message Identifier

047D31h

047D32h

047D33h

047D34h

047D35h CAN0 Mailbox 19: Data Length

047D36h CAN0 Mailbox 19: Data Field

047D37h

047D38h

047D39h

047D3Ah

047D3Bh

047D3Ch

047D3Dh

047D3Eh CAN0 Mailbox 19: Time Stamp

047D3Fh

047D40h CAN0 Mailbox 20: Message Identifier

047D41h

047D42h

047D43h

047D44h

047D45h CAN0 Mailbox 20: Data Length

047D46h CAN0 Mailbox 20: Data Field

047D47h

047D48h

047D49h

047D4Ah

047D4Bh

047D4Ch

047D4Dh

047D4Eh CAN0 Mailbox 20: Time Stamp

047D4Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB18

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB19

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB20

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 63 of 113

R32C/117A Group

Table 4.35

SFR List (35)

Address Register

047D50h CAN0 Mailbox 21: Message Identifier

047D51h

047D52h

047D53h

047D54h

047D55h CAN0 Mailbox 21: Data Length

047D56h CAN0 Mailbox 21: Data Field

047D57h

047D58h

047D59h

047D5Ah

047D5Bh

047D5Ch

047D5Dh

047D5Eh CAN0 Mailbox 21: Time Stamp

047D5Fh

047D60h CAN0 Mailbox 22: Message Identifier

047D61h

047D62h

047D63h

047D64h

047D65h CAN0 Mailbox 22: Data Length

047D66h CAN0 Mailbox 22: Data Field

047D67h

047D68h

047D69h

047D6Ah

047D6Bh

047D6Ch

047D6Dh

047D6Eh CAN0 Mailbox 22: Time Stamp

047D6Fh

047D70h CAN0 Mailbox 23: Message Identifier

047D71h

047D72h

047D73h

047D74h

047D75h CAN0 Mailbox 23: Data Length

047D76h CAN0 Mailbox 23: Data Field

047D77h

047D78h

047D79h

047D7Ah

047D7Bh

047D7Ch

047D7Dh

047D7Eh CAN0 Mailbox 23: Time Stamp

047D7Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB21

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB22

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB23

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 64 of 113

R32C/117A Group

Table 4.36

SFR List (36)

Address Register

047D80h CAN0 Mailbox 24: Message Identifier

047D81h

047D82h

047D83h

047D84h

047D85h CAN0 Mailbox 24: Data Length

047D86h CAN0 Mailbox 24: Data Field

047D87h

047D88h

047D89h

047D8Ah

047D8Bh

047D8Ch

047D8Dh

047D8Eh CAN0 Mailbox 24: Time Stamp

047D8Fh

047D90h CAN0 Mailbox 25: Message Identifier

047D91h

047D92h

047D93h

047D94h

047D95h CAN0 Mailbox 25: Data Length

047D96h CAN0 Mailbox 25: Data Field

047D97h

047D98h

047D99h

047D9Ah

047D9Bh

047D9Ch

047D9Dh

047D9Eh CAN0 Mailbox 25: Time Stamp

047D9Fh

047DA0h CAN0 Mailbox 26: Message Identifier

047DA1h

047DA2h

047DA3h

047DA4h

047DA5h CAN0 Mailbox 26: Data Length

047DA6h CAN0 Mailbox 26: Data Field

047DA7h

047DA8h

047DA9h

047DAAh

047DABh

047DACh

047DADh

047DAEh CAN0 Mailbox 26: Time Stamp

047DAFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB24

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB25

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB26

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 65 of 113

R32C/117A Group

Table 4.37

SFR List (37)

Address Register

047DB0h CAN0 Mailbox 27: Message Identifier

047DB1h

047DB2h

047DB3h

047DB4h

047DB5h CAN0 Mailbox 27: Data Length

047DB6h CAN0 Mailbox 27: Data Field

047DB7h

047DB8h

047DB9h

047DBAh

047DBBh

047DBCh

047DBDh

047DBEh CAN0 Mailbox 27: Time Stamp

047DBFh

047DC0h CAN0 Mailbox 28: Message Identifier

047DC1h

047DC2h

047DC3h

047DC4h

047DC5h CAN0 Mailbox 28: Data Length

047DC6h CAN0 Mailbox 28: Data Field

047DC7h

047DC8h

047DC9h

047DCAh

047DCBh

047DCCh

047DCDh

047DCEh CAN0 Mailbox 28: Time Stamp

047DCFh

047DD0h CAN0 Mailbox 29: Message Identifier

047DD1h

047DD2h

047DD3h

047DD4h

047DD5h CAN0 Mailbox 29: Data Length

047DD6h CAN0 Mailbox 29: Data Field

047DD7h

047DD8h

047DD9h

047DDAh

047DDBh

047DDCh

047DDDh

047DDEh CAN0 Mailbox 29: Time Stamp

047DDFh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB27

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB28

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB29

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

XXXXh

Page 66 of 113

R32C/117A Group

Table 4.38

SFR List (38)

Address Register

047DE0h CAN0 Mailbox 30: Message Identifier

047DE1h

047DE2h

047DE3h

047DE4h

047DE5h CAN0 Mailbox 30: Data Length

047DE6h CAN0 Mailbox 30: Data Field

047DE7h

047DE8h

047DE9h

047DEAh

047DEBh

047DECh

047DEDh

047DEEh CAN0 Mailbox 30: Time Stamp

047DEFh

047DF0h CAN0 Mailbox 31: Message Identifier

047DF1h

047DF2h

047DF3h

047DF4h

047DF5h CAN0 Mailbox 31: Data Length

047DF6h CAN0 Mailbox 31: Data Field

047DF7h

047DF8h

047DF9h

047DFAh

047DFBh

047DFCh

047DFDh

047DFEh CAN0 Mailbox 31: Time Stamp

047DFFh

047E00h CAN0 Acceptance Mask Register 0

047E01h

047E02h

047E03h

047E04h CAN0 Acceptance Mask Register 1

047E05h

047E06h

047E07h

047E08h CAN0 Acceptance Mask Register 2

047E09h

047E0Ah

047E0Bh

047E0Ch CAN0 Acceptance Mask Register 3

047E0Dh

047E0Eh

047E0Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MB30

Reset Value

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MB31

XXXXh

XXXX XXXXh

XXh

XXXX XXXX

XXXX XXXXh

C0MKR0

C0MKR1

C0MKR2

C0MKR3

XXXXh

XXXX XXXXh

XXXX XXXXh

XXXX XXXXh

XXXX XXXXh

Page 67 of 113

R32C/117A Group

Table 4.39

SFR List (39)

Address Register

047E10h CAN0 Acceptance Mask Register 4

047E11h

047E12h

047E13h

047E14h CAN0 Acceptance Mask Register 5

047E15h

047E16h

047E17h

047E18h CAN0 Acceptance Mask Register 6

047E19h

047E1Ah

047E1Bh

047E1Ch CAN0 Acceptance Mask Register 7

047E1Dh

047E1Eh

047E1Fh

047E20h CAN0 FIFO Receive ID Compare Register 0

047E21h

047E22h

047E23h

047E24h CAN0 FIFO Receive ID Compare Register 1

047E25h

047E26h

047E27h

047E28h CAN0 Mask Invalid Register

047E29h

047E2Ah

047E2Bh

047E2Ch CAN0 Mailbox Interrupt Enable Register

047E2Dh

047E2Eh

047E2Fh

047E30h

047E31h

047E32h

047E33h

047E34h

047E35h

047E36h

047E37h

047E38h

047E39h

047E3Ah

047E3Bh

047E3Ch

047E3Dh

047E3Eh

047E3Fh

047E40h to

047F1Fh

X: Undefined

Blanks are reserved. No access is allowed.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

4. Special Function Registers (SFRs)

Symbol

C0MKR4

Reset Value

XXXX XXXXh

C0MKR5

C0MKR6

XXXX XXXXh

XXXX XXXXh

C0MKR7

C0FIDCR0

C0FIDCR1

C0MKIVLR

C0MIER

XXXX XXXXh

XXXX XXXXh

XXXX XXXXh

XXXX XXXXh

XXXX XXXXh

Page 68 of 113

R32C/117A Group

Table 4.40

SFR List (40)

Address Register

047F20h CAN0 Message Control Register 0

047F21h CAN0 Message Control Register 1

047F22h CAN0 Message Control Register 2

047F23h CAN0 Message Control Register 3

047F24h CAN0 Message Control Register 4

047F25h CAN0 Message Control Register 5

047F26h CAN0 Message Control Register 6

047F27h CAN0 Message Control Register 7

047F28h CAN0 Message Control Register 8

047F29h CAN0 Message Control Register 9

047F2Ah CAN0 Message Control Register 10

047F2Bh CAN0 Message Control Register 11

047F2Ch CAN0 Message Control Register 12

047F2Dh CAN0 Message Control Register 13

047F2Eh CAN0 Message Control Register 14

047F2Fh CAN0 Message Control Register 15

047F30h CAN0 Message Control Register 16

047F31h CAN0 Message Control Register 17

047F32h CAN0 Message Control Register 18

047F33h CAN0 Message Control Register 19

047F34h CAN0 Message Control Register 20

047F35h CAN0 Message Control Register 21

047F36h CAN0 Message Control Register 22

047F37h CAN0 Message Control Register 23

047F38h CAN0 Message Control Register 24

047F39h CAN0 Message Control Register 25

047F3Ah CAN0 Message Control Register 26

047F3Bh CAN0 Message Control Register 27

047F3Ch CAN0 Message Control Register 28

047F3Dh CAN0 Message Control Register 29

047F3Eh CAN0 Message Control Register 30

047F3Fh CAN0 Message Control Register 31

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

C0MCTL15

C0MCTL16

C0MCTL17

C0MCTL18

C0MCTL19

C0MCTL20

C0MCTL21

C0MCTL22

C0MCTL23

C0MCTL24

C0MCTL25

C0MCTL26

C0MCTL27

C0MCTL28

C0MCTL29

C0MCTL30

C0MCTL31

Symbol

C0MCTL0

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

C0MCTL11

C0MCTL12

C0MCTL13

C0MCTL14

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

Reset Value

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 69 of 113

R32C/117A Group

Table 4.41

SFR List (41)

Address

047F40h CAN0 Control Register

047F41h

047F42h CAN0 Status Register

Register

047F43h

047F44h CAN0 Bit Configuration Register

047F45h

047F46h

047F47h CAN0 Clock Select Register

047F48h CAN0 Receive FIFO Control Register

047F49h CAN0 Receive FIFO Pointer Control Register

047F4Ah CAN0 Transmit FIFO Control Register

047F4Bh CAN0 Transmit FIFO Pointer Control Register

047F4Ch CAN0 Error Interrupt Enable Register

047F4Dh CAN0 Error Interrupt Factor Judge Register

047F4Eh CAN0 Receive Error Count Register

047F4Fh CAN0 Transmit Error Count Register

047F50h CAN0 Error Code Store Register

047F51h CAN0 Channel Search Support Register

047F52h CAN0 Mailbox Search Status Register

047F53h CAN0 Mailbox Search Mode Register

047F54h CAN0 Time Stamp Register

047F55h

047F56h CAN0 Acceptance Filter Support Register

047F57h

047F58h CAN0 Test Control Register

047F59h

047F5Ah

047F5Bh

047F5Ch

047F5Dh

047F5Eh

047F5Fh

047F60h to

047FFFh

048000h to

04FFFFh

X: Undefined

Blanks are reserved. No access is allowed.

4. Special Function Registers (SFRs)

Symbol

C0CTLR

C0STR

C0BCR

C0CLKR

C0RFCR

C0RFPCR

C0TFCR

C0TFPCR

C0EIER

C0EIFR

C0RECR

C0TECR

C0ECSR

C0CSSR

C0MSSR

C0MSMR

C0TSR

C0AFSR

C0TCR

Reset Value

0000 0101b

0000 0000b

0000 0101b

0000 0000b

00 0000h

000X 0000b

1000 0000b

XXh

1000 0000b

XXh

00h

00h

00h

00h

00h

XXh

1000 0000b

XXXX XX00b

0000h

XXXXh

00h

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 70 of 113

R32C/117A Group 5. Electrical Characteristics

5.

Electrical Characteristics

Table 5.1

Symbol

V

CC

AV

CC

V

I

Absolute Maximum Ratings

Supply voltage

Characteristic

Analog supply voltage

(1)

V

Condition

V

CC

CC

= AV

CC

= AV

CC

Value Unit

-0.3 to 6.0

-0.3 to 6.0

V

V

V

P

O d

T stg

Input voltage

XIN, RESET, CNVSS, NSD, V

REF

,

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P5_0 to P5_3, P8_4 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P13_0 to P13_7,

P14_1, P14_3 to P14_7,

P15_0 to P15_7, P17_4 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(2)

P4_0 to P4_7, P5_4 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_3, P12_0 to P12_7,

P16_0 to P16_7, P17_0 to P17_3

(2)

Output voltage

XOUT, P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(2)

Power consumption

Operating temperature range

Storage temperature range

Ta = 25°C

-0.3 to V

-0.3 to 6.0

-0.3 to V

CC

CC

500

+ 0.3

+ 0.3

-40 to 85

-65 to 150

V

V

V mW

°C

°C

Notes:

1.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2.

Ports P16 to P19 are available in the 176-pin package only.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 71 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.2

Operating Conditions (1/5)

(1)

Symbol Characteristic

V

CC

AV

CC

V

REF

V

SS

Digital supply voltage

Analog supply voltage

Reference voltage

Digital ground voltage

AV

SS dV

CC

/dt V

CC

ramp up rate (V

CC

< 2.0 V)

V

IH

Analog ground voltage

High level input voltage

XIN, RESET, CNVSS, NSD, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P17_4 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(3)

(2)

,

P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,

P7_0 to P7_7, P8_0 to P8_3, P16_0 to P16_7,

P17_0 to P17_3

(3)

P0_0 to P0_7,

P1_0 to P1_7, in single-chip mode

P13_0 to P13_7 in memory expansion mode or microprocessor mode

P12_0 to P12_7 in single-chip mode

Min.

3.0

3.0

0.05

0.8 × V

CC

0.8 × V

CC

0.8 × V

CC

0.5 × V

CC

0.8 × V

CC

Value

Typ.

5.0

V

CC

0

0

Max.

5.5

V

V

CC

CC

6.0

V

V

CC

CC

6.0

Unit

V

V

V

V

V

V

T

IL opr

Low level input voltage in memory expansion mode or microprocessor mode

XIN, RESET, CNVSS, NSD, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7

(2)

,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(3)

P0_0 to P0_7, in single-chip mode

P1_0 to P1_7,

P12_0 to P12_7, in memory expansion mode or microprocessor mode

P13_0 to P13_7

Operating N version temperature

D version range

P version

0.5 × V

CC

0

0

0

-20

-40

-40

6.0

0.2 × V

0.2 × V

0.16 × V

85

85

85

CC

CC

CC

V

V

V

V

°C

°C

°C

Notes:

1.

The device is operationally guaranteed under these operating conditions.

2.

V

IH

and V

IL

for P8_7 are specified for P8_7 as a programmable port. These values are not applicable to P8_7 as XCIN.

3.

Ports P16 to P19 are available in the 176-pin package only.

V

V

V

V

V

V/ms

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 72 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.3

C

Symbol

VDC

Operating Conditions (2/5)

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

(1)

Characteristic

Value

(2)

Min.

Typ. Max.

Decoupling capacitance for voltage regulator

Inter-pin voltage: 1.5 V

2.4

10.0

Unit

µF

Notes:

1.

The device is operationally guaranteed under these operating conditions.

2.

This value should be satisfied with due consideration of every condition as follows: operating temperature, DC bias, aging, etc.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 73 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.4

Symbol

Operating Conditions (3/5)

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

(1)

Characteristic

Min.

Value

Typ.

Max.

I

OH

(peak) High level peak

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, output current

(2)

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7

(3)

I

OH

(avg)

High level average output current

(4)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7

(3)

I

OL

(peak) Low level peak output current

(2)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7

(3)

I

OL

(avg)

Low level average output current

(4)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7, P19_0 to P19_7

(3)

-10.0

-5.0

10.0

5.0

Unit mA mA mA mA

Notes:

1.

The device is operationally guaranteed under these operating conditions.

2.

The following conditions should be satisfied:

• The sum of I

OL(peak)

of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11_0 to P11_4, P14_3 to P14_6,

P15, P18_2 to P18_7, P19_0, P19_1, P19_6, and P19_7 is 80 mA or less.

• The sum of I

OL(peak)

of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P11_5 to P11_7, P12, P13, P14_7,

P16, P17, P18_0, P18_1, and P19_2 to P19_5 is 80 mA or less.

• The sum of I

OH(peak)

of ports P0, P1, P2, P11_0 to P11_4, P18_2 to P18_7, P19_0, and P19_1 is

-40 mA or less.

• The sum of I

OH(peak)

of ports P8_6, P8_7, P9, P10, P14_3 to P14_6, P15, P19_6, and P19_7 is -40 mA or less.

• The sum of I

OH(peak)

of ports P3, P4, P5, P11_5, P11_6, P12, P13, P16, P17_0 to P17_3, and

P19_2 to P19_5 is -40 mA or less.

• The sum of I

OH(peak)

of ports P6, P7, P8_0 to P8_4, P11_7, P14_7, P17_4 to P17_7, P18_0, and

P18_1 is -40 mA or less.

3.

Ports P16 to P19 are available in the 176-pin package only.

4.

Average value within 100 ms.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 74 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.5

Symbol

Operating Conditions (4/5)

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

(1)

Characteristic

Min.

4

Value

Typ.

f

(XIN) f

(XRef) f

(PLL) f

(Base) t c(Base) f

(CPU) tc

(CPU)

Main clock oscillator frequency

Reference clock frequency

PLL clock oscillator frequency

Base clock frequency

Base clock cycle time

CPU operating frequency

CPU clock cycle time f f

(BCLK)

Peripheral bus clock operating frequency tc

(BCLK)

Peripheral bus clock cycle time

(PER) f

(XCIN)

Peripheral clock source frequency

Sub clock oscillator frequency

2

96

15.625

15.625

31.25

32.768

Note:

1.

The device is operationally guaranteed under these operating conditions.

Unit

Max.

16

4

MHz

MHz

128 MHz

64 MHz

64 ns

MHz ns

32 MHz ns

32 MHz

62.5

kHz

Base clock

(Internal signal)

CPU clock

(Internal signal)

Peripheral bus clock

(Internal signal)

Figure 5.1

Clock Cycle Time

t

c(Base) t

c(CPU) t

c(BCLK)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 75 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.6

V

Symbol r(VCC) dV r(VCC)

Operating Conditions (5/5)

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

(1)

Allowable ripple voltage

Characteristic

Value

Min.

Typ.

Max.

Unit

0.5

Vp-p

/dt Ripple voltage gradient

V

CC

= 5.0 V

V

CC

= 3.0 V

V

CC

= 5.0 V

V

CC

= 3.0 V

0.3

±0.3

±0.3

Vp-p

V/ms

V/ms f r(VCC)

Allowable ripple frequency

10 kHz

Note:

1.

The device is operationally guaranteed under these operating conditions.

1 / f r(VCC)

V

CC

V r(VCC)

Figure 5.2

Ripple Waveform

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 76 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.7

V

Symbol

RDR

RAM Electrical Characteristics

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and Ta = T opr

, unless otherwise noted)

Characteristic

RAM data retention voltage

Measurement condition in stop mode

Min.

2.0

Value

Typ.

Max.

Unit

V

Table 5.8

t

Symbol

SUSP

Flash Memory Electrical Characteristics

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and Ta = T opr

, unless otherwise noted)

Lock bit-program time

Block erasure time

Suspend latency

Characteristic

Programming and erasure endurance of flash Program area memory

(1)

Data area

4-word program time Program area

Data area

Program area

Data area

4 Kbyte block

32 Kbyte block

64 Kbyte block

Min.

1000

10000

Value

Typ.

Max.

Unit times times

150 900 µs

300 1700 µs

70 500 µs

140 1000 µs

0.12

0.17

0.20

3.0

3.0

3.0

s s s

250 µs

Data retention

(2)

Ta = 55°C

(3)

10 years

Notes:

1.

Program/erase definition

This value represents the number of erasures per block.

If the flash memory is programmed/erased n times, each block can be erased n times.

i.e. If 4-word write is performed in 512 different addresses in the block A of 4 Kbyte and then the block is erased, it is considered the programming/erasure is performed just once.

However a write in the same address more than once for one erasure is disabled (overwrite disabled).

2.

The data retention time includes the periods when the supply voltage is not applied and no clock is provided.

3.

Please contact a Renesas Electronics sales office regarding data retention time other than the above.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 77 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.9

Symbol

Power Supply Circuit Timing Characteristics

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Characteristic

Measurement condition

Value

Min.

Typ. Max.

td(P-R) Internal power supply start-up stabilization time after the main power supply is turned on

2

Unit ms t

d(P-R)

Internal power supply start-up stabilization time after the main power supply is turned on

V

CC

Recommended operating voltage

Supply voltage for internal logic

PLL oscillatoroutput waveform

Figure 5.3

Power Supply Circuit Timing

t

d(P-R)

Table 5.10

Electrical Characteristics of Voltage Regulator for Internal Logic

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

V

Symbol

VDC1

Characteristics

Output voltage

Measurement condition

Value

Min.

Typ.

Max.

1.5

Unit

V

Table 5.11

Electrical Characteristics of Low Voltage Detector

(V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Symbol Characteristics

Measurement condition t

ΔVdet

Detected voltage error

Vdet(R)-Vdet(F) Hysteresis width d(E-A)

Self-consuming current V

CC

= 5.0 V, low voltage detector enabled

Operation start time of low voltage detector

Value

Min.

Typ.

Max.

±0.3

0

4

150

Unit

V

V

µA

µs

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 78 of 113

R32C/117A Group 5. Electrical Characteristics

Table 5.12

Electrical Characteristics of Oscillator

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Symbol Characteristics

PLL clock self-oscillation frequency

Measurement condition

Value

Min.

Typ.

Max.

35 55

Unit

80

MHz f

SO(PLL) t

LOCK(PLL) t jitter(p-p) f

(OCO)

PLL lock time

(1)

PLL jitter period (p-p)

On-chip oscillator frequency

62.5

125

1

2.0

250 ms ns kHz

Note:

1.

This value is applicable only when the main clock oscillation is stable.

Table 5.13

Electrical Characteristics of Clock Circuitry

(V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

t

Symbol rec(WAIT) t rec(STOP)

Characteristics

Recovery time from wait mode to low power mode

Recovery time from stop mode

(1)

Measurement condition

Value

Min.

Typ.

Max.

Unit

225 µs

225 µs

Note:

1.

This recovery time does not include the period until the main clock oscillator is stabilized. The CPU starts operating before the oscillator is stabilized.

t

rec(WAIT)

Recovery time from wait mode to low power mode

Interrupt for exiting wait mode

Sub clock oscillator output

On-chip oscillator output

CPU clock t

rec(WAIT) t

rec(STOP)

Recovery time from stop mode

Interrupt for exiting stop mode

Main clock oscillator output

On-chip oscillator output

CPU clock

Figure 5.4

Clock Circuit Timing

REJ03B0298-0100 Rev.1.00

Jul 16, 2010 t

rec(STOP)

Page 79 of 113

R32C/117A Group 5. Electrical Characteristics

Timing Requirements (V

CC

= 3.0 to 5.5 V, V

SS

= 0 V, and Ta = T opr

, unless otherwise noted)

Table 5.14

Flash Memory CPU Rewrite Mode Timing

Symbol t cR t su(S-R) t h(R-S) t su(A-R) t h(R-A) t w(R) t cW t su(S-W) t h(W-S) t su(A-W) t h(W-A) t w(W)

Characteristics

Read cycle time

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

Write cycle time

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

100

200

0

30

Min.

Value

Max.

200

200

0

200

0

0

30

50

Unit ns ns ns ns ns ns ns ns ns ns ns ns

Read cycle

Chip select

Address

RD

Write cycle

Chip select

Address

WR t

su(S-R) t

su(A-R) t

su(S-W) t

su(A-W)

Figure 5.5

Flash Memory CPU Rewrite Mode Timing

t

cR t

w(R) t

cW t

w(W) t

h(R-S) t

h(R-A) t

h(W-S) t

h(W-A)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 80 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 5 V

Table 5.15

Electrical Characteristics (1/3)

(V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, T a

= T opr

, and f

(CPU)

= 64 MHz, unless otherwise noted)

Symbol

V

OH

V

OL

High level output voltage

Low level output voltage

Characteristic

Measurement condition

Min.

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

I

OH

= -5 mA V

CC

- 2.0

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

I

OH

= -200 µA V

CC

- 0.3

Value

Typ. Max.

V

V

CC

CC

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

I

I

OL

OL

= 5 mA

= 200 µA

2.0

0.45

Unit

V

V

V

V

Note:

1.

Ports P16 to P19 are available in the 176-pin package only.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 81 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 5 V

Table 5.16

Electrical Characteristics (2/3)

(V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, T a

= T opr

, and f

(CPU)

= 64 MHz, unless otherwise noted)

Symbol Characteristic

Measurement condition

Value

Min. Typ. Max.

Unit

V

T+

- V

T-

Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS10,

CLK0 to CLK10, RXD0 to RXD10,

SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,

SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7,

IIO1_0 to IIO1_7, UD0A, UD0B, UD1A,

UD1B, ISCLK2, ISRXD2, IEIN, CAN0IN,

CAN0WU

RESET

0.2

0.2

1.0

V

1.8

V

I

I

IH

IL

R

PULLUP

High level input current

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

Low level input current

Pull-up resistor

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P13_0 to P13_7, P14_1,

P14_3 to P14_7, P15_0 to P15_7,

P17_4 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

Rf

XIN

Feedback resistor

XIN

Rf

XCIN

Feedback resistor

XCIN

V

I

= 5 V

V

I

= 0 V

V

I

= 0 V

5.0

µA

-5.0

µA

30 50 170 k

Ω

1.5

15

M

Ω

M

Ω

Note:

1.

Ports P16 to P19 are available in the 176-pin package only.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 82 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 5 V

Table 5.17

Electrical Characteristics (3/3)

(V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Symbol

I

CC

Characterist ic

Measurement condition

Power supply current

In single-chip mode, output pins are left open and others are connected to V

SS f

(CPU)

= 64 MHz, f

(BCLK)

= 32 MHz, f

(XIN)

= 8 MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO

XIN-XOUT

Drive power:

XCIN-XCOUT

Drive power: low f

(CPU)

= f

SO(PLL)

/24 MHz,

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO f

(CPU)

= f

(BCLK)

= f

(XIN)

/256 MHz, f

(XIN)

= 8 MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO f

(CPU)

= f

(BCLK)

= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown f

(CPU)

= f

(BCLK)

= f

(OCO)

/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown f

(CPU)

= f

(BCLK)

= f

(XIN)

/256 MHz, f

(XIN)

= 8 MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO,

T a

= 25°C, Wait mode f

(CPU)

= f

(BCLK)

= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

T a

= 25°C, Wait mode f

(CPU)

= f

(BCLK)

= f

(OCO)

/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

T a

= 25°C, Wait mode

Stopped: all clocks,

Main regulator: shutdown,

T a

= 25°C

Value

Min. Typ. Max.

45

12

1.2

220

230

960 1600 µA

8

10 150 µA

5

Unit

60 mA mA mA

µA

µA

140 µA

70 µA

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 83 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 5 V

Table 5.18

A/D Conversion Characteristics (V

CC

= AV

CC

= V

REF

= 4.2 to 5.5 V, V

SS

= AV

SS

= 0 V,

T a

= T opr

, and f

(BCLK)

= 32 MHz, unless otherwise noted)

Symbol

INL

DNL

R

LADDER t

CONV t

CONV t

SAMP

V

IA

φ

AD

R

PU(AST)

R

PD(AST)

Characteristic Measurement condition

Value

Min.

Typ.

Max.

Resolution

Absolute error

Integral non-linearity error

V

REF

= V

CC

V

V

REF

REF

= V

= V

CC

CC

= 5 V

= 5 V

AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1

External op-amp connection mode

AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1

External op-amp connection mode

Differential non-linearity error

Offset error

Gain error

Resistor ladder

Conversion time

(10 bits)

Conversion time

(8 bits)

Sampling time

V

REF

= V

CC

φ

AD

= 16 MHz, with sample and hold function

φ

AD

= 16 MHz, without sample and hold function

φ

AD

= 16 MHz, with sample and hold function

φ

AD

= 16 MHz, without sample and hold function

φ

AD

= 16 MHz

Analog input voltage

4

2.06

3.69

1.75

3.06

0.188

0

10

±3

±7

±3

±7

±1

±3

Unit

Bits

LSB

LSB

LSB

LSB

LSB

LSB

±3 LSB

20 k

Ω

µs

µs

µs

µs

µs

Operating clock frequency without sample and hold function with sample and hold function

0.25

1

V

REF

V

16 MHz

16 MHz

Pull-up resistor for opencircuit detection

Pull-down resistor for open-circuit detection

5

5

10

10

15

15 k k

Ω

Ω

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 84 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 5 V

Table 5.19

D/A Conversion Characteristics (V

CC

= AV

CC and T a

= T opr

, unless otherwise noted)

= V

REF

= 4.2 to 5.5 V, V

SS

= AV

SS

= 0 V,

Symbol t

S

R

O

I

VREF

Characteristic

Resolution

Absolute precision

Settling time

Output resistance

Reference input current

Measurement condition

(1)

Value

Min.

Typ.

Max.

Unit

8 Bits

1.0

%

4 10

3 µs

20 k

Ω

1.5

mA

Note:

1.

One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (V

REF

disconnected), I

VREF

is supplied.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 85 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.20

External Clock Input

Symbol tc

(X) t w(XH) t w(XL) tr

(X) tf

(X) tw / tc

Characteristic

External clock input period

External clock input high level pulse width

External clock input low level pulse width

External clock input rise time

External clock input fall time

External clock input duty

Min.

Value

Max.

62.5

250

25

25

5

40

5

60

Unit ns ns ns ns ns

%

Table 5.21

External Bus Timing

Symbol tsu

(D-R) th

(R-D) tdis

(R-D)

Characteristic

Data setup time for read

Data hold time after read

Data disable time after read

Min.

40

0

Value

Max.

0.5 × t c(Base)

+ 10

Unit ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 86 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.22

Timer A Input (Counting input in event counter mode)

Symbol tc

(TA) tw

(TAH) tw

(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

Value

Max.

200

80

80

Unit ns ns ns

Table 5.23

Timer A Input (Gating input in timer mode)

Symbol tc

(TA) tw

(TAH) tw

(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

400

180

180

Value

Max.

Table 5.24

Timer A Input (External trigger input in one-shot timer mode)

Symbol tc

(TA) tw

(TAH) tw

(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

Value

Max.

200

80

80

Unit ns ns ns

Unit ns ns ns

Table 5.25

Timer A Input (External trigger input in pulse-width modulation mode)

Symbol Characteristic

Min.

Value

Max.

tw

(TAH) tw

(TAL)

TAiIN input high level pulse width

TAiIN input low level pulse width

80

80

Unit ns ns

Table 5.26

Timer A Input (Increment/decrement count switching input in event counter mode)

Symbol Characteristic

TAiOUT input clock cycle time

Min.

Value

Max.

2000

Unit ns tc

(UP) tw

(UPH) tw

(UPL) tsu

(UP-TIN) th

(TIN-UP)

TAiOUT input high level pulse width

TAiOUT input low level pulse width

TAiOUT input setup time

TAiOUT input hold time

1000

1000

400

400 ns ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 87 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.27

Timer B Input (Counting input in event counter mode)

Symbol t c(TB) tw

(TBH) tw

(TBL) tc

(TB) tw

(TBH) tw

(TBL)

Characteristic

TBiIN input clock cycle time (one edge counting)

TBiIN input high level pulse width (one edge counting)

TBiIN input low level pulse width (one edge counting)

TBiIN input clock cycle time (both edges counting)

TBiIN input high level pulse width (both edges counting)

TBiIN input low level pulse width (both edges counting)

Min.

Value

Max.

200

80

80

200

80

80

Unit ns ns ns ns ns ns

Table 5.28

Timer B Input (Pulse period measure mode)

Symbol t c(TB) tw

(TBH) tw

(TBL)

Characteristic

TBiIN input clock cycle time

TBiIN input high level pulse width

TBiIN input low level pulse width

Table 5.29

Timer B Input (Pulse-width measure mode)

Symbol t c(TB) tw

(TBH) tw

(TBL)

Characteristic

TBiIN input clock cycle time

TBiIN input high level pulse width

TBiIN input low level pulse width

Min.

Value

Max.

400

180

180

Unit ns ns ns

Min.

Value

Max.

400

180

180

Unit ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 88 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.30

Serial Interface

Symbol tc

(CK) tw

(CKH) tw

(CKL) tsu

(D-C) th

(C-D)

Characteristic

CLKi input clock cycle time

CLKi input high level pulse width

CLKi input low level pulse width

RXDi input setup time

RXDi input hold time

Min.

Value

Max.

200

80

80

80

90

Unit ns ns ns ns ns

Table 5.31

A/D Trigger Input

tw tw

Symbol

(ADH)

(ADL)

Characteristic

ADTRG input high level pulse width

Hardware trigger input high level pulse width

ADTRG input low level pulse width

Hardware trigger input high level pulse width

Min.

Value

Max.

3

----------

φ

AD

125

Unit ns ns

Table 5.32

External Interrupt INTi Input

tw tw

Symbol

(INH)

(INL)

Characteristic

INTi input high level pulse width

INTi input low level pulse width

Edge sensitive

Level sensitive

Edge sensitive

Level sensitive

Min.

Value

Max.

250 tc

(CPU)

+ 200

250 tc

(CPU)

+ 200

Unit ns ns ns ns

Table 5.33

Intelligent I/O

Symbol Characteristic t c(ISCLK2) t w(ISCLK2H) t w(ISCLK2L) t su(RXD-ISCLK2) t h(ISCLK2-RXD)

ISCLK2 input clock cycle time

ISCLK2 input high level pulse width

ISCLK2 input low level pulse width

ISRXD2 input setup time

ISRXD2 input hold time

Min.

Value

Max.

600

270

270

150

100

Unit ns ns ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 89 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.34

Multi-master I

2

C-bus Interface

t t

Symbol t w(SCLH) t w(SCLL) t r(SCL) t f(SCL) t r(SDA) t f(SDA) t h(SDA-SCL)S su(SCL-SDA)P w(SDAH)P t su(SDA-SCL) t h(SCL-SDA)

Characteristic

MSCL input high level pulse width

MSCL input low level pulse width

MSCL input rise time

MSCL input fall time

MSDA input rise time

MSDA input fall time

MSCL high level hold time after start condition/restart condition

MSCL high level setup time for restart condition/stop condition

MSDA high level pulse width after stop condition

MSDA input setup time

MSDA input hold time

Standard-mode

Min.

Max.

600

600

(1)

(1)

(1)

100

0

1000

300

1000

300

Value

Fast-mode

Min.

Max.

600

2 × t

2 × t

4 × t

600 c(

φ

IIC) c(

φ

IIC) c(

φ

IIC)

100

0

+ 40

+ 40

+ 40

300

300

300

300

Unit ns ns ns ns ns ns ns ns ns ns ns

Note:

1.

The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in the I2CSSCR register: t h(SDA-SCL)S

= SSC ÷ 2 × t c(

φ

IIC)

+ 40 [ns] t su(SCL-SDA)P

= (SSC ÷ 2 + 1) × t c(

φ

IIC)

+ 40 [ns] t w(SDAH)P

= (SSC + 1) × t c(

φ

IIC)

+ 40 [ns]

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 90 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Switching Characteristics (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.35

External Bus Timing (Separate bus)

Symbol Characteristic

Measurement condition t c(Base)

-15

(1) t c(Base)

-15

(1)

Value

1.5 × t c(Base)

-15

(1)

1.5 × t c(Base)

-15

(1)

Max.

Unit tsu

(S-R) th

(R-S) tsu

(A-R) th

(R-A) tw

(R) tsu

(S-W) th

(W-S) tsu

(A-W) th

(W-A) tw

(W) tsu

(D-W) th

(W-D)

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

Data setup time for write

Data hold time after write

Refer to

Figure 5.6

Min.

(1)

(1)

(1)

0 ns ns ns ns ns ns ns ns ns ns ns ns

Note:

1.

The value is calculated by the following formulas based on the base clock cycles (t c(Base)

) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the User’s manual.

t su(S-R)

= t su(A-R)

= Tsu(A-R) × t c(Base)

- 15 [ns] t w(R)

= Tw(R) × t c(Base)

- 10 [ns] t su(S-W)

= t su(A-W)

= Tsu(A-W) × t c(Base)

- 15 [ns] t w(W)

= t su(D-W)

= Tw(W) × t c(Base)

- 10 [ns]

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 91 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Switching Characteristics (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.36

External Bus Timing (Multiplexed bus)

t t

Symbol tsu

(S-ALE) t h(R-S) t su(A-ALE) t h(ALE-A) h(R-A) d(ALE-R) t w(ALE) t dis(R-A) t w(R) t h(W-S) t h(W-A) t d(ALE-W) t w(W) t su(D-W) t h(W-D)

Characteristic

Chip-select setup time for ALE

Chip-select hold time after read

Address setup time for ALE

Address hold time after ALE

Address hold time after read

ALE-read delay time

ALE pulse width

Address disable time after read

Read pulse width

Chip-select hold time after write

Address hold time after write

ALE-write delay time

Write pulse width

Data setup time for write

Measurement condition

Refer to

Figure 5.6

Min.

(1)

1.5 × t c(Base)

(1)

(1)

(1)

(1)

Value

-15 t c(Base)

- 5

(2)

1.5 × t c(Base)

-15 t c(Base)

- 5

(2)

(1)

1.5 × t c(Base)

-15

1.5 × t c(Base)

-15 t c(Base)

- 5

(2) t t

Max.

c(Base) c(Base)

8

+ 10

+ 10

(2)

(2)

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Data hold time after write 0.5 × t c(Base) ns

Notes:

1.

The value is calculated by the following formulas based on the base clock cycles (t c(Base)

) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the User’s manual.

t su(S-ALE)

= t su(A-ALE)

= t w(ALE)

= (Tsu(A-R) - 1) × t c(Base)

-15 [ns]

(when Tsu(A-R) is greater than 1) t su(S-ALE)

= t su(A-ALE)

= t w(ALE)

= 0.5 × t c(Base)

-15 [ns] (when Tsu(A-R) is 1) t w(R)

= Tw(R) × t c(Base)

-10 [ns] t w(W)

= t su(D-W)

= Tw(W) × t c(Base)

-10 [ns]

2.

When Tsu(A-R) is greater than 1 or Tsu(A-W) is greater than 1. Change “t c(Base)

” to “0.5 × t c(Base)

” when Tsu(A-R) is 1 or Tsu(A-W) is 1.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 92 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Switching Characteristics (V

CC

= 4.2 to 5.5 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 5 V

Table 5.37

Serial Interface

Symbol td

(C-Q) th

(C-Q)

Characteristic

TXDi output delay time

TXDi output hold time

Measurement condition

Refer to

Figure 5.6

Min.

Value

Max.

80

0

Unit ns ns

Table 5.38

Intelligent I/O

Symbol Characteristic td

(ISCLK2-TXD)

ISTXD2 output delay time th

(ISCLK2-RXD)

ISTXD2 output hold time

Measurement condition

Refer to

Figure 5.6

Min.

Value

Max.

180

0

Unit ns ns

Table 5.39

Multi-master I

2

C-bus Interface (Standard-mode)

Symbol Characteristic

Measurement condition t f(SCL) t f(SDA)

MSCL output fall time

MSDA output fall time t d(SDA-SCL)S

MSCL output delay time after start condition/restart condition t d(SCL-SDA)P

Restart condition/stop condition output delay time after MSCL becomes high t d(SCL-SDA)

MSDA output delay time

Refer to

Figure 5.6

Min.

2

2

Value

Max.

ns ns

20 × t c(

φ

IIC)

- 120 52 × t c(

φ

IIC)

- 40 ns

20 × t

2 × t c(

φ

IIC) c(

φ

IIC)

+ 40 52 × t

+ 40 3 × t c(

φ

IIC) c(

φ

IIC)

+ 120 ns

+ 120

Unit ns

Table 5.40

Multi-master I

2

C-bus Interface (Fast-mode)

Symbol Characteristic t f(SCL) t f(SDA)

MSCL output fall time

MSDA output fall time t d(SDA-SCL)S

MSCL output delay time after start condition/restart condition t d(SCL-SDA)P

Restart condition/stop condition output delay time after MSCL becomes high t d(SCL-SDA)

MSDA output delay time

Measurement condition

Refer to

Figure 5.6

10 × t

10 × t

Min.

2

2

(1)

(1) c(

φ

IIC) c(

φ

IIC)

Value

- 120 26 × t

+ 40 26 × t

Max.

c(

φ

IIC) c(

φ

IIC)

- 40

Unit ns ns ns

+ 120 ns

2 × t c(

φ

IIC)

+ 40 3 × t c(

φ

IIC)

+ 120 ns

Note:

1.

External circuits are required to satisfy the I

2

C-bus specification.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 93 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Table 5.41

Electrical Characteristics (1/3) (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, T a

= T opr

, and f

(CPU)

= 64 MHz, unless otherwise noted)

= 3.3 V

Symbol Characteristic

Measurement condition

Min.

Value

Typ. Max.

Unit

V

OH

V

OL

High level output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

Low level output voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_7, P15_0 to P15_7,

P16_0 to P16_7, P17_0 to P17_7,

P18_0 to P18_7, P19_0 to P19_7

(1)

I

OH

= -1 mA V

CC

- 0.6

I

OL

= 1 mA

V

CC

V

0.5

V

Note:

1.

Ports P16 to P19 are available in the 176-pin package only.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 94 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Table 5.42

Electrical Characteristics (2/3) (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, T a

= T opr

, and f

(CPU)

= 64 MHz, unless otherwise noted)

= 3.3 V

Symbol Characteristic

Measurement condition

Value

Min.

Typ. Max.

Unit

I

I

V

R

T+

IH

IL

Rf

Rf

- V

T-

PULLUP

XIN

XCIN

Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS10,

CLK0 to CLK10, RXD0 to RXD10,

SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,

SRXD0 to SRXD6, ADTRG,

IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,

UD0B, UD1A, UD1B, ISCLK2, ISRXD2,

IEIN, CAN0IN, CAN0WU

RESET

High level input current

Low level input current

Pull-up resistor

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_7,

P15_0 to P15_7, P16_0 to P16_7,

P17_0 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P13_0 to P13_7, P14_1,

P14_3 to P14_7, P15_0 to P15_7,

P17_4 to P17_7, P18_0 to P18_7,

P19_0 to P19_7

(1)

XIN Feedback resistor

Feedback resistor

XCIN

Note:

1.

Ports P16 to P19 are available in the 176-pin package only.

V

I

= 3.3 V

V

I

= 0 V

V

I

= 0 V

0.2

0.2

1.0

1.8

V

V

4.0

µA

-4.0

µA

50 100 500 k

Ω

3

25

M

Ω

M

Ω

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 95 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Table 5.43

Electrical Characteristics (3/3)

(V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Symbol

Characte ristic

I

CC

Power supply current

Measurement condition

In single-chip mode, output pins are left open and others are connected to V

SS

XIN-XOUT

Drive power: low f

(CPU)

= f

SO(PLL)

/24 MHz,

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO

XCIN-XCOUT

Drive power: low f

(CPU)

= 64 MHz, f

(BCLK)

= 32 MHz, f

(XIN)

= 8 MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO f

(CPU)

= f

(BCLK)

= f

(XIN)

/256 MHz, f

(XIN)

= 8 MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO f

(CPU)

= f

(BCLK)

= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown f

(CPU)

= f

(BCLK)

= f

(OCO)

/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown f

(CPU)

= f

(BCLK)

= f

(XIN)

/256 MHz, f

(XIN)

= 8 MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO,

T a

= 25°C, Wait mode f

(CPU)

= f

(BCLK)

= 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

T a

= 25°C, Wait mode f

(CPU)

= f

(BCLK)

= f

(OCO)

/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

T a

= 25°C, Wait mode

Stopped: all clocks,

Main regulator: shutdown,

T a

= 25°C

Value

Min. Typ. Max.

Unit

40

9

670

180

190

500 900 µA

8

10 150 µA

5

55 mA

140 µA

70 mA

µA

µA

µA

µA

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 96 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Table 5.44

A/D Conversion Characteristics (V

CC

= AV

CC

= V

REF

= 3.0 to 3.6 V, V

SS

= AV

SS

= 0 V,

T a

= T opr

, and f

(BCLK)

= 32 MHz, unless otherwise noted)

Symbol

INL

DNL

Characteristic

Resolution

Absolute error

Integral non-linearity error

Measurement condition

V

REF

= V

CC

V

REF

= V

CC

= 3.3 V AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1

External op-amp connection mode

V

REF

= V

CC

= 3.3 V AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1

External op-amp connection mode

V

REF

= V

CC

= 3.3 V

Value

Min.

Typ.

Max.

Unit

10 Bits

±5 LSB

±7 LSB

±5 LSB

±7 LSB

±1 LSB

R

LADDER t

CONV t

CONV

Differential nonlinearity error

Offset error

Gain error

Resistor ladder

Conversion time

(10 bits)

Conversion time

(8 bits)

Sampling time

V

REF

= V

CC

φ

AD

= 10 MHz, with sample and hold function

φ

AD

= 10 MHz, with sample and hold function

φ

AD

= 10 MHz

4

3.3

2.8

0.3

±3 LSB

±3 LSB

20 k

Ω

µs

µs t

SAMP

V

IA

φ

AD

Analog input voltage

Operating clock frequency without sample and hold function with sample and hold function

0

0.25

1

µs

V

REF

V

10 MHz

10 MHz

R

PU(AST)

R

PD(AST)

Pull-up resistor for open-circuit detection

Pull-down resistor for open-circuit detection

5

5

10

10

15

15 k

Ω k

Ω

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 97 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Table 5.45

D/A Conversion Characteristics (V

CC

= AV

CC and T a

= T opr

, unless otherwise noted)

= V

REF

= 3.0 to 3.6 V, V

SS

= AV

SS

= 0 V,

Measurement condition

Symbol t

S

R

O

I

VREF

Characteristic

Resolution

Absolute precision

Settling time

Output resistance

Reference input current

(1)

Value

Min.

Typ.

Max.

8

1.0

3

4 10

Unit

20

Bits

%

µs k

Ω

1.0

mA

Note:

1.

One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The resistor ladder for A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (V

REF

disconnected), I

VREF

is supplied.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 98 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 3.3 V

Table 5.46

External Clock Input

Symbol tc

(X) t w(XH) t w(XL) t r(X) tf

(X) tw / tc

Characteristic

External clock input period

External clock input high level pulse width

External clock input low level pulse width

External clock input rise time

External clock input fall time

External clock input duty

Min.

Value

Max.

62.5

250

25

25

5

5

40 60

Unit ns ns ns ns ns

%

Table 5.47

External Bus Timing

Symbol t su(D-R) t h(R-D) t dis(R-D)

Characteristic

Data setup time for read

Data hold time after read

Data disable time after read

Min.

40

0

Value

Max.

0.5 × t c(Base)

+ 10

Unit ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 99 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 3.3 V

Table 5.48

Timer A Input (Counting input in event counter mode)

Symbol t c(TA) t w(TAH) t w(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

Value

Max.

200

80

80

Unit ns ns ns

Table 5.49

Timer A Input (Gating input in timer mode)

Symbol t c(TA) t w(TAH) t w(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

400

180

180

Value

Max.

Table 5.50

Timer A Input (External trigger input in one-shot timer mode)

Symbol t c(TA) t w(TAH) t w(TAL)

Characteristic

TAiIN input clock cycle time

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

Value

Max.

200

80

80

Unit ns ns ns

Unit ns ns ns

Table 5.51

Timer A Input (External trigger input in pulse-width modulation mode)

t

Symbol w(TAH) tw

(TAL)

Characteristic

TAiIN input high level pulse width

TAiIN input low level pulse width

Min.

Value

Max.

80

80

Unit ns ns

Table 5.52

Timer A Input (Increment/decrement count switching input in event counter mode)

Symbol Characteristic

Min.

Value

Max.

Unit t c(UP) t w(UPH) t w(UPL) t su(UP-TIN) t h(TIN-UP)

TAiOUT input clock cycle time

TAiOUT input high level pulse width

TAiOUT input low level pulse width

TAiOUT input setup time

TAiOUT input hold time

2000

1000

1000

400

400 ns ns ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 100 of 113

R32C/117A Group

Table 5.54

Timer B Input (Pulse period measure mode)

Symbol t c(TB) t w(TBH) t w(TBL)

Characteristic

TBiIN input clock cycle time

TBiIN input high level pulse width

TBiIN input low level pulse width

5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 3.3 V

Table 5.53

Timer B Input (Counting input in event counter mode)

Symbol t c(TB) t w(TBH) t w(TBL) t c(TB) t w(TBH) t w(TBL)

Characteristic

TBiIN input clock cycle time (one edge counting)

TBiIN input high level pulse width (one edge counting)

TBiIN input low level pulse width (one edge counting)

TBiIN input clock cycle time (both edges counting)

TBiIN input high level pulse width (both edges counting)

TBiIN input low level pulse width (both edges counting)

Min.

Value

Max.

200

80

80

200

80

80

Unit ns ns ns ns ns ns

Min.

Value

Max.

400

180

180

Unit ns ns ns

Table 5.55

Timer B Input (Pulse-width measure mode)

Symbol t c(TB) t w(TBH) t w(TBL)

Characteristic

TBiIN input clock cycle time

TBiIN input high level pulse width

TBiIN input low level pulse width

Min.

Value

Max.

400

180

180

Unit ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 101 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 3.3 V

Table 5.56

Serial Interface

Symbol t c(CK) t w(CKH) t w(CKL) t su(D-C) t h(C-D)

Characteristic

CLKi input clock cycle time

CLKi input high level pulse width

CLKi input low level pulse width

RXDi input setup time

RXDi input hold time

Min.

Value

Max.

200

80

80

80

90

Unit ns ns ns ns ns

Table 5.57

A/D Trigger Input

t t

Symbol w(ADH) w(ADL)

Characteristic

ADTRG input high level pulse width

Hardware trigger input high level pulse width

ADTRG input low level pulse width

Hardware trigger input high level pulse width

Min.

Value

Max.

3

----------

φ

AD

125

Unit ns ns

Table 5.58

External Interrupt INTi Input

Characteristic Symbol t w(INH) tw

(INL)

INTi input low level pulse width

Level sensitive

Edge sensitive

Level sensitive

Min.

Value

250

Max.

tc

(CPU)

+ 200

250 tc

(CPU)

+ 200

Unit ns ns ns ns

Table 5.59

Intelligent I/O

Symbol Characteristic tc

(ISCLK2)

ISCLK2 input clock cycle time tw

(ISCLK2H) tw

(ISCLK2L)

ISCLK2 input high level pulse width

ISCLK2 input low level pulse width tsu

(RXD-ISCLK2)

ISRXD2 input setup time th

(ISCLK2-RXD)

ISRXD2 input hold time

Min.

Value

Max.

600

270

270

150

100

Unit ns ns ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 102 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

Timing Requirements (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

= 3.3 V

Table 5.60

Multi-master I

2

C-bus Interface

t t t t t t t t t

Symbol w(SCLH) w(SCLL) r(SCL) f(SCL) r(SDA) f(SDA) h(SDA-SCL)S su(SCL-SDA)P w(SDAH)P

Characteristic

MSCL input high level pulse width

MSCL input low level pulse width

MSCL input rise time

MSCL input fall time

MSDA input rise time

MSDA input fall time

MSCL high level hold time after start condition/restart condition

MSCL high level setup time for restart condition/stop condition

MSDA high level pulse width after stop condition

MSDA input setup time

MSDA input hold time

Standard-mode

Min.

Max.

600

600

(1)

(1)

(1)

1000

300

1000

300

Value

2 × t

2 × t

4 × t

Fast-mode

Min.

Max.

600

600 c(

φ

IIC) c(

φ

IIC) c(

φ

IIC)

+ 40

+ 40

+ 40

300

300

300

300

Unit ns ns ns t su(SDA-SCL) t h(SCL-SDA)

100

0

100

0 ns ns

Note:

1.

The value is calculated by the following formulas based on a value SSC set by bits SSC4 to SSC0 in the I2CSSCR register: t h(SDA-SCL)S

= SSC ÷ 2 × t c(

φ

IIC)

+ 40 [ns] t su(SCL-SDA)P

= (SSC ÷ 2 + 1) × t c(

φ

IIC)

+ 40 [ns] t w(SDAH)P

= (SSC + 1) × t c(

φ

IIC)

+ 40 [ns] ns ns ns ns ns ns

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 103 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Switching Characteristics (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Table 5.61

External Bus Timing (Separate bus)

Symbol t su(S-R) t h(R-S) t su(A-R) t h(R-A) t w(R) t su(S-W) t h(W-S) t su(A-W) t h(W-A) t w(W) t su(D-W) t h(W-D)

Characteristic

Chip-select setup time for read

Chip-select hold time after read

Address setup time for read

Address hold time after read

Read pulse width

Chip-select setup time for write

Chip-select hold time after write

Address setup time for write

Address hold time after write

Write pulse width

Data setup time for write

Data hold time after write

Measurement condition

Refer to

Figure 5.6

Min.

(1) t c(Base)

(1)

- 15 t c(Base)

- 15

(1)

(1)

1.5 × t c(Base)

(1)

Value

- 15

1.5 × t c(Base)

- 15

(1)

(1)

0

Max.

Unit ns ns ns ns ns ns ns ns ns ns ns ns

Note:

1.

The value is calculated by the following formulas based on the base clock cycles (t c(Base)

) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the User’s manual.

t su(S-R)

= t su(A-R)

= Tsu(A-R) × t c(Base)

- 15 [ns] t w(R)

= Tw(R) × t c(Base)

- 10 [ns] t su(S-W)

= t su(A-W)

= Tsu(A-W) × t c(Base)

- 15 [ns] t w(W)

= t su(D-W)

= Tw(W) × t c(Base)

- 10 [ns]

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 104 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Switching Characteristics (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Table 5.62

External Bus Timing (Multiplexed bus)

Symbol t su(S-ALE) t h(R-S) t su(A-ALE) t h(ALE-A) t h(R-A) t d(ALE-R) tw

(ALE) t dis(R-A) t w(R) t h(W-S) t h(W-A) t d(ALE-W) t w(W) t su(D-W) t h(W-D)

Characteristic

Chip-select setup time for ALE

Chip-select hold time after read

Address setup time for ALE

Address hold time after ALE

Address hold time after read

ALE-read delay time

ALE pulse width

Address disable time after read

Read pulse width

Chip-select hold time after write

Address hold time after write

ALE-write delay time

Write pulse width

Data setup time for write

Measurement condition

Refer to

Figure 5.6

1.5 × t

Min.

(1)

1.5 × t c(Base) t

(1)

- 15 t c(Base)

- 5

(2) c(Base) c(Base)

(1)

(1)

1.5 × t c(Base)

- 15

1.5 × t c(Base)

- 15 t c(Base)

- 5

(2)

(1)

(1)

- 5

(2)

Value

- 15 t t

Max.

c(Base)

8 c(Base)

+ 10

+ 10

(2)

(2)

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Data hold time after write 0.5 × t c(Base) ns

Notes:

1.

The value is calculated by the following formulas based on the base clock cycles (t c(Base)

) and respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the calculation results in a negative value, modify the value to be set. For the details of how to set values, refer to the User’s manual.

t su(S-ALE)

= t su(A-ALE)

= (Tsu(A-R) - 1) × t c(Base)

-15 [ns] (when Tsu(A-R) is greater than 1) t su(S-ALE)

= t su(A-ALE)

= 0.5 × t c(Base)

-15 [ns] (when Tsu(A-R) is 1) t w(ALE)

= (Tsu(A-R) - 1) × t c(Base)

- 20 [ns] (when Tsu(A-R) is greater than 1) t w(ALE)

= 0.5 × t c(Base)

- 20 [ns] (when Tsu(A-R) is 1) t w(R)

= Tw(R) × t c(Base)

-10 [ns] t w(W)

= t su(D-W)

= Tw(W) × t c(Base)

-10 [ns]

2.

When Tsu(A-R) is greater than 1 or Tsu(A-W) is greater than 1. Change “t c(Base)

” to “0.5 × t c(Base)

” when Tsu(A-R) is 1 or Tsu(A-W) is 1.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 105 of 113

R32C/117A Group 5. Electrical Characteristics

V

CC

= 3.3 V

Switching Characteristics (V

CC

= 3.0 to 3.6 V, V

SS

= 0 V, and T a

= T opr

, unless otherwise noted)

Table 5.63

Serial Interface

Symbol td

(C-Q) th

(C-Q)

Characteristic

TXDi output delay time

TXDi output hold time

Measurement condition

Refer to

Figure 5.6

Min.

Value

Max.

80

0

Unit ns ns

Table 5.64

Intelligent I/O

Symbol Characteristic td

(ISCLK2-TXD)

ISTXD2 output delay time th

(ISCLK2-RXD)

ISTXD2 output hold time

Measurement condition

Refer to

Figure 5.6

Min.

Value

Max.

180

0

Unit ns ns

Table 5.65

Multi-master I

2

C-bus Interface (Standard-mode)

Symbol Characteristic

Measurement condition t f(SCL) t f(SDA)

MSCL output fall time

MSDA output fall time t d(SDA-SCL)S

MSCL output delay time after start condition/restart condition t d(SCL-SDA)P

Restart condition/stop condition output delay time after MSCL becomes high t d(SCL-SDA)

MSDA output delay time

Refer to

Figure 5.6

Min.

2

2

Value

Max.

Unit ns ns

20 × t c(

φ

IIC)

- 120 52 × t c(

φ

IIC)

- 40 ns

20 × t

2 ×t c(

φ

IIC)

+ 40 52 × t c(

φ

IIC)

+ 40 3 × t c(

φ

IIC)

+ 120 ns c(

φ

IIC)

+ 120 ns

Table 5.66

Multi-master I

2

C-bus Interface (Fast-mode)

Symbol Characteristic t f(SCL) t f(SDA)

MSCL output fall time

MSDA output fall time t d(SDA-SCL)S

MSCL output delay time after start condition/restart condition t d(SCL-SDA)P

Restart condition/stop condition output delay time after MSCL becomes high t d(SCL-SDA)

MSDA output delay time

Measurement condition

Refer to

Figure 5.6

10 × t

10 × t

Min.

2

2

(1)

(1) c(

φ

IIC) c(

φ

IIC)

Value

- 120 26 × t

+ 40 26 × t

Max.

c(

φ

IIC) c(

φ

IIC)

- 40

Unit ns ns ns

+ 120 ns

2 × t c(

φ

IIC)

+ 40 3 × t c(

φ

IIC)

+ 120 ns

Note:

1.

External circuits are required to satisfy the I

2

C-bus specification.

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 106 of 113

R32C/117A Group

MCU

Pin to be measured

30 pF

Figure 5.6

Switching Characteristic Measurement Circuit

5. Electrical Characteristics

XIN t

c(X) t

r(X) t

w(XH) t

f(X) t

w(XL)

Figure 5.7

External Clock Input Timing

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 107 of 113

R32C/117A Group 5. Electrical Characteristics

External bus timing (Separate bus)

Read cycle

CS0 to CS3 t

su(S-R) t

su(A-R)

A23 to A0, BC0 to BC3 t

cR t

h(R-S) t

h(R-A) t

w(R)

RD

D31 to D0

Write cycle

CS0 to CS3 t

cW t

su(D-R) t

h(R-D) t

su(S-W) t

su(A-W) t

h(W-S) t

h(W-A)

A23 to A0, BC0 to BC3

WR, WR0 to WR3

D31 to D0 t t

w(W)

su(D-W) t

h(W-D)

Measurement conditions

Item

Criterion for input voltage

Criterion for output voltage

V = 4.2 to 5.5 V

CC

2.5 V

0.8 V

2.0 V

0.8 V

V = 3.0 to 3.6 V

CC

1.5 V

0.5 V

2.4 V

0.5 V

Figure 5.8

External Bus Timing (Separate Bus)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 108 of 113

R32C/117A Group 5. Electrical Characteristics

External bus timing (Multiplexed bus)

Read timing t

su(S-ALE)

CS0 to CS3 t

su(A-ALE)

A23 to A8, BC0 to BC3 t

w(ALE)

ALE

A15/D15 to A0/D0,

BC0/D0, BC2/D1 t

h(ALE-A) t

su(A-ALE) t

dis(R-A)

Address t

d(ALE-R) t

cR t

w(R) t

su(D-R)

Data

RD t

su(D-R)

D31 to D8 t

h(R-S) t

h(R-A) t

h(R-D) t

dis(R-D) t

h(R-D)

Write cycle

CS0 to CS3

A23 to A8, BC0 to BC3

ALE

A15/D15 to A0/D0,

BC0/D0, BC2/D1

WR, WR0 to WR3

D31 to D8

Measurement conditions

Item

Criterion for input voltage

Criterion for output voltage t

su(S-ALE) t

su(A-ALE) t

w(ALE) t

su(A-ALE) t

h(ALE-A)

Address t

d(ALE-W)

2.5 V

0.8 V

2.0 V

0.8 V t

cW t

h(W-S) t

h(W-A) t

su(D-W)

Data t

w(W) t

h(W-D) t

su(D-W) t

h(W-D)

1.5 V

0.5 V

2.4 V

0.5 V

Figure 5.9

External Bus Timing (Multiplexed Bus)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 109 of 113

R32C/117A Group 5. Electrical Characteristics

TAiIN input t

w(TAH) t

c(TA) t

w(TAL) t

w(UPH) t

c(UP) t

w(UPL)

TAiOUT input

In event counter mode

TAiOUT input (input for increment/ decrement count switching)

TAiIN input (in falling edge counting) t

su(UP-TIN)

TAiIN input (in rising edge counting) t

w(TBH) t

c(TB) t

w(TBL)

TBiIN input t

w(CKH) t

c(CK) t

w(CKL)

CLKi t

d(C-Q)

TXDi t

su(D-C)

RXDi t

h(C-D) t

w(ADL) t

w(ADH)

ADTRG input t

w(INL) t

w(INH)

INTi input

2 CPU clock cycles +

300 ns or more

2 CPU clock cycles +

300 ns or more

NMI input

Figure 5.10

Timing of Peripheral Functions

t

h(TIN-UP) t

h(C-Q)

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 110 of 113

R32C/117A Group 5. Electrical Characteristics

MSCL

MSDA t

c(SCL) t

r(SCL) t

w(SCLH) t

f(SCL) t

w(SCLL) t

h(SDA-SCL)S t

r(SDA) t

f(SDA) t

w(SDAH)P t

su(SCL-SDA)P

MSCL

MSDA (input) t

d(SDA-SCL)S t

d(SCL-SDA)P t

h(SDA-SCL)S

MSCL

MSDA (output) t

su(SDA-SCL) t

d(SDA-SCL)S t

h(SCL-SDA)

MSCL

MSDA (input) t

d(SCL-SDA)

MSCL

MSDA (output)

Figure 5.11

Timing of Multi-master I

2

C-bus Interface

t

su(SCL-SDA)P t

d(SCL-SDA)P

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 111 of 113

R32C/117A Group

Appendix 1. Package Dimensions

JEITA Package Code

P-LQFP176-24x24-0.50

RENESAS Code Previous Code

PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV

MASS[Typ.]

1.8g

H

D

*1

D

132 89

133 88

176

S

1

Z

D

Index mark e y S

44

45

F

*3 b p x M

Appendix 1. Package Dimensions b p b

1

Terminal cross section

NOTE)

DO NOT INCLUDE MOLD FLASH.

"*3" DOES NOT

INCLUDE TRIM OFFSET.

Detail F

L

L

1

H

D

H

E

A

A

1 b p b

1 c c

1

θ

Reference

Symbol

Dimension in Millimeters

Min Nom Max

D

E

A

2

23.9

24.0

24.1

23.9

24.0

24.1

1.4

25.8

26.0

26.2

25.8

26.0

26.2

0.05

0.1

0.09 0.145

0.125

0.15

0.15

0.20

0.25

0.18

1.7

0.20

8° e x y

Z

Z

L

L

D

E

1

0.5

0.08

0.10

1.25

1.25

0.35

0.5

0.65

1.0

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 112 of 113

R32C/117A Group

JEITA Package Code

P-LQFP144-20x20-0.50

RENESAS Code

PLQP0144KA-A

Previous Code

144P6Q-A / FP-144L / FP-144LV

MASS[Typ.]

1.2g

H

D

*1

D

109

108

73

72 b p b

1

Terminal cross section

S

144

Z

D

1

Index mark e y S

36

37

F

*3 b p x Detail F

L

1

L

Appendix 1. Package Dimensions

NOTE)

1.

DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

2.

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

e x y

Z

D

Z

E

L

L

1

Reference

Symbol

D

E

A

1 b p b

1 c

A

2

H

D

H

E

A c

1

Dimension in Millimeters

Min

19.9

19.9

21.8

21.8

0.05

0.17

0.09

Nom

20.0

20.0

1.4

22.0

22.0

0.1

0.22

0.20

0.145

0.125

Max

20.1

20.1

22.2

22.2

1.7

0.15

0.27

0.20

0° 8°

0.35

0.5

1.25

1.25

0.5

1.0

0.08

0.10

0.65

REJ03B0298-0100 Rev.1.00

Jul 16, 2010

Page 113 of 113

Revision History R32C/117A Group Datasheet

Rev.

0.50

1.00

Date

Mar 05, 2010

Jul 16, 2010

Page

Description

Summary

Initial release

Second edition released

This manual in general

• Applied new Renesas templates and formats to the manual

• Changed company name to “Renesas Electronics Corporation” and changed related descriptions due to business merger of Renesas

Technology Corporation and NEC Electronics Corporation (under

Chapters 1 and 5)

• Modified expressions “version N”, “version D”, and “version P” to “N version”, “D version”, and “P version”, respectively (under Chapters 1 and 5)

3, 5

6

8

20

Chapter 1. Overview

• Specified current consumptions in Tables 1.2 and 1.4; Deleted Note 1

• Corrected package codes in Table 1.5

• Deleted Note 1 from Figure 1.2

35, 38 • Changed register name “Group i Timer Measurement Prescaler

Register” in Tables 4.6 and 4.9 to “Group i Time Measurement

Prescaler Register”

40 • Modified expression “XY Control Register” in Table 4.11 to “X-Y

Control Register”

42

• Modified expression “fC” in Table 1.15 to “low speed clock”

Chapter 4. SFRs

44

55

• Changed register name “UART2 Transmission/Receive Mode

Register” in Table 4.13 to “UART2 Transmit/Receive Mode Register”;

Changed hexadecimal format of reset values for registers TABSR,

ONSF, and TRGSR to binary

• Modified reset value “X00X X000b” for AD0CON2 register in Table

4.15

to “XX0X X000b”

• Changed register name “External Interrupt Source Select Register i” in

Table 4.26

to “External Interrupt Request Source Select Register i”

70 • Modified register names “CAN0 Reception Error Count Register” and

“CAN0 Transmission Error Count Register” in Table 4.41 to “CAN0

Receive Error Count Register” and “CAN0 Transmit Error Count

Register”, respectively

Chapter 5. Electrical Characteristics

• Initially added —

Appendix 1. Package Dimensions

112, 113 • Added a seating plane to the drawing of package dimension

All trademarks and registered trademarks are the property of their respective owners.

A- 1

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed.

After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.

The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas

Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas

Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.

The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically

"Specific": designed for life support.

Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.

(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

SALES OFFICES

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.

2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.

Tel: +1-408-588-6000, Fax: +1-408-588-6130

Renesas Electronics Canada Limited

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Tel: +1-905-898-5441, Fax: +1-905-898-3220

Renesas Electronics Europe Limited

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Tel: +44-1628-585-100, Fax: +44-1628-585-900

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, Germany

Tel: +49-211-65030, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.

7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China

Tel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.

Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China

Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898

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Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong

Tel: +852-2886-9318, Fax: +852 2886-9022/9044

Renesas Electronics Taiwan Co., Ltd.

7F, No. 363 Fu Shing North Road Taipei, Taiwan

Tel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.

1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632

Tel: +65-6213-0200, Fax: +65-6278-8001

Renesas Electronics Malaysia Sdn.Bhd.

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics Korea Co., Ltd.

11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea

Tel: +82-2-558-3737, Fax: +82-2-558-5141 http://www.renesas.com

© 2010 Renesas Electronics Corporation. All rights reserved.

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