Application Note AN491

IoT Subsystem for Cortex-M

Non-confidential

DAI0491A

AN491

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i

IoT Subsystem for Cortex-M

Copyright © 2015 ARM. All rights reserved.

Release Information

The following changes have been made to this SMM.

Change History

Date

25 September 2015

Issue

1

Confidentiality

Non-confidential

Change

First release

Proprietary Notice

Words and logos marked with ™ or

® are registered trademarks or trademarks of ARM in the EU and other countries except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product .

Web Address

http://www.arm.com

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Contents

IoT Subsystem for Cortex-M

1 Conventions and Feedback ....................................................................................1-1

2 Preface ......................................................................................................................2-1

2.1

References ..........................................................................................................2-1

2.2

Terms and abbreviations .....................................................................................2-1

2.3

Encryption key .....................................................................................................2-2

3 Overview ...................................................................................................................3-1

3.2

Detailed memory map .........................................................................................3-3

3.3

3.4

External ZBT Synchronous SRAM (SSRAM1)....................................................3-5

External ZBT Synchronous SRAM (SSRAM2 & SSRAM3) ................................3-5

3.5

3.6

3.7

External PSRAM..................................................................................................3-5

AHB GPIO ...........................................................................................................3-5

SPI (Serial Peripheral Interface)..........................................................................3-5

3.8

3.9

Color LCD parallel interface ................................................................................3-6

Ethernet ...............................................................................................................3-6

3.10

VGA .....................................................................................................................3-6

3.11

Audio I

2

S..............................................................................................................3-7

3.12

Audio Configuration .............................................................................................3-8

3.13

FPGA system control and I/O..............................................................................3-9

4 IO mapping ...............................................................................................................4-1

5 Clocks .......................................................................................................................5-1

6 Interrupt assignments .............................................................................................6-1

7 Serial Communication Controller (SCC)................................................................7-3

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1 Conventions and Feedback

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The following describes the typographical conventions and how to give feedback:

Typographical conventions

The following typographical conventions are used: monospace monospace denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.

denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

monospace italic denotes arguments to commands and functions where the argument is to be replaced by a specific value.

monospace bold denotes language keywords when used outside example code.

italic

highlights important notes, introduces special terminology, denotes internal cross-references, and citations.

bold

highlights interface elements, such as menu names. Denotes signal names.

Also used for emphasis in descriptive lists, where appropriate.

Feedback on this product

If you have any comments and suggestions about this product, contact your supplier and give:

 Your name and company.

 The serial number of the product.

 Details of the release you are using.

 Details of the platform you are using, such as the hardware platform, operating system type and version.

 A small standalone sample of code that reproduces the problem.

 A clear explanation of what you expected to happen, and what actually happened.

 The commands you used, including any command-line options.

 Sample output illustrating the problem.

 The version string of the tools, including the version number and build numbers.

Feedback on documentation

If you have comments on the documentation, e-mail [email protected]

. Give:

 The title.

 The number, DAI0491A.

 If viewing online, the topic names to which your comments apply.

 If viewing a PDF version of a document, the page numbers to which your comments apply.

 A concise explanation of your comments.

ARM also welcomes general suggestions for additions and improvements.

Copyright

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1-1

ARM periodically provides updates and corrections to its documentation on the ARM Information

Center, together with knowledge articles and Frequently Asked Questions (FAQs).

Other information

 ARM Information Center, http://infocenter.arm.com/help/index.jsp

.

 ARM Technical Support Knowledge Articles, http://infocenter.arm.com/help/topic/com.arm.doc.faqs/index.html

.

 ARM Support and Maintenance, http://www.arm.com/support/services/supportmaintenance.php

.

 ARM Glossary, http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-

/index.html

.

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

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2 Preface

This SMM is intended for developers/programmers/users who deploy hardware/software for a purpose.

These topics support the following chapters:

 References on page 2-1.

 Terms and abbreviations on page 2-1.

 Encryption key on page 2-2

2.1

References

 ARMv7-M Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI 0403D)

for Cortex-M products

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0403c/index.html

 ARM

®

Versatile™ Express Cortex

Manual

®

-M Prototyping System (V2M-MPS2)Technical Reference

http://arminfo.emea.arm.com/help/topic/com.arm.doc.100112_0100_03_en/index

.html

 Cortex ®

-M System Design Kit

http://www.arm.com/products/processors/cortex-m/cortex-m-system-designkit.php

 Cortex ®

-M System Design Kit Technical Reference Manual

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0479c/index.html

 ARM

®

PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0194g/

I1005344.html

 Keil ®

MCBSTM32C Evaluation Board Display Board Schematic

http://www.keil.com/mcbstm32c/mcbstm32c-display-board-schematics.pdf



IoT Subsytem for Cortex-M product page

http://www.arm.com/products/internet-of-things-solutions/iot-subsystemfor-cortex-m.php

2.2

Terms and abbreviations

CMSDK

MPS2

FPGA

SMM

ZBT

SRAM

SSRAM

Cortex-M System Design Kit.

Cortex-M Prototyping system, also known as MPS2 (second generation of

Microcontroller prototyping system).

Field programmable gate array.

Soft M9acrocell Model.

Zero bus turnaround

Static random access memory

Synchronous SSRAM

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2-1

2.3

Encryption key

ARM supplies the V2M-MPS2 motherboard with a decryption key programmed into the FPGA.

This key is needed to enable loading of encrypted, prebuilt images. AN491 is supplied as an encrypted image.

Caution

A battery supplies power to the key storage area of the FPGA. Any keys stored in the FPGA may be lost when battery power is lost. If this happens you must return the board to ARM for reprogramming of the key.

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3 Overview

The SMM design is based on the IOT Subsystem for Cortex-M and incorporates a Cortex-M3 processor. Cortex-M System Design Kit (CMSDK) components are used for many of the peripherals.

3.1.1

Overview

MPS2 or MPS2+ Board

AN491 Wrapper

Initialisation

MCC

SPI SPI

IoT Subsystem for Cortex-M CSS

AHB

APB Interface

Core APB Peripherals

UART

Watchdog

Dual Timer

SCC

FLASH

Interface

SRAM

FCACHERAM

SRAM0IF SRAM2IF

SRAM1IF SRAM3IF AHB

DATA

RAM0

DATA

RAM1

SRAM0 SRAM2

SRAM1 SRAM3

Other Peripherals

AHB to ZBT

SRAM 64

ZBT ZBT

AHB Mux

AHB to ZBT

SRAM 32

ZBT

AHB to ZBT

SRAM 32

ZBT

AHB to ext SRAM

PSRAM Ethernet

VGA

(EDK)

FPGA IO regs

Audio

I2S

APB

AHB to

APB

SPI x 2

(master)

SBCon x 2 SCC

Figure 3-1 System Overview

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3-1

3.1.2

IoT Subsystem for Cortex-M diagram

IOT Subsystem for Cortex-M

CSS

DAP

TPIU

SWJ/DP

WIC

S

PIL

TPIU

CM3

I D

APBTARGEXP

(APB4x11)

2,4-8,11-15

….

APB4

AHB2

APB

Bridge

TIMER0/1

AHB lite

32-bit

TARGAPB0

TARG_FLASH0

AHB lite

32-bit

Flash

Cache

AHB lite

128-bit

SRAM

Controller

SRAM

128-bit

AHB lite

32-bit

AHB lite

32-bit

Code MUX

AHB lite

32-bit

AHB2

AHB lite

32-bit

SRAM0

AHB2

SRAM1

MS AHB lite 32-bit

AHB2

SRAM2

MS AHB lite 32-bit

AHB2

SRAM3

SL AHB lite

32-bit

INITCM3DI INITCM3S INITEXP1

Multilayer AHB Bus Matrix

TARG_SRAM0 TARG_SRAM1

INITEXP0

TARG_SRAM2

TARGEXP0

TARG_SRAM3 TARGEXP1

AHB lite

32-bit

AHB lite

32-bit

AHB lite

32-bit

AHB lite

32-bit

SL AHB lite

32-bit

SRAM0IF SRAM1IF SRAM2IF SRAM3IF

Fi

Figure 3-2 IoT Subsystem for Cortex-M Overview

3.1.3

Subsystem version

The IoT subsystem for Cortex-M implementation used in AN491 has been modified to replace its

FLASH memory controller with an SRAM controller for FPGA compatibility.

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3-2

3.2

Detailed memory map

0x40024000

0x40023000

0x40022000

0x40021000

0x40020000

0x4001F000

0x40012000

0x40011000

0x40010000

0x4000F000

0x40008000

0x40006000

Start Address

0x60000000

0x41100000

0x41010000

0x41000000

0x40200000

0x40032000

0x40031000

0x40030000

0x4002F000

0x40029000

0x40028000

0x40025000

0x40024FFF

0x40023FFF

0x40022FFF

0x40021FFF

0x40020FFF

0x4001FFFF

0x4001EFFF

0x40011FFF

End Address Description

0x5FFFFFFF Reserved

0x4113FFFF

0x410FFFFF

0x4100FFFF

VGA Image

Reserved

VGA Console

0x40FFFFFF

0x401FFFFF

0x40031FFF

0x40030FFF

0x4002FFFF

0x4002EFFF

0x40028FFF

0x40027FFF

Comment

512x128x32bit

Ethernet

Reserved

GPIO5

GPIO4 via ahb_to_extmem16

SCC register

Reserved

FPGA System Control & I/O

Reserved

Audio I

2

S

See SCC section

SBCon

SBCon

PL022

PL022

SysCtrl

Reserved

GPIO1

Audio Configuration

Touch for LCD module

SPI for LCD module

SPI connector J21

CMSDK system controller

0x40010FFF

0x40009FFF

0x40008FFF

0x40007FFF

GPIO0

Reserved

Watchdog

Reserved

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0x20800000

0x20400000

0x20020000

0x20018000

0x20010000

0x20008000

0x20000000

Start Address

0x40005000

0x40003000

0x40002000

0x40001000

0x40000000

0x22000000

0x21000000

0x00800000

0x00400000

0x00080000

0x00000000

0x20FFFFFF

0x207FFFFF

0x203FFFFF

0x2001FFFF

0x20017FFF

0x2000FFFF

0x20007FFF

End Address Description

0x40005FFF UART1

0x40004FFF

0x40002FFF

Reserved

Dual timer

0x40001FFF

0x40000FFF

0x3FFFFFFF

0x21FFFFFF

Timer1

Timer0

Reserved

PSRAM

0x1FFFFFFF

0x007FFFFF

0x003FFFFF

0x0007FFFF

Reserved

ZBT2&3

Reserved

SRAM3

SRAM2

SRAM1

SRAM0

Reserved

ZBT1

Reserved

RAM

Comment

User Memory

User Memory

FPGA Block RAM

FPGA Block RAM

FPGA Block RAM

FPGA Block RAM

User Memory

Replaces subsystem FLASH RAM

Table 3-1 Detailed System Memory Map

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3-4

3.3

External ZBT Synchronous SRAM (SSRAM1)

This is interfaced to two external 32-bit ZBT SSRAM in parallel, forming a 64-bit ZBT SSRAM.

This memory is in the processor’s code region.

3.4

External ZBT Synchronous SRAM (SSRAM2 & SSRAM3)

The Fast ZBT SSRAM is set up as two external ZBT SSRAMs, connected to two independent

ZBT interfaces. It is in the processor’s SRAM region.

The ZBT SSRAM is interleaved and available to the user as shown in the table below.

Upper 32-bit ZBT SSRAM3

0x207FFFFC

…

0x2040000C

0x20400004

Lower 32-bit ZBT SSRAM2

0x207FFFF8

…

0x20400008

0x20400000

Table 3-2 32 bit ZBT Memory Map

3.5

External PSRAM

A 16MB 16-bit PSRAM area is available and the memory map allocates the address-range

0x21000000 -0x21FFFFFF. This enables large test programs to be used.

Note: Running code from SRAM region is slower than from CODE region because the internal bus structure is not optimized for running programs from this region.

3.6

AHB GPIO

The SMM uses CMSDK AHB GPIO #0 and #1. GPIO #4 and #5 have been added to increase the number of pins available. See the CMSDK TRM

3.7

SPI (Serial Peripheral Interface)

The SMM implements two PL022 SPI modules:

 General purpose SPI module that connects to the general-purpose SPI connector, J21.

 Color LCD module control.

The Color LCD module control interfaces with an Ampire AM-240320LG 2.4” Touch Panel on the Keil MCBSTM32C display board. (Schematic listed in the reference section).

Self-test provided with the MPS2 board includes example code for the color LCD module control interface.

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3-5

3.8

Color LCD parallel interface

The color LCD module has two interfaces:

 SPI for LCD module used for sending image data to the LCD.

 I 2

C for touch used to transfer data input via the touch screen.

These interfaces are connected to a STMicroelectronics STMPE811QTR Port Expander with

Advanced Touch Screen Controller on the Keil MCBSTM32C display board. (Schematic listed in the reference section).

Self-test provided with the MPS2 includes example code for both of these interfaces.

3.9

Ethernet

The SMM design connects SMSC LAN9220 through AHB to external memory block.

The SMM self-test code includes example code for a simple loopback operation.

3.10

VGA

Address

0x41000000 - 0x4100FFFF

0x41100000 - 0x4113FFFF

Description

Writes to the current location of the cursor.

512x128 image area at the top right of the screen. 0x41100000 is the top left of the area and 0x4113FFFF is the bottom right. HADDR[16:2] =

YYYYYYYXXXXXXXX where X and Y are the horizontal and vertical pixel offset respectively.

Table 3-3 VGA Memory Map

For the image data, each pixel requires one 32 bit word, therefore, a total of 256KB are needed.

The values in the data buffer are packed as 4 bits per-channel in the format 0x00000RGB.

The pixel in the top left hand corner of the display occupies address 0x41100000 with each successive row using an offset of 0x00000400 from the previous row. For example: the left most pixel (LMP) of the 2 nd row is at 0x41100400 and the LMP of the 3 rd row is at 0x41100800.

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3-6

3.11

Audio I

2

S

A simple FIFO interface generates and receives I

2

S audio.

Address

0x40024000

0x40024004

Name

CONTROL

STATUS

Information

Control Register

[31:18] : Reserved

[17] : Audio CODEC reset control (output pin)

[16] : FIFO reset

[15] : Reserved

[14:12] : RX Buffer IRQ Water Level - Default 2

(IRQ triggers when more less 2 word space available)

[11] : Reserved

[10: 8] : TX Buffer IRQ Water Level - Default 2

(IRQ triggers when more than 2 word space available)

[7: 4] : Reserved

[3] : RX Interrupt Enable

[2] : RX Enable

[1] : TX Interrupt Enable

[0] : TX Enable

Status register

[31:6] : Reserved

[5] : RX Buffer Full

[4] : RX Buffer Empty

[3] : TX Buffer Full

[2] : TX Buffer Empty

[1] : RX Buffer Alert (Depends on Water level)

[0] : TX Buffer Alert (Depends on Water level)

0x40024008 ERROR

0x4002400C DIVIDE

0x40024010 TXBUF

Error status register

[31:2] : Reserved

[1] : RX overrun - write 1 to clear

[0] : TX overrun/underrun - write 1 to clear

Divide ratio register (for Left/Right clock)

[31:10] : Reserved

[ 9: 0] LRDIV (Left/Right) Default = 0x80

12.288MHz / 48KHz / 2 (L+R) = 128

Transmit Buffer FIFO Data Register (WO)

[31:16] : Left Channel

[15: 0] : Right Channel

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Address

0x40024014

Name

RXBUF

-

Information

Receive Buffer FIFO Data Register (RO)

[31:16] Left Channel

[15: 0] Right Channel

0x40024018

–

0x400242FC

0x40024300

RESERVED

ITCR

0x40024304

0x40024308

ITIP1

ITOP1

Integration Test Control Register

[31:1] : Reserved

[0] : ITCR

Integration Test Input Register 1

[31:1] : Reserved

[0] : SDIN

Integration Test Output Register 1

[31:4] : Reserved

[3] : IRQOUT

[2] : LRCK

[1] : Reserved

[0] : SDOUT

Table 3-4 Audio I

2

S Memory Map

3.12

Audio Configuration

The SMM implements a simple serial interface (SBCon) to the audio codec.

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3-8

3.13

FPGA system control and I/O

The SMM implements an FPGA system control block.

Address

0x40028000

0x40028004

0x40028008

0x4002800C

0x40028010

0x40028014

0x40028018

0x4002801C

0x40028020

0x40028024

0x4002804C

Name

FPGAIO->LED0

Information

LED connections

[31:2] : Reserved

[1:0] : LED

RESERVED

FPGAIO->BUTTON Buttons

[31:2] : Reserved

[1:0] : Buttons

RESERVED

FPGAIO->CLK1HZ

FPGAIO->CLK100HZ

FPGAIO->COUNTER

1Hz up counter

100Hz up counter

Cycle Up Counter

Increments when 32-bit prescale counter reach zero.

FPGAIO->PRESCALE

FPGAIO->PSCNTR

Bit[31:0] – reload value for prescale counter.

32-bit Prescale counter – current value of the pre-scaler counter.

The Cycle Up Counter increment when the prescale down counter reach 0. The pre-scaler counter is reloaded with PRESCALE after reaching 0.

RESERVED

FPGAIO->MISC Misc control

[31:7] : Reserved

[6] : CLCD_BL_CTRL

[5] : CLCD_RD

[4] : CLCD_RS

[3] : CLCD_RESET

[2] : RESERVED

[1] : SPI_nSS

[0] : CLCD_CS

Table 3-5 System Control and I/O Memory Map

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3-9

4 IO mapping

GPIO0[6]

GPIO0[7]

GPIO0[8]

GPIO0[9]

GPIO0[13]

GPIO0[10]

GPIO0[11]

GPIO0[12]

GPIO0[14]

GPIO1[2]

GPIO

GPIO0[0]

GPIO0[4]

GPIO0[2]

GPIO0[3]

GPIO0[1]

GPIO0[15]

GPIO0[5]

EXP_11

EXP_12

EXP_13

EXP_14

EXP_7

EXP_8

EXP_9

EXP_10

EXP_15

EXP_16

EXP_3

EXP_4

EXP_5

EXP_6

EXP Pin

EXP_0

EXP_1

EXP_2

GPIO4[8]

GPIO4[9]

GPIO1[0]

GPIO1[9]

GPIO1[8]

GPIO1[15]

GPIO1[1]

GPIO1[7]

GPIO1[11]

GPIO1[14]

GPIO1[10]

GPIO1[3]

GPIO1[4]

GPIO1[5]

GPIO4[4]

GPIO4[5]

GPIO4[6]

GPIO4[7]

EXP_28

EXP_29

EXP_30

EXP_31

EXP_32

EXP_33

EXP_34

EXP_24

EXP_25

EXP_26

EXP_27

EXP_17

EXP_18

EXP_19

EXP_20

EXP_21

EXP_22

EXP_23

GPIO4[11]

GPIO4[12]

GPIO4[3]

GPIO4[13]

GPIO4[14]

GPIO4[15]

GPIO5[0]

GPIO5[1]

GPIO5[2]

GPIO5[3]

GPIO1[12]

GPIO1[13]

GPIO4[10]

GPIO4[0]

GPIO4[1]

GPIO4[2]

GPIO1[6]

EXP_46

EXP_47

EXP_48

EXP_49

EXP_50

EXP_51

EXP_42

EXP_43

EXP_44

EXP_45

EXP_35

EXP_36

EXP_37

EXP_38

EXP_39

EXP_40

EXP_41

Table 4-1 I/O Mapping

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5 Clocks

The following table shows the Source Clocks for the system. These clocks are used to derive the clocks in the tables below. These clocks should not be adjusted.

Name

OSCCLK[0]

OSCCLK[1]

OSCCLK[2]

CFGCLK

CS_TCK

SPICFGCLK

Frequency

48MHz

24.576MHz

25MHz

0.5MHz

Determined by debugger

7.5MHz

Table 5-1 Source Clocks

The following table shows the Derived Clocks.

Name

SYSCLK

AUDMCLK

AUDSCLK

DBGCLK

SPICLCD

SPICON

I2CCLCD

I2CAUD

CLK32KI

Frequency

24MHz

12.29MHz

3.07MHz

24MHz

25MHz

25MHz

25MHz

25MHz

32KHz

2

2

750

8

2

2

2

2

2

Division

Factor

1

1

1

1

1

1

1

1

1

Multiplication

Factor

Derived From

OSCCLK[0]

OSCCLK[1]

OSCCLK[1]

OSCCLK[0]

OSCCLK[0]

OSCCLK[0]

OSCCLK[0]

OSCCLK[0]

OSCCLK[0]

Table 5-2 Derived Clocks

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6 Interrupt assignments

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

IRQ22

IRQ23

IRQ24

IRQ25

Interrupt

NMI

IRQ0

IRQ1

IRQ2

IRQ3

Touch Screen

GPIO 0/1 – pin 0

GPIO 0/1 – pin 1

GPIO 0/1 – pin 2

GPIO 0/1 – pin 3

GPIO 0/1 – pin 4

GPIO 0/1 – pin 5

GPIO 0/1 – pin 6

GPIO 0/1 – pin 7

GPIO 0/1 – pin 8

GPIO 0/1 – pin 9

Peripheral

Watchdog / External

Reserved

Reserved

UART 1

Reserved

Reserved

Reserved

GPIO 0 combined interrupt

GPIO 1 combined interrupt

Timer 0

Timer 1

Dual Timer

Reserved

UART overflow

Reserved

Reserved

Handler name in C header

NMI_Handler

UART1_Handler

PORT0_COMB_Handler

PORT1_COMB_Handler

TIMER0_Handler

TIMER1_Handler

DUALTIMER_HANDLER

UARTOVF_Handler

GPIO01P0_Handler

GPIO01P1_Handler

GPIO01P2_Handler

GPIO01P3_Handler

GPIO01P4_Handler

GPIO01P5_Handler

GPIO01P6_Handler

GPIO01P7_Handler

GPIO01P8_Handler

GPIO01P9_Handler

CMSDK/MPS2 usage

Watchdog

UART0 RX

UART0 TX

UART1 RX

UART1 TX

I2S

DMA

GPIO 0 – pin 0

GPIO 0 – pin 1

GPIO 0 – pin 2

GPIO 0 – pin 3

GPIO 0 – pin 4

GPIO 0 – pin 5

GPIO 0 – pin 6

GPIO 0 – pin 7

GPIO 0 – pin 8

GPIO 0 – pin 9

UART2 RX

UART2 TX

GPIO 0 combined interrupt

GPIO 1 combined interrupt

Timer 0

Timer 1

Dual Timer

FPU / SPI #0 and SPI #1

UART overflow

Ethernet

DAI0491A

AN491

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6-1

IRQ26

IRQ27

IRQ28

IRQ29

IRQ30

IRQ31

IRQ32-46

IRQ47

IRQ48

IRQ49-53

IRQ54

IRQ55

GPIO 0/1 – pin 10

GPIO 0/1 – pin 11

GPIO 0/1 – pin 12

GPIO 0/1 – pin 13

GPIO 0/1 – pin 14

GPIO 0/1 – pin 15

Reserved

Ethernet

I2S

Reserved

GPIO 4 combined interrupt

GPIO 5 combined interrupt

GPIO01P10_Handler

GPIO01P11_Handler

GPIO01P12_Handler

GPIO01P13_Handler

GPIO01P14_Handler

GPIO01P15_Handler

GPIO 0 – pin 10

GPIO 0 – pin 11

GPIO 0 – pin 12

GPIO 0 – pin 13

GPIO 0 – pin 14

GPIO 0 – pin 15

Table 6-1 Interrupts

DAI0491A

AN491

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6-2

7 Serial Communication Controller (SCC)

The SMM implements communication between the microcontroller and the FPGA system through an SCC interface.

DAI0491A

AN491

Figure 7-1 Diagram of the SCC Interface

The read-addresses and write-addresses of the SCC interface do not use bits[1:0].

All address words are word-aligned.

Address

0x000

0x004

0x008

0x00C

0x010

0x014

0x018

0x01C

0x020 – 0x09C

0x0A0

0x0A4

Name

CFG_REG0

CFG_REG1

CFG_REG2

CFG_REG3

CFG_REG4

CFG_REG5

CFG_REG6

CFG_REG7

RESERVED

SYS_CFGDATA_RTN

SYS_CFGDATA_OUT

Information

Bits[31:0] Reserved

Bits [31:8] Reserved

Bits [7:0] MCC LEDs: 0 = OFF 1 = ON

Reserved

Bits [31:8] Reserved

Bits [7:0] MCC switches: 0 = OFF 1 = ON

Bits [31:4] Reserved

Bits [3:0] Board Revision

Reserved

Reserved

Reserved

-

32bit DATA [r/w]

32bit DATA [r/w]

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DAI0491A

AN491

Address

0x0A8

0x0AC

0x0AD – 0x0FC

0x100

0x104 – 0xFF4

0xFF8

0xFFC

Name

SYS_CFGCTRL

SYS_CFGSTAT

RESERVED

SCC_DLL

RESERVED

SCC_AID

SCC_ID

Information

Bit[31] : Start (generates interrupt on write to this bit)

Bit[30] : R/W access

Bits[29:26] : Reserved

Bits[25:20] : Function value

Bits[19:12] : Reserved

Bits[11:0] : Device (value of 0/1/2 for supported clocks)

Bit 0 : Complete

-

Bit 1 : Error

DLL lock register

Bits [31:24] DLL LOCK MASK[7:0] - These bits indicate if the DLL locked is masked.

Bits [23:16] DLL LOCK MASK[7:0] - These bits indicate if the DLLs are locked or unlocked.

Bits [15:1] : Reserved

Bit[0] This bit indicates if all enabled DLLs are locked:

-

SCC AID register is read only

Bits[31:24] : FPGA build number

Bits[23:20] : V2M-MPS2 target board revision

1 = (B) V2M-MPS2, 2 = (C) V2M-MPS2+

Bits[19:8] Reserved

Bits[7:0] number of SCC configuration register

SCC ID register is read only

Bits[31:24] : Implementer ID: 0x41 = ARM

Bits[23:20] : Application note IP variant number

(note 1)

Bits[19:16] : IP Architecture: 0x4 =AHB

Bits[11:4] : Primary part number: 491 = AN491

Bits[3:0] : Application note IP revision number

(note 1)

Table 7-1 SCC Register memory map

note 1

The variant and revision numbers relate to the rxpy number. For example for r1p0 processors the 1 would be the variant number and the 0 would be the revision number.

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Non-confidential

7-4