# AN-1106: An Improved Topology for Creating Split Rails from a Single Input Voltage (Rev. A) PDF

AN-1106 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com An Improved Topology for Creating Split Rails from a Single Input Voltage by Kevin Tompsett INTRODUCTION combination results in two supplies that track each other very well under all but a 100% load mismatch. An analysis of the converter’s operation and implementation using the Analog Devices, Inc., ADP161x demonstrates the versatility of this topology. In addition, a revolutionary new design tool is introduced, providing a quick path to implementing a SEPIC-Ćuk in user applications. One solution to this problem is to use two different converters; one to provide the positive rail and one to provide the negative rail. This can be expensive and, as this application note shows, unnecessary. Another solution is using a flyback; however, the supplies tend not to track each other very well with differential loading, it requires a large and expensive transformer, and it tends to be inefficient. A better solution is a SEPIC-Ćuk converter. This topology consists of an unregulated Ćuk converter tied to the same switching node as a regulated SEPIC converter. This VIN L2a L2b –VOUT C2 Q3 L1a COUT2 Q2 +VOUT C1 CIN Q1 L1b COUT1 09556-001 Even with the widespread use of rail-to-rail single supply op amps, there is still often the requirement for dual rails (for example, ±15 V) to be generated from a single (positive) input power rail to power different parts of the analog signal chain. These are often low current (such as 10 mA to 500 mA) with relatively well-matched loads on the positive and negative supplies. Figure 1. Schematic of the SEPIC-Ćuk Converter Rev. A | Page 1 of 12 AN-1106 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Power Component Stress .............................................................6 Revision History ............................................................................... 2 Output Filter ..................................................................................8 Description of Topology .................................................................. 3 ADP161x Design Tool ......................................................................9 Limits to the Coupling Coefficient ............................................ 4 Lab Results....................................................................................... 10 Differential Load and Output Voltage Tracking ...................... 4 References.................................................................................... 10 Small-Signal Analysis and Loop Compensation ...................... 5 Conclusion .................................................................................. 10 REVISION HISTORY 7/13—Rev. 0 to Rev. A Changes to Figure 8 .......................................................................... 6 7/11—Revision 0: Initial Version Rev. A | Page 2 of 12 Application Note AN-1106 DESCRIPTION OF TOPOLOGY Initially, the SEPIC-Ćuk appears to be a complicated converter with four different inductors and switches. Fortunately, it can be broken down into its two constituent converters, simplifying the analytical problem. For a SEPIC or Ćuk converter, the Q1 and Q2 switches operate in the opposite phase from one another. Figure 2 shows the current flow diagram for the two different switch states in a SEPIC converter. L1b COUT1 Q1 SN2 Q2 L1b Figure 2. Current Flow in a SEPIC Converter It is not immediately obvious, but the transfer capacitor (C1) voltage is approximately constant VIN (with small ripple). Figure 4 shows the idealized waveforms for a SEPIC converter. When Q1 is on, the voltage at SN2 is equal to −VIN. Thus, during the time that Q1 is on (Q2 is off), the voltage across both L1a and L1b is VIN and when Q1 is off (Q2 is on), then the voltage across both L1a and L1b is −VOUT. Applying the principles of inductor-volt second balance, the equilibrium dc conversion ratio as shown in Equation 1 can be calculated. D is the converter’s duty cycle (the fraction of the switching cycle that Q1 is on). VIN D (1 D) COUT2 (Q1 IS OPEN, Q2 IS CLOSED) L2a SN1 C2 SN2 L2b –V OUT Q1 Q2 COUT1 The idealized waveforms for a Ćuk converter are shown in Figure 4. Applying the principles of inductor-volt second balance and capacitor charge balance, the voltage across C2 is VIN + VOUT. Therefore, the SN2 switch node switches between GND, when Q2 is closed, and −(VIN + VOUT). The voltage across both L2a and L2b while Q1 is on (Q2 is off), is VIN and, while Q1 is off (Q2 is on), the voltage across both L2a and L2b is −VOUT. VOUT COUT1 Q2 Figure 3. Current Flow in a Ćuk Converter 09556-002 L1a SN1 C1 Q1 Comparing the waveforms in Figure 4 and Figure 5, note that the voltages across the inductors in a Ćuk are identical to those for the SEPIC. Thus, the duty cycle equation for a Ćuk is simply negative the duty cycle for the SEPIC,` as shown in Equation 2. NODE VOLTAGES VIN + VOUT –VIN (1) The Ćuk converter operates in a similar manner to the SEPIC converter, however, in this case, Switch Q2 is connected to ground rather than the output and the Inductor L2b is connected to the output instead of ground. Figure 3 shows a current flow diagram for the Ćuk converter during both switch positions. SN1 SN2 COMPONENT CURRENTS IL1a IL1b IOUT (IQ2) IOUT/(1 – D) D × IOUT (1 – D) IOUT The Ćuk is a negative output converter, so current flowing out of the load is actually delivering power to the output. Rev. A | Page 3 of 12 ON TIME OFF TIME ON TIME Figure 4. Idealized Waveforms SEPIC OFF TIME 09556-003 Q1 CIN VOUT SEPIC VIN CIN (Q1 IS OPEN; Q2 IS CLOSED) VIN CIN (Q1 IS CLOSED; Q2 IS OPEN) L1a SN1 C1 SN2 Q2 VOUT CIN (Q1 IS CLOSED, Q2 IS OPEN) L2a SN1 C1 SN2 L2b –V OUT 09556-004 VIN VIN AN-1106 Application Note NODE VOLTAGES LIMITS TO THE COUPLING COEFFICIENT SN1 SN2 Even though coupling the inductors has distinct advantages, it is undesirable for the coupling to be tight enough for there to be significant energy transfer through the core. To avoid this situation, the designer must ensure that the magnitude of the complex impedance of C1 (and C2) at the switching frequency is less than a tenth that of the impedance of the leakage inductance (LLKG) plus the DCR of a single winding. VIN + VOUT –VIN – VOUT COMPONENT CURRENTS IL1a IL1b IQ2 This inequality is designated in Equation 5. The leakage inductance (Ll) can be calculated using Equation 6 and the coupling coefficient (K) generally found on coupled inductor data sheets. Lm is the measured self-inductance that appears in the data sheet. Note that in Equation 5, the x in Cx and Lx refers to either C1 or C2 or L1 or L2. –IOUT/(1 – D) D × IOUT (1 – D) OFF TIME ON TIME OFF TIME 09556-005 ON TIME –IOUT | Z Cx Figure 5. Idealized Waveforms Ćuk VOUT Cuk VIN D (1 D) (2) The fact that the duty cycles are equal and opposite, the switch node (SN1) voltages are identical, and the inductor currents are identical is what makes it possible to simply attach the two converters together at Node SN1. The combined converter is shown in Figure 1. Q2 and Q3 have been replaced by diodes because these supplies are generally lower power analog supplies where an asynchronous controller makes good sense. In addition, two inductors (L1a and L2a) are in parallel. The reason for this is that L1a and L1b, and L2a and L2b, are coupled together using two separate coupled inductors. This has multiple advantages. Coupling the inductors reduces current ripple in the inductors by a factor of two (see the Ćuk-Middlebrook paper cited in the References section). In addition, it significantly reduces the complexity of the small signal model and enables higher bandwidth by eliminating the SEPIC and Ćuk resonances located according to Equation 3 and Equation 4. This enables the use of a wide variety of off-the-shelf parts since there are not many three winding 1:1:1 inductors available. f SEPIC resonance f Cuk resonance 1 2 L1a L1b C1 1 2 L 2a L 2b C 2 (3) 1 |= ESRC x 2 + 2 C f C x sw DCR L x 2 2L L lkg 2 | Z Llkg | Lx 10 Lx 10 Llkg Lm (1 K ) (5) (6) DIFFERENTIAL LOAD AND OUTPUT VOLTAGE TRACKING By nature, the Ćuk (negative) output of the SEPIC-Ćuk is unregulated; thus, there is some amount of load variation with changes in output current and, particularly with load mismatch, compared to the SEPIC (positive) output. Note that the tracking is much better than a similarly configured flyback converter, especially in the case of a transient or a load mismatch. This is because the coupling between channels is a direct connection rather than through the transformer with its inherent leakage inductance. Figure 6 shows a 30 mA transient applied to the Ćuk (−VOUT) output of a SEPIC-Ćuk converter, while a constant 100 mA remains on the SEPIC output. It shows that both outputs respond to the transient load. This is the worst-case transient because the Ćuk output is unregulated. Interestingly, most of the deviation shown on the −VOUT rail is actually dc regulation shift caused by the mismatch between the loads applied to the two rails (IOUT+, IOUT−). (4) A six winding part, such as found in Coilcraft’s Hexapath line product line, or a custom three winding transformer could also be used. Rev. A | Page 4 of 12 Application Note AN-1106 ADP161x part in SEPIC-Ćuk and may not be accurate for other parts made by Analog Devices or the company’s competitors. VOUT+ C1 The small-signal model for a SEPIC-ĆUK looks very similar to a SEPIC converter with no attached Ćuk as long as a few design requirements are met. It is assumed that identical inductors are used on the SEPIC-Ćuk rails. This requirement makes sense because both outputs are designed for the same voltage and current. VOUT– C3 C4 IOUT+ IOUT– C1 F BWL AC1M 5.00mV/DIV 15.100mV C2 F BWL DC 50.0mA/DIV –199.00mA TIMEBASE 0.00ms 500µs/DIV 500kS 100MS/s C3 F BWL AC1M 5.00mV/DIV 2.900mV C4 I F B DC 50.0mA/DIV –50.00mV TRIGGER C3 DC STOP 300µV EDGE POSITIVE 09556-006 C2 Figure 6. Transient Response from a 30 mA Step Load Applied to the Negative (Ćuk) Output With an identical load on both supplies, at steady state, the most significant error terms are a mismatch in the DCR of the inductors and the forward voltage of the diodes, both of which can be made quite small relative to the output voltage. With substantial load mismatch, the error grows as shown in Figure 7. Therefore, in some applications it may be necessary to put a small dummy load on one or both of the channels to keep both supplies in their regulation window. Note that, in general, analog chips, like op amps, are largely insensitive to dc changes in their power supplies as long as there is sufficient head room available. 2.0 LOAD ON VOUT+ = 0.1A LOAD ON VOUT+ = 0.01A LOAD ON VOUT+ = 0.051A LOAD ON VOUT+ = 0.0016A 1.5 VOUT/VIN (%) 0.5 0 –0.5 –1.0 –2.0 0.02 0.03 0.04 0.05 0.06 0.07 IOUT NEGATIVE SUPPLY (A) 0.08 0.09 0.10 09556-007 –1.5 0.01 The first step in compensating a SEPIC Ćuk is to choose an achievable target crossover frequency. Like most boost and buck-boost topologies, the SEPIC-Ćuk has a right half plane zero (RHP) located according to Equation 7. An RHP has the dual effect of adding gain, like a zero, and subtracting phase, like a pole. Therefore, the converter must be compensated for a crossover frequency a maximum of one fifth of the frequency of the RHP (fRHP). The SEPIC-Ćuk has an additional resonance caused by the leakage inductance (Llkg ) and transfer capacitance (C1) that occurs at Fres. This resonance is generally well damped by the DCR of the inductors, but can introduce significant phase lag; therefore, it is good to crossover at least a decade before it. In addition, a current mode controller with standard Type II compensation is used, thus, the maximum achievable crossover frequency is approximately one-tenth the switching frequency. Target fu should, therefore, be chosen as the minimum of these three constraints, as shown in Equation 9. 1.0 0 In their paper, Ćuk and Middlebrook (see the References section) show that a coupled inductor, from both a small signal and a large signal, behaves like an inductor with twice its single winding inductance value, without the SEPIC or Ćuk resonances. Therefore, analysis in this application note is shown using the effective inductance, that is, twice the single winding inductance value that appears on coupled inductor data sheets. The analysis assumes identical resistive loads, though the converter remains stable with significant load imbalance. The two transfer capacitances (C1 and C2) should be nearly the same value, erring on the side of having C2 slightly larger than C1. These are assumed to be ceramic capacitors and, thus, the designer needs to take into account the differences in their dc bias value when calculating their effective capacitances. Figure 7. Relative Voltage Regulation Between Rails with Differential Loading f RHP = f res = SMALL-SIGNAL ANALYSIS AND LOOP COMPENSATION A complete small-signal analysis of the SEPIC-Ćuk converter is beyond the scope of this paper; however, the equations provided in this application note should allow the designer to correctly compensate their design. The ADP161x SEPIC-Ćuk design tool uses a more complete model which is more accurate, but much more complicated. The equations shown refer to the Rev. A | Page 5 of 12 R LOAD D Q2 1.5 L D Q1 1 2π L lkg C 1 f fsw f f f u = minimum RHP , res , 10 10 5 (7) (8) (9) AN-1106 Application Note Ac is the magnitude of the open-loop converter gain at the crossover frequency fu. POWER STAGE AND INNER CURRENT LOOP –VOUT L2a C2 D2 L1a VIN GCS C1 Q1 L1b L2b RESR 3 COUT3 RLOAD D1 +VOUT RESR1 RLOAD COUT1 CLK R RI + M c 1 – RF1 VC CC1 CC2 GM VREF V REF 2 G m 2 Ac 2 4π 2 VOUT 2 1 1 f p2 fu 2 09556-008 2 C 2 1 fu C2 2 f p2 D off M c D on (16) Acs 13.5 (ADP1612/ADP1613) (17) VOUT I OUT V IN I pkLxa I I N 0.45 C out1 C out3 C 2 R LOAD (12) (into each inductor L1a and L2 a) I L 0.3I IN where: fp is the dominant pole for the current mode converter with some correction factors to account for ramp compensation and finite current gain. fp (15) V RAMP 0.1 (ADP1612/ADP1613) I IN (11) 2 (14) As is often the case, a 30% ripple in the inductors generally results in a reasonable value (see Equation 19). However, with large step down ratios it can be more optimal to increase this ripple percentage in the input inductor to 50% or 60%. (10) 1 2f p C C1 VRAMP f sw L1 Acs 2 V IN POWER COMPONENT STRESS The compensation values in Figure 8 can be calculated as follows. Since it is assumed ceramic output capacitors will be used, CC2 can be selected as 10 pf. (1 D off ) 0.25 (13) Vramp and Acs are fixed constants within the chip. RF2 RC1 Figure 8. Block Diagram Showing Power Stage and Compensation Components Rc 2 Lf sw Acs 4 M c V IN Fm FEEDBACK AND COMPENSATION C C1 C C2 f 1 u fp 2 Mc and Fm are terms derived from Ridley’s thesis (see the References section) on current mode control. RAMP Q S Fm F V (1 D ) 2D on D off 1 m out 2 on D on D off Rload Ac f 1 u f rhp (19) I L 2 I pkLxb I OUT L1 (18) I L 2 V I N VOUT (V IN VOUT ) f sw I L (20) (21) (22) The currents in the FET Switch Q1 and the two diode switches, Q2 and Q3, are shown in Figure 9. The dc components of the switch current are also shown in Figure 9. Note that Q1 carries the current for both the SEPIC and the Ćuk rails. The peak currents depend on the ripple chosen in Equation 19. Rev. A | Page 6 of 12 Application Note AN-1106 IQ1 IQ2 = IQ3 2 × IOUT/(1 – D) The peak-to-peak output voltage ripple on the SEPIC (positive) output is (ΔVripple SEPIC) and is approximated by 4 × ∆I I OUT D ON ΔVripple SEPIC ON TIME OFF TIME 09556-009 IOUT/(1 – D) ON TIME OFF TIME f sw C OUT 1 ESRCOUT 1 I OUT (1 D ON ) (23) The value of the current through the capacitor (IRMS Cout SEPIC) is Figure 9. Idealized Waveforms for SEPIC-Ćuk I D 1 I 1 DON (24) OUT ON 1 L (1 DON ) 2 I OUT 3 2 I rms _ COUT _ SEPIC Calculating the switching loss in the primary Switch Q1 is beyond the scope of this application note. Note that, in many cases, the switching loss can be quite large since the voltage swing the switch sees is large (~VIN + VOUT) and so are the currents (see Figure 9). The peak-to-peak output voltage ripple on the Ćuk (negative) output (ΔVripple Ćuk) is approximated by Vripple Cuk The ADP1612/ADP1613 work to reduce this loss by switching very quickly. The FET chosen must be rated to withstand at least VIN + VOUT and good engineering allows some margin for switch node ringing due to stray inductances, in addition to thermal stress from RDS on loss and switching losses. I L D ON ESR COUT3 I L 8 f sw C OUT3 (25) The I rms value of the current into the COUT on the Ćuk (negative) output (ΔVrip Ćuk) is approximated by I rms _ COUT _ Cuk I L 3 (26) The ripple on C1 and C2 should be chosen for around 5% of VIN. As stated earlier, they should have similar values despite the difference in dc voltage across them. Vripple _ Cx 1 DON I IN f sw C 1 I IN ESRC x (27) It is important to consider I rms ratings when choosing C1 and C2 since the current through them is quite large. Vripple _ Cx 1 DON I pk _ Lxa 2 I pk _ Lxa 1 DON I IN I IN ESRCx f sw C 1 I rms _ C C 1 2 3 I IN I L 2 I IN I L 2 2 DON 3 I pk _ L xb 2 I I L I L 2 pk _ L xb I OUT 2 I OUT 2 (28) (29) Rev. A | Page 7 of 12 AN-1106 Application Note I DC _ diode _ current _ rating 2 I IN I OUT I L 3 (30) OUTPUT FILTER The SEPIC-Ćuk as a dual rail converter is typically used for analog power supplies, which often require very low output ripple. Low output ripple (down to 1 mV) is generally easily achieved on the Ćuk (negative) output rail simply by using ceramic output capacitors because the output current is continuous like the output current of a buck converter. RFILT Q2 LFILT COUT1 +VOUT COUT2 09556-010 Since Q2 and Q3 are generally diodes, there are several things to consider when choosing a component. Vds max must be rated to at least VIN + VOUT. The continuous current should be at least 1/3 the peak current to be seen. Interestingly, because of the phase relationship between the output voltage ripple of the two supplies, the SEPIC diode actually receives the full switch for some amount of time before the current achieves a more even split. As expected though, the average current through both diodes is the same, IOUT. In addition, the package must be able to handle the IOUT in the thermal environment of the application. Figure 10. Schematic of the Output Filter Although this filter affects the small-signal model in new and interesting ways, this issue is not fully discussed in this application note. As long as the damping resistor is chosen according to the Equation 31 and Equation 32, and the converter is designed to crossover at a tenth of ωo or less, no instability should be caused by the pi filter. COUT1 should be chosen for around 2% output ripple and COUT2 should be chosen to match the output capacitor of the Ćuk output using the equations in the power components stress section. A good value for Lfilt is generally 1 μH, and Qo should be set to 1. o On the SEPIC (positive) rail, the output current is discontinuous like the input current of a buck converter. This results in a step change in the current into the output capacitors. These switching spikes are not well attenuated even by ceramic capacitors because of their inductance. Therefore, it is often necessary to put a small, damped output pi filter on the output of the SEPIC winding. Rev. A | Page 8 of 12 R filt 2C OUT 1 C OUT 2 L filt C OUT 1 C OUT 2 L R load L filt C OUT 1 C OUT 2 filt Q o o R load C OUT 1 C OUT 2 L filt C OUT 1 Qoo (31) (32) Application Note AN-1106 ADP161X DESIGN TOOL If the View Solution button is pressed, the design tool outputs a complete, optimized design. This includes a costed BOM with compensation values, an accurate, tested efficiency plot across load, a plot of power loss across load, a full load bode plot, performance parameters, component stresses, and power dissipation for every component. In addition, the Build Your Design tab provides the same BOM, but with the components arranged to fit on the blank demo board (ADP161x-BL3-EVZ) and any extra components required to configure the demo board . 09556-012 The ADP161x SEPIC-Ćuk design tool is a fully integrated Excel®-based designer for the ADP161x chips in a SEPIC-Ćuk configuration. Once the user has enabled macros (which may require a change of the security settings in Excel), the Enter Inputs dialog box appears, or can be found by pressing the Find Solution button. In the dialog box, enter the voltages and currents required for the design and choose whether to optimize for cost, loss, or size. Figure 12. Advanced inputs Dialog Box One of the most powerful features of this tool are the component buttons found on the User Interface tab. This functionality gives the user the ability to individually change each component to fully customize the design. 09556-011 Each of the components in the drop-down list have been preselected from a database of thousands of components to produce a functional design, and sorted according to the optimization chosen in the Enter Inputs dialog box. The components must be selected in order, from top to bottom, since there are dependencies between the different components. Figure 11. Basic Inputs Dialog Box Additional customization tools are available in the Advanced Settings dialog box. Here the user can select parameter specifications for output voltage ripple, current, transient response, optional output filter usage, an external UVLO, and more. A more in-depth description of the functionality of these options is provided in the Program Details dialog box available by clicking the Program Details button found on the Enter Inputs dialog box. Rev. A | Page 9 of 12 AN-1106 Application Note LAB RESULTS REFERENCES To demonstrate the efficacy of the design tool, a design was done using the tool for 5 VIN, ±5 VOUT at 50 mA with the advanced specifications shown in Figure 11 and Figure 12. In addition, the diode was changed for slightly lower loss. The jagged efficiency line at around 10 mA is caused by the converter going into discontinuous mode. Once both the switches have turned off, the switch node rings causing zero voltage switching at specific load currents. A schematic for the circuit is shown in Figure 14. Ridley, Dr. Ray. 1990. “A New Continuous-Time Model for Current-Mode Control.” Brandenton, FL: Ridley Engineering. Ćuk, Slobodan and R.D. Middlebrook. 1983. “CoupledInductor and Other Extensions of a New Optimum Topology Switching DC-DC Converter.” Advances in Switched-Mode Power Conversion, Volumes I and II. Irvine, CA: Tesla Co. CONCLUSION In conclusion, the SEPIC-Ćuk provides an inexpensive and robust way to create dual rails using only one controller. The ADIsimPOWER™ design tool allows complete customization of the design and can be relied on to create robust SEPIC-Ćuk designs quickly. 0.9 0.7 0.6 PREDICTED EFFICIENCY MEASURED EFFICIENCY 0.5 0 0.01 0.02 IOUT (A) 0.03 0.04 Figure 13. Efficiency Verification VOUT– COUT3 2× 10µF, 6.3V, 0805 D2 b a LPD4012-153 C2 1µF, 16V, 0805 b D1 VIN a LPD4012-153 CIN1 1µF, 6.3V, 0603 ENABLE RB0 10Ω C1 1µF, 16V, 0805 1µH ME3220-102MLB COUT1 1µF, 6.3V, 0603 VOUT+ COUT2 2× 10µF 6.3V, 0805 U1 ADP1613 CC1 15nF CC2 10pF RC1 27.4kΩ COMP FB EN GND SS RT IN SW CV5 1µF, 6.3V, 0603 RF2 16.5kΩ CSS 10nF RF1B 49.9kΩ 09556-014 0.4 09556-013 EFFICIENCY (POUT/PIN) 0.8 Figure 14. Schematic of Test Circuit Rev. A | Page 10 of 12 Application Note AN-1106 NOTES Rev. A | Page 11 of 12 AN-1106 Application Note NOTES ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN09556-0-7/13(A) Rev. A | Page 12 of 12

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