Atmel SAM9M10 EKES evaluation kit User Guide
Below you will find brief information for evaluation kit SAM9M10 EKES. The SAM9M10-EKES is a fully-featured evaluation platform for the Atmel SAM9M10-based microcontroller. The evaluation kit allows users to extensively evaluate, prototype and create application-specific designs. It includes many hardware peripherals such as two high speed USB hosts and one high speed device port, an Ethernet 10/100 interface, two high speed multimedia card interfaces, an LCD TFT display (480RGB272) with touch panel, a composite video output, a camera interface, and several communication peripherals such as Universal Synchronous/Asynchronous Receiver Transmitter (USART), Serial Synchronous Controller (SSC), and Two-Wire Interface (TWI). The external memory block is made of 3 memory types: DDR2-SDRAM, NAND Flash, and NOR Flash.
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AT91SAM9M10-EKES
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User Guide
11029A–ATARM–11-Jan-10
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AT91SAM9M10-EKES User Guide
Section 1
Section 2
Section 3
3.2
Battery................................................................................................................................ 3-1
3.3
DevStart ............................................................................................................................. 3-1
3.4
Recovery Procedure .......................................................................................................... 3-1
3.5
Sample Code and Technical Support ................................................................................ 3-2
Section 4
4.2.14 Push Buttons ..................................................................................................... 4-22
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Section 5
Section 6
Section 7
Section 8
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AT91SAM9M10-EKES User Guide
Section 1
Introduction
1.1
Scope
This User Guide introduces the SAM9M10 Evaluation Kit (SAM9M10-EKES) and describes its development and debugging capabilities.
Figure 1-1.
Board Photo
The Atmel
®
SAM9M10-EKES is a fully-featured evaluation platform for the Atmel SAM9M10-based microcontroller. The evaluation kit allows users to extensively evaluate, prototype and create applicationspecific designs.
The SAM9M10-EKES includes many hardware peripherals such as:
Two high speed USB hosts and one high speed device port
An Ethernet 10/100 interface
Two high speed multimedia card interfaces
An LCD TFT display (480*RGB*272) with touch pannel
A composite video output
AT91SAM9M10-EKES User Guide 1-1
11029A–ATARM–11-Jan-10
Introduction
A camera interface
Several communication peripherals such as:
– Universal Synchronous/Asynchronous Receiver Transmitter (USART)
– Serial Synchronous Controller (SSC)
– Two-Wire Interface (TWI)
The external memory block is made of 3 memory types:
DDR2-SDRAM
NAND Flash
NOR Flash
1.2
Applicable Documents
Table 1-1. Applicable Documents
Reference
6355A
Title
SAM9M10 Preliminary Datasheet
Comments
This document describes the SAM9M10, which is part of the Atmel's
Smart ARM
®
Microcontrollers.
It is available from http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf
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AT91SAM9M10-EKES User Guide
Section 2
Kit Contents
2.1
Deliverables
The Atmel SAM9M10-EKES toolkit includes:
Board
– The SAM9M10-EKES board
Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
Cables
– One micro A/B-type USB cable
– One serial RS232 cable
A Welcome Letter
Figure 2-1.
Unpacked SAM9M10-EKES
Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
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11029A–ATARM–11-Jan-10
Kit Contents
2.2
Evaluation Board Specifications
Table 2-1. SAM9M10-EKES Specifications
Characteristics Specifications
Clock speed
Ports
Board supply voltage
400 MHz PCK, 133 MHz MCK
Ethernet, USB, RS232, DBGU
5 VDC from connector
Temperature
- operating
- storage
Relative humidity
Dimensions
RoHS status
-10° to +50° C
-40° to +85° C
0 to 90% (non condensing)
180 mm x 160 mm
Compliant
2.3
Electrostatic Warning
The SAM9M10-EKES evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example...). Avoid touching the component pins or any other metallic element on the board.
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Section 3
Power up
3.1
Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.
3.2
Battery
The SAM9M10-EKES ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM9M10 series devices when the board is switched off.
3.3
DevStart
The on-board NAND Flash contains a “SAM9M10-EKES DevStart”.
It is stored in the “SAM9M10-EKES DevStart” folder on the USB Flash disk available when the
SAM9M10-EKES is connected to a host computer.
Click the file “welcome.html” in this folder to launch SAM9M10-EKES DevStart.
SAM9M10-EKES DevStart guides you through installation processes of IAR™ EWARM, Keil
™
MDK and
GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how to program it into the SAM9M10-EKES. Optionally, if you have a SAM-ICE™, instructions are also given about how to debug the code.
We recommend that you backup the “SAM9M10-EKES DevStart” folder on your computer before launching it.
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Power up
3.4
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-EKES to the state as it was when shipped by Atmel.
Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want to recover from this situation.
3.5
Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can d o w n l o a d s a m p l e c o d e a n d g e t t e c h n i c a l s u p p o r t f r o m A t m e l w e b s i t e http://www.atmel.com/dyn/products/product_card.asp?part_id=4653
Figure 3-1.
Atmel Website for SAM9M10 Series
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AT91SAM9M10-EKES User Guide
Section 4
Board Description
4.1
Equipment on the Board
Figure 4-1.
Board Architecture
Main Memory Multimedia cards LCD TFT Vidéo Audio User I/O
DDR2
SDRAM
DDR2
SDRAM
NAND
FLASH
PARALLEL
FLASH
8 bits interface
SD/MMC
Data
Flash
4 bits interface
SD/MMC
480*272
Screen
Composite video
Micro
Line In
Line Out
Codec
Joystick
& P.B
Led
LCD Interface
LCD Interface
AC97
AC97
EBI0
EBI0
EBI1 / 1.8v
EBI1 / 1.8v
External Memory
External Memory
MCI1
MCI1
SPI0
SPI0
MCI0
MCI0
Multimedia Cards Interface
Multimédia Cards Interface
System Controller
System Controller
Power /
Shdn
Image Sensor
Image Sensor
Interface
TWI
TWI
oooooooo oooooooo
Serial
Eeprom
ETHERNET
ETHERNET USART
USART
PHY RMII
RS232
VCC 5V ISI Ethernet RMII/MII RS232
USB
USB
PIO
PIO
DEBUG
DEBUG
DBGU JTAG/ICE
oooooooo oooooooo oooooooo oooooooo
USB Hub
High / Full
USB
Hub / Device
DBGU JTAG/ICE PIO
4.1.1
Interfaces
The board is equipped with a SAM9M10-CU chip (324-ball TFBGA package) together with the following interfaces or peripherals:
DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory
External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND
Flash and NOR Flash (not populated))
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Board Description
One TWI serial memory
One USB Host/Device multiplexed port interface
One USB Host port interface
One RS232 serial communication port
One DBGU serial communication port
One JTAG/ICE debug interface
One Ethernet 100-base TX with three status LEDs
One AC97 Audio DAC with headphone line out, line in and mono/stereo micro inputs
One TV interface (composite video output)
One 4.3" TFT LCD Module with touch screen and back light
One ISI connector (camera interface)
One Power red LED and two general-purpose green LEDs
Two user input push buttons
One joystick with 4-direction control and selector
One Wakeup input push button
One reset input push button
One DataFlash®/SD/SDIO/MMC plus card slot (4/8 bit interface)
One SD/SDIO/MMC card slot (4-bit interface)
One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)
4.1.2
4.1.3
Board Interface Connection
Ethernet using RJ45 connector (J15)
USB Host, support USB host using a type A connector (J12)
USB Host/Device, support USB host/device using a type micro AB connector (J14)
UART1 (Rx, Tx, Rts, Cts) connected to a 9-way male D-type RS232 connector (J11)
DBGU (Rx and Tx only) connected to a 9-way male D-type RS232 connector (J10)
JTAG, 20 pin IDC connector (J13)
SD/MMCplus connector (J5)
SD/MMC connector (J6)
Headphone (J7), line-in (J8) and microphone headset (J9)
Speaker output (JP15)
Image sensor connector (J17)
TFT LCD display (J16), with TouchScreen (J19) and BackLigth (J21)
Test points; various test points are located throughout the board
Main power supply (J2)
Push Button Switches
Reset, board reset (BP1)
Wake up, push button to bring processor out of low power mode (BP2)
Right and left click, user push button switches (BP4 and BP5)
Joystick (BP3)
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AT91SAM9M10-EKES User Guide
Board Description
4.1.4
Display LCD and LEDs
Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)
One surface-mounted power red LED, user interface (D8)
Two surface-mounted green LEDs, user interface (D6 and D7)
Three surface-mounted LEDs indicate Ethernet status (D9, D10, D11)
Figure 4-2.
Board Layout Commented
LINE
INPUT
MICROPHONE
INPUT
HEADPHONES
HEADER
VIDEO
OUTPUT
USER
JOYSTICK
TP4
DBGU
J10
MN18
C136
J8
J9
C118
R71
C150
C151
R72
JP14
MN15
C128
R58
C131
Y3
C121
C113 C112
JP13
J7
J20
C196
R121
R119
L21
TP5
R125
C192
BP3
L18
Y6
TP2
RS232
HOST
USB
HOST
DEVICE
USB
JP10
MN11
MN9
J11
MN17
MN10
MN8
4
J12
23 1
C163
J14
1
Q2
2
1
TP6
MN6
MN20 C165
JP5
C36
MN5
R23
C54
C35
C27
Y1
JP6
RR23 C48
C52
29
Y2
30
JTAG ETHERNET POWER
J13
MN7
20
19
J15 k k k
D9
D10
D11
1
C177
C172
C174
R109
R185
C173
C171
Y4
R92
R93
Y5
R112
R94 R95
C175
C181
C180 R108
C182
L2
L4
TP1
L5
L3
L6
2
1
J1
8
7
JP11
R104
MN14
R101 R100
1
JP4
Q1
BP2
J2
D2
MN4
BP1
J17
2
WAKE-UP
BUTTON
RESET
BUTTON
J3
BACKUP
BATTERY
C220
R142
C221
R143
BP5
RR36
RR34
RR35
BP4
TP3
«RIGHT»
USER BUTTON
«LEFT»
USER BUTTON
2
1
J18
20
19
2
1
J23
40
39
SD/MMC 0
SLOT
J6
J5
SD/MMC 1
SLOT
LCD DISPLAY LCD EXTENSION
CONNECTORS
ISI/CAMERA
CONNECTOR
The major components of the SAM9M10-EKES board are shown in Figure 4-1 .
4.2
4.2.1
4.2.2
Hardware Layout and Configuration
Processor
The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus.
For more information, refer to the last SAM9M10 datasheet available from http://www.atmel.com/
Clock Circuitry
The SAM9M10-EKES includes six clock sources:
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Board Description
Two are alternatives for the SAM9M10 main clock,
One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,
One crystal is used for the AC97 codec chip, and
One crystal or one crystal oscillator is used for the TV encoder.
Table 4-1. Main Components Associated with the Clock Systems
Quantity
1
Description
Crystal for Internal Clock, 12 MHz
1
1
1
1
1
Crystal for RTC Clock, 32.768 kHz
Oscillator for Ethernet Clock RMII, 50 MHz
Crystal for Ethernet Clock MII, 25 MHz
Crystal for AC91 Codec Clock, 24.576 MHz
Crystal for TV Encoder Clock, 13 MHz, or
Oscillator for TV Encoder, 13 MHz
Component assignment
Y1
Y2
Y4
Y5
Y3
Y7
Y6
4.2.3
4.2.4
Reset Circuitry
The reset sources are:
Power on reset
Push button reset
JTAG reset from an in-circuit emulator interface.
Memory
4.2.4.1
External Memories
The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The SAM9M10-EKES board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2-
SDRAM memory (Micron MT47H64M8B6-3 16Meg*8*4).
The External Bus Interface (EBI) is connected to three kinds of memory devices:
One Parallel Flash AT49SV322DT (not populated by default)
Two DDR2-SDRAM MT47H64M8B6-3
One NAND Flash MT29F2G16ABD (not populated by default) or MT29F2G08ABD (single footprint)
The chip select NCS0, NCS1 and CS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash memories, respectively. Furthermore, a dedicated jumper can disconnect each of these NCS0, NCS1, and
NCS3 signals, making them available for other functions.
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AT91SAM9M10-EKES User Guide
Figure 4-3.
EBI0 - DDR2
Board Description
AT91SAM9M10-EKES User Guide 4-5
11029A–ATARM–11-Jan-10
Board Description
Figure 4-4.
EBI1 - DDR2 + Flash
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AT91SAM9M10-EKES User Guide
4.2.5
Board Description
Power Supplies
The SAM9M10 Board contains four regulated power supplies:
3.3 VDC Supply
1.8 VDC Supply
1.0 VDC Core Supply
1.0 VDC Core UTMI Supply, PLL
The outputs of these regulated power supplies
1
are distributed as necessary to each part of the circuit board.
The 3.3 VDC Supply is generated by an LTC1765-3.3 chip. It accepts VIN 5 VCC power and outputs a regulated +3.3 V to most other circuits in the SAM9M10-VB.
The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an LT1765-1.8. It is powered by VIN
5 VCC power and outputs a regulated +1.8V.
The 1.0 VDC Core Supply (VDDCORE) is generated by a TPS60500 IC. It is powered by the VIN
5 VCC power.
The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by a CMOS voltage regulator R1100D series. It is powered by the output of the 3.3 VDC Supply.
Note: 1.
Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to permit probing of these voltages.
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Board Description
Figure 4-5.
Power Supply and Management Power Block
2 2 2
1
OUT
2
VDD
GND
3
2 2
2
2
T BOOS
GND1
GND2
GND4
GND5
GND3
VC
SYNC
8
1
17
16
9
14
13
2
T BOOS
GND1
GND2
GND4
GND5
GND3
VC
SYNC
8
1
17
16
9
14
13
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AT91SAM9M10-EKES User Guide
Board Description
4.2.6
Debug Interface
4.2.6.1
JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator.
Figure 4-6.
JTAG Interface
3V3
3V3
14
16
18
20
2
4
6
8
10
12
3V3
13
15
17
19
1
3
5
7
9
11
ICE INTERFACE
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
4.2.6.2
DBGU Com Port
This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).
Figure 4-7.
DBGU Com Port
3V3
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
6
14
7
13
8
16
15
2
1
C1-
C2+
3
4
5
11
10
12
9
3V3
PB13
PB12
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Board Description
4.2.6.3
User Serial Com Port
The USART1 is used as a user serial com port. This USART1 is buffered with an RS-232 Transceiver
(TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Software must assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the
UART1 function.
Figure 4-8.
User Serial Com Port
3V3
PB4
PD16
PB5
PD17
3V3
1
5
11
10
12
9
3
4
C1-
C2+
6
14
7
13
8
16
15
2
RS232 COM PORT
1
6
2
7
3
8
4
9
5
Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs.
4.2.6.4
USB Port
The SAM9M10-EKES features USB communication ports:
Two Host Ports: Full speed OHCI and High speed EHCI
One Device Port: High speed.
USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is multiplexed with the USB device High speed and connected to the second UTMI port.
One USB high/full speed type standard A connector
One USB interface Host/Device Micro AB connector
Refer to the SAM9M10 datasheet for detailed programming information.
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Board Description
Figure 4-9.
USB Port
1
4
5 6
2
3
USB HOST INTERFACE
33 uF
16V
33 uF
16V
5V
8
7
OUTA
IN
ENA
FLGA
1
2
6
5
GNG
OUTB
FLGB
ENB
3
4
R88 47K
(VBUS)
PB19
3V3
7
6
1
2
3
4
5
USB HOST/DEVICE INTERFACE
HDMA
HDPA
(ENA)
(FLGA)
(FLGB)
(ENB)
PD1
PD2
PD4
PD3
(IDUSB)
HDMB
HDPB
PD28
4.2.6.5
Ethernet 10/100 (EMAC) Port
The port is compatible with IEEE
®
Standard 802.3.
The SAM9M10-EKES is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical
Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment
(PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status
LEDs.
The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-Tx or
10Base-Tx. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the table below.
AT91SAM9M10-EKES User Guide 4-11
11029A–ATARM–11-Jan-10
Board Description
Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name Normal MII Mode
ETX0-ETX1
ETX2-ETX3
ETXEN
ETXER
ETXCK/REFCK
ERX0-ERX1
ERX2-ERX3
SAM9M10
ETX[0:1] transmit data
ETX[2:3] transmit data
ETXEN: transmit enable
ETXER: transmit error
ETXCK: transmit clock
ERX[0:1]: receive data
ERX[2:3]: receive data
ERXER ERXER: receive error
DM9161
TXD [0:1]
TXD [2:3]
TXEN
TXER/TXD[4]
TXCLK
RXD [0:1]
RXD [2:3]
RXER/RXD[4]/
RPTR/NODE
ERXDV
ERXCK
ECOL
ECRS
EMDC
EMDIO
NRST
ERXDV: receive valid data
ERXCK: receive clock
ECOL: collision detect
ECRS: carrier sense / data valid
RXDV
RXCLK
COL
CRS (PHYAD[2:4]
EMDC: management data clock MDC
EMDIO: management data input / output
NRST: microcontroller reset
MDIO
RESET# XT1
(25 MHz)
ETX[0:1]
Reduced MII Mode
SAM9M10 DM9161
TXD [0:1]
NC
ETXEN: transmit enable
NC
REFCK: reference clock
ERX[0:1]: receive data
NC
NC
TXEN
NC
REF_CLK
RXD [0:1]
NC
RPTR/NODE ERXER: receive error
ECRSDV: carrier sense / data valid
NC
NC
CRS DV
NC
NC
NC NC
EMDC: management data clock
EMDIO: management data input / output
NRST: microcontroller reset
MDC
MDIO
RESET# XT1
(REF_CLK 50MHz)
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AT91SAM9M10-EKES User Guide
Board Description
Figure 4-10. Ethernet Port
16
15
7
6
5
8
3
2
1
4
6
5
8
7
7
6
5
8
6
5
8
7
4
3
2
1
3
2
1
4
4
3
2
1
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.
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11029A–ATARM–11-Jan-10
Board Description
4.2.7
Audio Stereo Interface
The SAM9M10-EKES includes an AD1981B AC97 SoundMAX® CODEC for digital sound input and output. This interface includes audio jacks for MIC input (J9), Line audio input (J8), Headphone line output
(J7) and a 2-point speaker output connector (JP15).
It is compliant with AC97 Component Specification V2.2.
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AT91SAM9M10-EKES User Guide
Figure 4-11. Audio Stereo Interface
AGND_AC97
+ + + +
2
46
45
47
48
42
41
40
44
43
38
37
39
2
NC
ID1
ID0
EAPD
SPDIF
AVSS
AVSS3
AVDD3
AVDD2
HP_OUT_L
HP_OUT_R
MONO_OUT
CD_GND_REF
PHONE_IN
LINE_IN_R
LINE_IN_L
CD_ R
MIC2
MIC1
1
0
JS
JS
CD_L
AUX_R
AUX_L
22
21
19
20
24
23
15
14
13
17
18
16
Board Description
IN O
For more information about the AC97 codec device, refer to the Analog Devices AD1981B controller manufacturer's datasheet.
AT91SAM9M10-EKES User Guide 4-15
11029A–ATARM–11-Jan-10
Board Description
4.2.8
TV-Out Extension
The Chrontel CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set by converting LCD signals to TV signals.
The CH7024 is a TV encoder device which encodes the video signals and generates synchronization signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433,
PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or Svideo.
Figure 4-12. TV-Out Extension Port
PE[0..30]
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPW R)
PE19
PE20
PE21
PE22
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE15
PE16
PE17
PE18
PE3
PE4
PE5
PE6
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
39
40
41
20
V
H
XCLK
DE
47
48
1
4
5
6
2
3
7
8
42
43
44
45
46
9
10
11
12
13
14
15
17
19
3V3
PA20
PA21
NRST
(TW DO)
(TW CK0)
3V3
21
22
SPD
SPC
23
RESET
24
NC
1 4
2 3
SG-8002JC-13.0000M-PCB
DNP
C205
DNP
4
1
3
2
VDDIO
DVDD
38
16
DGND
18
AVDD_PLL
32
AGND_PLL
31
AVDD
33
AGND
36
AVDD_DAC
25
AGND_DAC
29
ISET
CVBS
30
28
Y
27
C/CVBS
26
P-OUT
37
C190
100nF
C191
100nF
C192
10uF
10V
3V3
1V8
3V3
C196
10uF
10V
1
C193
10uF
10V
3V3
2
3
Composite Video Output
4.2.9
The frequency accuracy must be +-20ppm or higher.
Software Controlled LEDs
Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their control through either GPIO or PWM control.
LEDs D6 to D8 are software controlled by PIO pins.
LEDs D9 to D11 indicate Ethernet traffic and link status. These are automatically managed by on-chip microcontroller hardware. See Section 7.1 ”Schematics” .
4-16
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Board Description
Table 4-3. Discrete LEDs
LED Description
D6
D7
D8
D9
D10
D11
Green LED
Green LED
Red LED
Yellow LED
Green LED
Green LED
Comment
User software controlled
User software controlled
User software controlled
Indicates transmission or reception via Ethernet
Indicates speed 100
Is lit when a good link test has been detected
Figure 4-13. Software Controlled LEDs
USER INTERFACE
3V3
3V3
PD0
PD31
PB15
PB16
3
1
2
POWER LED
PD30
PB[14..18]
PB14
PB18
PB17
LEFT
PUSH
1
2
3
4
5
6
UP
RIGHT
DOWN
JOYSTICK
4.2.10
Serial Peripheral Interface Controller (SPI)
The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial EEPROM.
Figure 4-14. SPI
3V3
PB0
PB1
PB2
PB3
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
NRST
DNP
Test point
1 3
8
1
2
4
SO
SI
SCK
CS
VCC
GND
6
7
3
RESET WP
5
SERIAL DATAFLASH
3V3
W RITE PROTECT
NORMALLY OPEN
AT91SAM9M10-EKES User Guide 4-17
11029A–ATARM–11-Jan-10
Board Description
4.2.11
Two Wire Interface (TWI)
The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully compatible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the onboard Serial DataFlash, ISI and TV encoder interface.
Figure 4-15. TWI
3V3
PA21
PA20
(TW CK0)
(TW DO)
3V3
6
5
SCL
SDA
8
VCC
4
GND
A0
A1
A3
1
2
3
WP
7
SERIAL EEPROM
4.2.12
SD/MMC Interface
The SAM9M10-EKES has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit
SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit
SD/MMC card slot.
The users must provide their own compatible cards for use with these connectors.
Please note that the power is connected to VCC, which is 3.3 volts.
4-18
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Figure 4-16. SD/MMC0-MMC1
8
7
6
5
8
7
6
5
8
7
6
5
4
3
2
1
4
3
2
1
4
3
2
1
Board Description
8
7
6
5 4
3
2
1
AT91SAM9M10-EKES User Guide 4-19
11029A–ATARM–11-Jan-10
Board Description
4.2.13
TFT LCD with Touch Panel
The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10-
EKES with a low power LCD display, back light unit and a touch panel, similar to that used on commercial PDAs.
The TFT LCD component is an LG
®
/PHILIPS
®
, model number LB043WQ1.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the user to develop graphical user interfaces for a wide variety of end applications.
Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing so may damage both units and is not covered by warranty.
The back light voltage is generated from a TPS61161 boost converter. It is powered directly by the VIN
5 VCC power (the control for the back light voltages is separated from the main board voltages due to the specific voltage requirements of the LCD panel).
4-20
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Figure 4-17. TFT LCD
Board Description
AT91SAM9M10-EKES User Guide
S S LG PHILIP LG PHILIP
E rs rs cto
SIDE SID nducto du Co Con
TOP TOP
on on
4
SW
GND
THP
7
3
4-21
11029A–ATARM–11-Jan-10
Board Description
4.2.14
Push Buttons
The SAM9M10-EKES is equipped with two system push buttons, two user push buttons and one joystick. The push buttons consist of momentary push button switches mounted directly to the board. When any switch is depressed, a low (zero) appears at the associated input pin.
System push buttons:
– Reset, perform system reset
– Wakeup, perform system wake up
User push button:
– Right click
– Left click
Joystick:
– One touch, 5-way switching,
– Normally open momentary contacts,
– Push down to select in any position.
Figure 4-18. Push Buttons
VDDBU
3V3
NRST
WAKE UP
RIGHT CLICK
LEFT CLICK
NRST
WAKE UP
PB7
PB6
4.2.15
Expansion Slot
GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23
All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17
Touch screen signals and analog I/O are connected to J18
This allows the developer to extend the features of the board by adding external hardware components or boards.
4-22
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Figure 4-19. Expansion Slot
CONNECTOR EXTENTION FOR LARGE LCD
PD14
3V3
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
PE4
PE5
PE6
PE0
(GPIO1)
23
25
27
29
13
15
17
19
21
5
7
9
11
1
3
31
33
35
37
39
24
26
28
30
14
16
18
20
22
2
4
6
8
10
12
32
34
36
38
40
PE7
PE9
PE11
PE13
PE15
PE17
PE19
PE21
PE23
PE25
PE27
PE29
PE3
PE2
PE1
(GPIO2)
PD15
PD21
PD23
PD25
PD27
PD19
3V3
(AD1Xm)
(AD3Ym)
7
9
11
13
1
3
5
15
17
19
2
4
6
8
10
12
14
16
18
20
(AD0Xp)
(AD2Yp)
PD20
PD22
PD24
PD26
PD18
5V
3V3
Board Description
IMAGE SENSOR CONNECTOR
3V3
C187
10uF
10V
VDDISI
PD12
(CTRL1)
PA21
PB21
PB23
PB25
PB27
PB9
PB11
13
15
17
19
21
23
25
27
29
7
9
11
1
3
5
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13
AT91SAM9M10-EKES User Guide 4-23
11029A–ATARM–11-Jan-10
Section 5
Configuration
5.1
JTAG/ICE Configuration
Table 5-1. JTAG/ICE Configuration
Designation Default Setting
R84
R85
R86
R87
Not populated
Soldered
Soldered
Not populated
Feature
Disables the ICE NTRST input
Enables the ICE RTCK return. R87 must be opened
Enables the ICE NRST input
Disables TCK <-> RTCK local loop
5.2
ETHERNET Configuration
RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R92 and solder R93, R98 to R104, R107.
Two types of jumpers are used on the SAM9M10-EKES board:
2-pin jumpers with two possible settings:
– Fitted: the circuit is closed, and
– Not fitted: the circuit is open
3-pin jumpers with two possible positions, for which settings are presented in the following tables.
AT91SAM9M10-EKES User Guide 5-1
11029A–ATARM–11-Jan-10
Configuration
5.3
Jumpers Configuration
Table 5-2. Jumpers Configuration
Designation
Default
Setting
J1
(combined jumper array)
JP1
JP2
JP3
JP4
JP5
JP6
JP7
JP8
JP9
JP10
JP11
JP12
JP13
JP14
JP15
JP16
Closed
Closed
Closed
Closed
1-2
1-2
1-2
Opened
1-2
1-2
1-2
Opened
Closed
Closed
Test point
Closed
Opened
Closed
J1-1
J1-2
J1-3
J1-4
JP1
JP2
JP3
1-2
3-4
5-6
7-8
1-2
2-3
1-2
2-3
1-2
2-3
VDDIOP0
VDDIOP2
Feature
VDDUTMII 3V3
VDDUTIMC 1V
VDDCORE 1V
VDDPLLUTMI 1V
External power to VDDIOP0
VDDIOP1
External power to VDDIOP1
External power to VDDIOP2
3V3
3V3 nominal
3V3
3V3 nominal
3V3
3V3 nominal
Forces power on.
To use the software shutdown control, JP4 must be opened.
3V battery backup must be present and JP7 jumper set in position 1-2
1-2 VDDIOM0 1V8
JP5
2-3
1-2
External power to VDDIOM0
VDDIOM1
1V8 nominal
1V8
JP6
2-3
1-2
External power to VDDIOM1
VDDBU
1V8 nominal
Lithium 3V Battery
JP7
2-3 VDDBU 3.3V from regulator
BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected to NCS0
Enables chip select access, Boot on the NCS0 (MN10 Flash)
Enables chip select access, Boot on the NCS3 (MN12 NAND Flash)
JP11.1: SO JP11.2: SI
JP14.1 = Line_Out_L
Used to connect a Loudspeaker
DISMDIX (MN22)
JP11.3: SCK
Enables chip select access, Boot on the SPIO_NPCS0 (Serial Data Flash MN14)
Set address A0 low (MN13 Serial EEPROM), enable Boot access.
JP14.3 = Line_Out_R
5-2
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
5.4
Configuration
Miscellaneous Configuration Items
N.P = not populated
P = populated
R58, R59
R60
R75, R77
R69, R70
R84,R85
R86,R87
R92, R93,
R94, R95,
R98, R99
R100, R101
R102,R103
R104,R107
R112
Y6, R122,
R124
TP1
TP2
TP3
TP4
Table 5-3. Miscellaneous Configuration
Designation
Default
Setting
R20
R21
N.P
P
Feature
JTAGSEL
Connect TSADVREF to VDDANA (may be used for specific filtering)
R22
R24
P
P
R47
R55
N.P
N.P
N.P
N.P
N.P
Connect GNDANA to GND (may be used for specific filtering)
Force TST pin to GND (chip is set in non-test mode = normal operation mode)
Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND
Flash device)
Write protect serial Data Flash (mount a 0-ohm resistor to write-protect the serial
Flash device)
Clock selection Audio AC97 (see mapping table in Section 7.1 ”Schematics” )
External clock Audio AC97 (mount a 0-ohm resistor to connect it)
Change bias from VREFOUT (see Section 7.1 ”Schematics” )
Voice filter components
N.P
ICE interface reset and clocking schemes (see
GND Test point
GND Test point
GND Test point
GND Test point
Ethernet interface, MII mode (see
Section 5.2 ”ETHERNET Configuration”
External 13 MHz oscillator (option) for the on-board video composite encoder
5.5
5.5.1
PIO Configuration
Peripheral Signals Multiplexing on I/O Lines
The AT91SAMM10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
AT91SAM9M10-EKES User Guide 5-3
11029A–ATARM–11-Jan-10
Configuration
5.5.2
Multiplexing on PIO Controller A (PIOA)
"R.Select" = connection selectable via an on-board resistor (default not populated)
Table 5-4. PIO Multiplexing Port A
I/O Peripheral A Peripheral B
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA4
PA5
PA6
PA7
PA0
PA1
PA2
PA3
ERXER
ETXCK
EMDC
EMDIO
TWD0
TWCK0
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4
MCI1_DA5
MCI1_DA6
MCI1_DA7
MCI1_CK
MCI0_CK
MCI0_CDA
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
ETX0
ETX1
ERX0
ERX1
ETXEN
ERXDV
CTS3
PWM3
TIOB2
ETXER
ERXCK
ECRS
ECOL
PCK0
SCK3
RTS3
ERX2
ERX3
TCLK3
TIOA3
TIOB3
TCKL4
TIOA4
TIOB4
ETX2
ETX3
R.Select
R.Select
R.Select
R.Select
Function and Comments
MMCI0 Clock
MMCI0 Command
MMCI0 Data0
MMCI0 Data1
MMCI0 Data2
MMCI0 Data3
Ethernet MII
Ethernet MII
Ethernet MII
Ethernet MII
Ethernet RMII Transmit data 0
Ethernet RMII Transmit data 1
Ethernet RMII Receive data 0
Ethernet RMII Receive data 1
Ethernet RMII Transmit enable
Ethernet RMII Receive data valid
Ethernet RMII Receive Error
Ethernet RMII Transmit Clock
Ethernet RMII Manag.Data Clock
Ethernet RMII Manag.Data In/Out
Two Wire Interface Data
Two Wire Interface Clock
MMCI1 Command
MMCI1 Data0
MMCI1 Data1
MMCI1 Data2
MMCI1 Data3
MMCI1 Data4
MMCI1 Data5
MMCI1 Data6
MMCI1 Data7
MMCI1_clock
Ethernet MII
Ethernet MII
Ethernet MII
Ethernet MII
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Power
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
5-4
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Configuration
5.5.3
Multiplexing on PIO Controller B (PIOB)
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB5
PB6
PB7
PB8
PB1
PB2
PB3
PB4
Table 5-5. PIO Multiplexing Port B
I/O
PB0
Peripheral A
SPI0_MISO
Peripheral B
TXD0
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
TXD1
RXD1
TXD2
RXD2
TXD3 ISI_D8
RXD3
TWD1
TWCK1
DRXD
ISI_D9
ISI_D10
ISI_D11
DTXD
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
CTS0
SCK0
SPI1_NPCS0 RTS0
RXD0 SPI0_NPCS1
ISI_D7
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
SPI0_NPCS2
PCK1
Function and Comments
SPI Slave Out AT45DB642
SPI Slave In AT45DB642
SPI Serial Clock AT45DB642
SPI Chip Select AT45DB642
USART1 Receive Data
User Push Button Right click
User Push Button Left click
Image Sensor Data 8
Image Sensor Data 9
Image Sensor Data 10
Image Sensor Data 11
DBGU Receive Data
DBGU Transmit Data
Joystick Right
Joystick Up
Joystick Down
Joystick Push
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
UsbVbus VDDIOP0
Image Sensor Data 0 VDDIOP2
Image Sensor Data 1
Image Sensor Data 2
VDDIOP2
VDDIOP2
Image Sensor Data 3
Image Sensor Data 4
Image Sensor Data 5
Image Sensor Data 6
Image Sensor Data 7
Image Sensor Data Clock
Image Sensor Vertical Synchro
Image Sensor Horizontal Synchro
Image Sensor Reference Clock
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
Power
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP0
VDDIOP0
VDDIOP0
AT91SAM9M10-EKES User Guide 5-5
11029A–ATARM–11-Jan-10
Configuration
5.5.4
Multiplexing on PIO Controller C (PIOC)
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC29
PC30
PC31
Table 5-6. PIO Multiplexing Port C
I/O
PC0
PC5
PC6
PC7
PC8
PC1
PC2
PC3
PC4
PC9
PC10
PC11
PC12
Peripheral A
DQM2
DQM3
A19
A20
A21/NANDALE
A22/NANDCLE
A23
A24
CFCE1
CFCE2
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
Peripheral B Function and Comments
Add19 Flash AT49SV322
Add20 Flash AT49SV322
ALE Flash AT49SV322
CLE Flash AT49SV322
Power
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
RTS2
TCLK2
Ready/Busy NAND Flash
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
CTS2 VDDIOM1
VDDIOM1
D25
D26
D27
D28
D21
D22
D23
D24
D17
D18
D19
D20
NCS2
NCS3/NANDCS Chip select NAND Flash
NWAIT
D16
D29
D30
D31
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
5-6
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Configuration
5.5.5
Multiplexing on PIO Controller D (PIOD)
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD5
PD6
PD7
PD8
PD1
PD2
PD3
PD4
Table 5-7. PIO Multiplexing Port D
I/O
PD0
Peripheral A
TK0
Peripheral B
PWM3
SPI1_NPCS3
TIOA0
TIOA1
TIOA2
TCLK0
SPI0_NPCS1
SPI0_NPCS2
PCK0
PCK1
TSADTRG
TCLK1
TIOB0
TIOB1
RK0
RF0
AC97RX
TF0
TD0
RD0
AC97TX
AC97FS
AC97CK
TD1
RD1
TK1
RK1
TF1
RF1
RTS1
CTS1
SPI1_NPCS2
FIQ
PWM0
PWM1
PWM2
SPI0_NPCS3
SPI1_NPCS1
SCK1
SCK2
PWM1
IRQ
PCK0
TIOA5
TIOB5
TCLK5
Function and Comments
Output ENA USB Host
Input FLGA USB Host
Output ENB USB Host
Input FLGB USB Host
Int. Ethernet 10/100 MDINTR
AC97 Receive Signal
AC97 Signal
AC97 Frame Sync Signal
Card Detect MMCI0 MCI0_CD
Card Detect MMCI1 MCI1_CD
CTRL1 Image Sensor Interface
CTRL2 Image Sensor Interface
GPIO1 Large LCD (connector)
GPIO2 Large LCD (connector)
USART1 Request to Send
USART1 Clear To Send
TSAD0 Touch screen X_Right
TSAD1
TSAD2
TSAD3
GPAD4
Touch screen X_Left
Touch screen Y_Up
Touch screen Y_Down
General purpose A/D4
GPAD5
GPAD6
GPAD7
General purpose A/D5
General purpose A/D6
General purpose A/D7
USB Plug-ID IDUSB
MCI1_WP
Command Power Led
Command LED1
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Power
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
AT91SAM9M10-EKES User Guide 5-7
11029A–ATARM–11-Jan-10
Configuration
5.5.6
Multiplexing on PIO Controller E (PIOE)
Table 5-8. PIO Multiplexing Port E
I/O
PE0
Peripheral A Peripheral B
LCDPWR PCK0
PE25
PE26
PE27
PE28
PE29
PE30
PE31
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE5
PE6
PE7
PE8
PE1
PE2
PE3
PE4
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD16
LCDD17
LCDD18
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
PWM2
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD8
LCDD9
LCDMOD
LCDCC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDD0
LCDD1
Function and Comments
LCD Panel Pow.Enab.Ctrl
LCD Modulation Signal
LCD Contrast Control
LCD Vertical Synch.
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD18
LCDD19
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCD Data Enable
LCD-Red0
LCD-Red1
LCD-Red2
LCD-Red3
LCD-Red4
LCD-Red5
LCD-Red6
LCD-Red7
LCD-Green0
LCD-Green1
LCD-Green2
LCD-Green3
LCD-Green4
LCD-Green5
LCDD20
LCDD21
LCDD22
LCDD23
LCD-Green6
LCD-Green7
LCD-Blue0
LCD-Blue1
LCD-Blue2
LCD-Blue3
LCD-Blue4
LCD-Blue5
PCK1
LCD-Blue6
LCD-Blue7
AC97 External Clock
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
Power
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
5-8
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Section 6
Connectors
6.1
Power Supply
The AT91SAMM10-EKES evaluation board can be powered from a DC 5V power supply via the external power supply jack (J2) shown in Figure 10 1. The positive pole must be on J2 center pin.
Figure 6-1.
Power Supply Connector J2
Table 6-1. Power Supply Connector J2 Signal Description
Pin
1
Mnemonic
Center
Signal description
+5 VCC
2 Gnd
6.2
RS232 Connector with RTS/CTS Handshake Support
Connector J11 is the COM1 connector.
Figure 6-2.
RS232 COM1 Connector J11
AT91SAM9M10-EKES User Guide 6-1
11029A–ATARM–11-Jan-10
Connectors
Table 6-2. Serial COM1 Connector J11 Signal Descriptions
Pin Mnemonic Signal description
1, 4, 6, 9
2
3
5
7
8
NC
TXD TRANSMITTED DATA
RXD RECEIVED DATA
GND
RTS READY TO SEND
CTS CLEAR TO SEND
NO CONNECTION
RS232 serial data output signal
RS232 serial data input signal
GROUND
Active-positive RS232 input signal
Active-positive RS232 output signal
6.3
DBGU
Connector J10 is the DBGU connector.
Figure 6-3.
RS232 DBGU Connector J10
Table 6-3.
RS232 DBGU Connector J10 Signal Descriptions
Pin Mnemonic Signal description
1, 4, 6, 7, 8, 9 NC
2 TXD TRANSMITTED DATA
3
5
RXD RECEIVED DATA
GND
NO CONNECTION
RS232 serial data output signal
RS232 serial data input signal
GROUND
6-2
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors
6.4
Ethernet
Connector J15 is the RJ-45 Ethernet Connector.
Figure 6-4.
Ethernet RJ45 Connector J15
Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions
Pin
1
Mnemonic
TxData+ DIFFERENTIAL OUTPUT PLUS
Pin
2
Mnemonic
Txdata- DIFFERENTIAL OUTPUT MINUS
3
5
7
RxData+ DIFFERENTIAL INPUT PLUS
Shield
Shield
4
6
8
Shield
RxData- DIFFERENTIAL INPUT MINUS
Shield
6.5
USB Host
Connector J12 is the USB Host connector.
Figure 6-5.
USB Host type A connector J12
Table 6-5. USB Host Type A Connector J12 Signal Descriptions
Pin
1
Mnemonic
Vbus
Signal description
5v power
4
5
2
3
DM
DP
Gnd
Shield
Data minus
Data plus
Ground
Shield
AT91SAM9M10-EKES User Guide 6-3
11029A–ATARM–11-Jan-10
Connectors
6.6
USB Host/Device
Connector J14 is the USB Host/Device connector.
Figure 6-6.
USB Host/Device Micro AB connector J14
Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions
Pin Mnemonic Signal description
Vbus 5v power
3
4
1
2
5
DP
ID
Gnd
Data plus
On the Go Identification
Ground
6.7
JTAG Debugging Connector
Connector J13 is the JTAG/ICE connector.
A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable.
Figure 6-7.
JTAG/ICE Connector J13
6-4
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Connectors
17
18
19
20
14
15
16
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin Mnemonic
1
2
3
VTref. 3.3V power
Vsupply. 3.3V power nTRST TARGET RESET - Active-low output signal that resets the target
Description
This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor.
This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
4 GND
5
6
7
TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal.
GND
TMS TEST MODE SELECT
Common ground
JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
Common ground
JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.
8
9
10
11
12
13
TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access.
GND
RTCK - Input Return test clock signal from the target.
GND
TDO JTAG TEST DATA OUTPUT - Serial data input from the target.
GND nSRST RESET
GND
RFU
GND
RFU
GND
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
Common ground
Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND
Common ground
JTAG data output from target CPU. Typically connected to TDO on target CPU.
Common ground
Active-low reset signal. Target CPU reset signal
Common ground
This pin is not connected in SAM-ICE.
Common ground
This pin is not connected in SAM-ICE
Common ground
AT91SAM9M10-EKES User Guide 6-5
11029A–ATARM–11-Jan-10
Connectors
6.8
SD/MMC- MCI0
Connector J6 is the SD/MMC connector.
Figure 6-8.
SD/MMC0 Connector J6
6-6
11029A–ATARM–11-Jan-10
Table 6-8. SD/MMC0 Connector J6 Signal Descriptions
Pin Mnemonic Pin Mnemonic
9
11
5
7
1
3
RSV/DAT3
GND
CLK
DAT0
DAT2
GND
6
8
2
4
10
12
CDA
VCC
GND
DAT1
Card Detect
AT91SAM9M10-EKES User Guide
Connectors
6.9
SD/MMC- MCI1
Connector J5 is the SD/MMC connector.
Figure 6-9.
SD/MMC1 Connector J5
Table 6-9. SD/MMC1 Connector J5 Signal Descriptions
Pin
1
Mnemonic
RSV/DAT3
Pin
2
Mnemonic
CMD
VCC
11
13
7
9
3
5
GND
CLK
DAT0
DAT2
DAT4
DAT6
4
6
8
10
12
14
DAT1
DAT3
DAT5
DAT7
6.10
AC97
Connector J7 is the Headphone connector.
Connector J8 is the Line In connector.
Connector J9 is the Line In connector.
Connector JP15 is the Speaker Output connector
Figure 6-10. Audio Connector J7, J8, J9
Table 6-10. J7, J8, J9 Signal Description
Pin Mnemonic
Central pin Signal
AT91SAM9M10-EKES User Guide 6-7
11029A–ATARM–11-Jan-10
Connectors
Table 6-11. Speaker JP15 Signal Descriptions
Pin Mnemonic
1
2
Speaker bridge output A
Speaker bridge output B
6.11
Image Sensor - ISI
Connector J17 is the ISI connector.
Figure 6-11. ISI Connector J17
6-8
11029A–ATARM–11-Jan-10
Table 6-12. ISI Connector J17 Signal Descriptions
Pin
1
Mnemonic
VCC 3v3
Pin
2
Mnemonic
Gnd
19
21
23
25
27
29
11
13
15
17
7
9
3
5
VCC 3v3
Ctrl1
SCL
Gnd
Gnd
Gnd
Gnd
Gnd
ISI_Data1
ISI_Data3
ISI_Data5
ISI_Data7
ISI_Data9
ISI_Data11
20
22
24
26
28
30
12
14
16
18
8
10
4
6
Gnd
Ctrl2
SDA
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI_Data0
ISI_Data2
ISI_Data4
ISI_Data6
ISI_Data8
ISI_Data10
Gnd
AT91SAM9M10-EKES User Guide
6.12
Video
Connector J20 is the Video connector
Figure 6-12. Video Connector J20
Table 6-13. Video Connector J20 Signal Description
Pin Mnemonic Signal description
1 Center Composite video signal output
6.13
Display Devices
6.13.1
LG TFT LCD LG/PHILIPS
Connector J24 is the TFT-LCD connector.
Figure 6-13. TFT LCD Connector J24
Connectors
Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
Pin
1
Mnemonic
GND
Pin
2
Mnemonic
GND
7
9
3
5
VDD 3V3
R0
R2
R4
4
6
8
10
VDD 3V3
R1
R3
R5
AT91SAM9M10-EKES User Guide 6-9
11029A–ATARM–11-Jan-10
Connectors
Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
Pin Mnemonic Pin Mnemonic
35
37
39
41
27
29
31
33
43
45
19
21
23
25
11
13
15
17
B6
GND
DISPON
NO CONNECT
VDD PWR SEL
X1
X2
GND
VLED+
NO CONNECT
G6
B0
B2
B4
R6
G0
G2
G4
36
38
40
42
44
20
30
32
34
20
14
16
18
12
14
16
18
B7
DCLK
NO CONNECT
LCDEN
GND
Y1
Y2
VLED-
NO CONNECT
G7
B1
B3
B5
R7
G1
G3
G5
6.14
Large LCD Extension
Connectors J23 and J18 are for an optional large LCD extension (not populated).
6-10
11029A–ATARM–11-Jan-10
Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin
1 PE8
Mnemonic
RED Data Signal
Pin
2 PE7
11
13
15
17
7
9
3
5
19
21
23
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
RED Data Signal
RED Data Signal
RED Data Signal (MSB)
GREEN Data Signal
GREEN Data Signal
GREEN Data Signal
GREEN Data Signal (MSB)
BLUE Data Signal
BLUE Data Signal
BLUE Data Signal
BLUE Data Signal (MSB)
12
14
16
18
8
10
4
6
20
22
24
PE9
PE11
PE13
PE15
PE17
PE19
PE21
PE23
PE25
PE27
PE29
Mnemonic
RED Data Signal (LSB)
RED Data Signal
RED Data Signal
RED Data Signal
GREEN Data Signal (LSB
GREEN Data Signal
GREEN Data Signal
GREEN Data Signal
BLUE Data Signal (LSB)
BLUE Data Signal
BLUE Data Signal
BLUE Data Signal
AT91SAM9M10-EKES User Guide
Connectors
Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin Mnemonic Pin
33
35
37
39
25
27
29
31
PE4
PE5
GND
PE6
PE0
PD14
GND
VCC
LCDHSYNC 26
LCDDOTCK 28
(0V)
LCDDEN
30
32
DISPON
GPIO1
(0V)
+3V3 power source
34
36
38
40
PE3
GND
NC
PE2
PE1
PD15
GND
NC
Mnemonic
LCDVSYNC
(0V)
LCDCC
LCDMOD
GPIO2
(0V)
Table 6-16. Connector J18 Signal Description for a Large LCD Extension
Pin
1 XM AD1XM
Mnemonic Pin
2 XP AD0XP
Mnemonic
11
13
15
17
19
7
9
3
5
YM
GND
PD25
PD27
PD19
GND
GND
GND
VCC
AD3YM
(0V)
PD25
PD27
PD19
(0V)
(0V)
(0V)
+3V3 power source
12
14
16
18
20
8
10
4
6
YP
GND
PD24
PD26
PD18
GND
GND
VCC
AD2YP
(0V)
PD24
PD26
PD18
(0V)
+5V
(0V)
+3V3 power source
AT91SAM9M10-EKES User Guide 6-11
11029A–ATARM–11-Jan-10
7.1
Schematics
This section contains the following schematics:
Top Level view, block architecture of the design
Power Supply
SAM Processor
Bus impedance adaptor
Main memory
EBI memory
MCI & TWI
Audio AC97
Serial interfaces
Ethernet
LCD
Video interfaces and LCD extension
Section 7
Schematics
AT91SAM9M10-EKES User Guide 7-1
11029A–ATARM–11-Jan-10
D
C
B
A
8 7 6 5 4 3 2 1
POWER SUPPLY
POWER
3V3
1V8
1V
EB0 DRR2 INTERFACE
EB0 DRR2 INTERFACE
PIO
DBGU
COM1
Sheet 2
RES.ARRAYS
EBI0_EBI1 ADAPTER
Sheet 5
NOTE
"DNP" means the component is not populated by default
8
HOST
HOST
DEVICE
ICE
INTERFACE
Sheet 9
PIO
10/100 FAST
ETHERNET
PIO
PIO A,...E
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
MCI0_CK
MCI0_CDA
MCI0_DA0
MCI0_DA1
(MCI0_DA2)
(MCI0_DA3)
TXD2
TXD3
RXD2
RXD3
TXD0
TXD1
RXD0
RXD1
TX_EN
RX_DV
Sheet 10
PIO
CONNECTOR
LCD INTERFACE
4.3"
480x272
TFT
TOUCH SCREEN
ISI
CAMERA
INTERFACE
TV
INTERFACE
Sheet 11 12
PIO
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
RX_ER
TX_CLK
MDC
MDIO
TWDO
TWCK0
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4 / TX_ER
MCI1_DA5 / RX_CLK
MCI1_DA6 / CRS
MCI1_DA7 / COL
MCI1_CK
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
TXD1
RXD1
BP5_LEFT
BP4_RIGHT
ISI_D8
ISI_D9
ISI_D10
ISI_D11
DRXD
DTXD
BP3_LEFT
BP3_RIGHT
EB1 DATA INTERFACE
ATMEL
ARM9 Processor
SAM9M10 or SAM9G45
(LFBGA324)
EB1 ADRESSE INTERFACE
EB1 BUS INTERFACE
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PIO MUXING
BP3_UP
BP3_DOWN
BP3_PUSH
VBUS
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
Sheet 3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
NOT USED
NOT USED
A19
A20
NANDALE / A21
NANDCLE
NOT USED
NOT USED
RDY/BSY
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NCS3
NOT USED
PIO A,...E
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
Sheet 4
AUDIO
Sheet 8
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
USER_LED_D6
ENA
FLGA
ENB
FLGB
MDINTR
AC97RX
AC97TX
AC97FS
AC97CK
MCI0_CD
(MCI1_CD)
CTRL1
CTRL2
GPIO1
GPIO2
EB1 DRR2 INTERFACE
EB1 FASH INTERFACE
EB1 NANDFASH INTERFACE
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
RTS1
CTS1
J18_12
J18_11
AD0Xp
AD1Xm
AD2Yp
AD3Ym
J18_8
J18_7
J18_10
J18_9
IDUSB
(MCI1_WP)
POWER LED
USER_LED_D7
7 6 5 4 3
Sheet 6
CARD
READER
CARD
READER
SERIAL
EEPROM
SERIAL
DATA
FLASH
Sheet 7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
LCDPWR
LCDMOD
LCDCC
VSYNC
HSYNC
LCDDOTCK
LCDDEN
R0
R1
R2
R3
R4
R5
R6
R7
G0
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
G5
G6
G7
B0
G1
G2
G3
G4
B1
B2
B3
B4
B5
B6
B7
EXT_CLK
G5
G6
G7
B0
G1
G2
G3
G4
B1
B2
B3
B4
B5
B6
B7
EXT_CLK
G5
G6
G7
B0
G1
G2
G3
G4
B1
B2
B3
B4
B5
B6
B7
EXT_CLK
AT91SAM9G45-EKES
TOP LEVEL
2
E
D
C
B
E
D
C
B
E
D
C
B
A
REV
SCALE
INIT EDIT
MODIF.
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
1
12
1
A
C
B
D
D
1
2
8
D2
5V
R2
100K
5V
7
C2
2.2uF
3
4
11
7
10
15
VIN1
VIN2
SHDN
NC1
NC2
NC3
6
C1
180nF
1
SW1
SW2
FB
6
5
12
5
2
3V3
C4
10uF
C6
2.2nF
C
{3} SHDN
FORCE
POWER
ON
1
2
3
6
5
5V
4
5V
C10
2.2uF
11
7
10
15
3
4
VIN1
VIN2
SHDN
NC1
NC2
NC3
C9
180nF
1
SW1
SW2
FB
6
5
12
2
1V8
C12
10uF
C15
2.2nF
R5
10K
B
R126
10K
USER INTERFACE
3V3
R12
470R
3V3
PB15
PB16
A
3
1
Q2
IRLML2402
2
POWER LED
8
R15
470K
PD30 {3}
{3} PB[14..18]
7
PB14
PB18
PB17
3V3
C18
2.2uF
C16
1uF
6 3
C17
1uF
4 8
5
C1M
VIN
C1P C2M C2P
VOUT
7
C19
10pF
R6
68K
1
EN GND
9
FB
10
PG
2
1V
C22
22uF
LEFT
PUSH
1
2
3
JOYSTICK
4
5
6
UP
RIGHT
DOWN
R141
100R
6
PD0 {3}
PD31 {3}
NRST
WAKE UP
RIGHT CLICK
LEFT CLICK
5
4
3V3
3
C13
2.2uF
1V
1V8
R142
100R
R143
100R
VDDBU
R13
100K
3V3
R14
1K
NRST {3,7,8,9,10,12}
WAKE UP {3}
PB7 {3}
ADHESIVE FEET
GND TEST POINT
PB6 {3}
4 3
2
1 2
1
VDDUTMII {3}
VDDANA {3}
R1
1R
C5
4.7uF
C3
100nF
VDDOSC {3}
D
R3
1R
C8
4.7uF
C7
100nF
1
1
1
1V VDDUTMIC
C14
2.2uF
3 4
3
3
3
7
R7
1R
C21
4.7uF
C20
100nF
8
VDDIOP0 {3}
VDDIOP1 {3}
VDDIOP2 {3,12}
VDDISI {3,12}
VDDUTMIC {3}
VDDPLLUTMI {3}
C
VDDPLLA {3}
R9
1R
C24
4.7uF
C23
100nF
5 6
VDDCORE {3}
B
1
1
3
3
VDDIOM0 {3}
VDDIOM1 {3}
3V3
1 3
C25
100nF
VDDBU
VDDBU {3}
AT91SAM9M10-EKES
AT91SAM9G45-EKES
POWER SUPPLY
2
E
D
C
B
A
REV
SCALE
INIT EDIT
MODIF.
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
2
12
1
A
D
8
{7,10,12} PA[0..31]
7
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
U3
U2
R4
V1
R3
T2
T3
U1
R2
P4
T1
P5
N5
N6
R1
P3
L7
N2
M5
P1
N3
P2
M6
N4
L6
M2
M3
M4
L1
M1
L5
N1
PA0/MCI0_CK/TCLK3
PA1/MCI0_CDA/TIOA3
PA2/MCI0_DA0/TIOB3
PA3/MCI0_DA1/TCKL4
PA4/MCI0_DA2/TIOA4
PA5/MCI0_DA3/TIOB4
PA6/MCI0_DA4/ETX2
PA7/MCI0_DA5/ETX3
PA8/MCI0_DA6/ERX2
PA9/MCI0_DA7/ERX3
PA10/ETX0
PA11/ETX1
PA12/ERX0
PA13/ERX1
PA14/ETXEN
PA15/ERXDV
PA16/ERXER
PA17/ETXCK
PA18/EMDC
PA19/EMDIO
PA20/TWD0
PA21/TWCK0
PA22/MCI1_CDA/SCK3
PA23/MCI1_DA0/RTS3
PA24/MCI1_DA1/CTS3
PA25/MCI1_DA2/PWM3
PA26/MCI1_DA3/TIOB2
PA27/MCI1_DA4/ETXER
PA28/MCI1_DA5/ERXCK
PA29/MCI1_DA6/ECRS
PA30/MCI1_DA7/ECOL
PA31/MCI1_CK/PCK0
C
B
{4} EBI0_D[0..15]
{4} EBI0_A[0..13]
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{5,6}
EBI0_CKE
EBI0_CLK
EBI0_NCLK
EBI0_CS
EBI0_CAS
EBI0_RAS
EBI0_WE
DDR_VREF
{4}
{4}
EBI0_DQM0
EBI0_DQM1
{4}
{4}
EBI0_BA0
EBI0_BA1
EBI0_DQS0
EBI0_DQS1
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
N15
N16
P18
N17
N18
N14
M15
M16
R16
R15
T14
P15
P16
P17
R14
P14
EBI0_DDR_D0
EBI0_DDR_D1
EBI0_DDR_D2
EBI0_DDR_D3
EBI0_DDR_D4
EBI0_DDR_D5
EBI0_DDR_D6
EBI0_DDR_D7
EBI0_DDR_D8
EBI0_DDR_D9
EBI0_DDR_D10
EBI0_DDR_D11
EBI0_DDR_D12
EBI0_DDR_D13
EBI0_DDR_D14
EBI0_DDR_D15
K15
K16
K18
K17
J14
J15
M17
L14
M18
L15
L16
L18
L17
K14
EBI0_DDR_A0
EBI0_DDR_A1
EBI0_DDR_A2
EBI0_DDR_A3
EBI0_DDR_A4
EBI0_DDR_A5
EBI0_DDR_A6
EBI0_DDR_A7
EBI0_DDR_A8
EBI0_DDR_A9
EBI0_DDR_A10
EBI0_DDR_A11
EBI0_DDR_A12
EBI0_DDR_A13
G17
G16
EBI0_DDR_BA0
EBI0_DDR_BA1
J16
J18
H18
H14
H17
J17
H15
EBI0_DDR_CKE
EBI0_DDR_CLK
EBI0_DDR_NCLK
EBI0_DDR_CS
EBI0_DDR_CAS
EBI0_DDR_RAS
EBI0_DDR_WE
A16
EBI0_DDR_VREF
G14
H16
EBI0_DDR_DQM0
EBI0_DDR_DQM1
G18
G15
EBI0_DDR_DQS0
EBI0_DDR_DQS1
A
8 7
6 5 4 3
PB[0..31] {2,7,9,12}
PB0/SPI0_MISO
PB1/SPI0_MOSI
PB2/SPI0_SPCK
PB3/SPI0_NPCS0
PB4/TXD1
PB5/RXD1
PB6/TXD2
PB7/RXD2
PB8/TXD3/ISI_D8
PB9/RXD3/ISI_D9
PB10/TWD1/ISI_D10
PB11/TWCK1/ISI_D11
PB12/DRXD
PB13/DTXD
PB14/SPI1_MISO
PB15/SPI1_MOSI/CTS0
PB16/SPI1_SPCK/SCK0
PB17/SPI1_NPCS0/RTS0
PB18/RXD0/SPI0_NPCS1
PB19/TXD0/SPI0_NPCS2
PB20/ISI_D0
PB21/ISI_D1
PB22/ISI_D2
PB23/ISI_D3
PB24/ISI_D4
PB25/ISI_D5
PB26/ISI_D6
PB27/ISI_D7
PB28/ISI_D8
PB29/ISI_VSYNC
PB30/ISI_HSYNC
PB31/ISI_MCK/PCK1
T6
U6
N7
P7
P6
R6
M7
V5
R5
V4
T5
U5
T4
V2
V3
U4
T12
N11
U13
M11
P12
T15
R12
T16
N12
M12
U14
M13
N13
R13
T13
P13
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
{4,6}
{6}
{6}
PC[2..5]
PC8
PC14
PC8
PC14
PC2
PC3
PC4
PC5
EBI1_NBS0/A0
EBI1_NBS2/NWR2/A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_BA0/A16
EBI1_BA1/A17
EBI1_A18
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
EBI1_RAS
EBI1_CAS
EBI1_SDWE
EBI1_SDA10
EBI1_SDCKE
EBI1_SDCK
EBI1_NSDCK
EBI1_NCS0
EBI1_NCS1/SDCS
EBI1_NRD/CFOE
EBI1_NWE/NWR0/CFWE
EBI1_NBS1/NWR1/CFIOR
EBI1_NBS3/NWR3/CFIOW
EBI1_NANDOE
EBI1_NANDWE
A13
A14
A10
F10
F11
C9
D9
A9
D10
E10
B11
D11
A11
E11
A12
C11
F12
B9
B12
E15
E16
D18
D17
C18
B18
A18
B17
F13
F14
F18
F15
E14
F17
F16
E17
C10
B10
C17
B14
D13
C13
E13
B13
E12
D12
C12
A17
D15
C15
B16
B15
D14
C14
A15
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
EBI1_A0
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_A16
EBI1_A17
EBI1_A18
EBI1_D[0..15] {4}
EBI1_A[1..18] {4}
EBI1_A0
EBI1_DQM0 {4}
EBI1_DQM1 {4}
EBI1_DQS0 {4}
EBI1_DQS1 {4}
EBI1_RAS {4}
EBI1_CAS {4}
EBI1_SDWE {4}
EBI1_SDA10 {4}
EBI1_SDCKE {4}
EBI1_SDCK {4}
EBI1_NSDCK {4}
EBI1_NCS0 {6}
EBI1_NCS1/SDCS {4}
EBI1_NRD/CFOE {6}
EBI1_NWE/NWR0/CFWE
EBI1_NANDOE {6}
EBI1_NANDWE {6}
{6}
{2}
{9}
{9}
{9}
{9}
HDPA
HDMA
HDPB
HDMB
VDDOSC
{9}
{9}
{9}
{9}
{9}
{9}
{2,7,8,9,10,12}
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
A2
B2
B3
B1
D5
A3
C4
A1
A4
C5
B4
E6
E7
B5
D6
F7
A5
D7
F8
C6
E8
C7
B6
B7
F9
A7
D8
A6
A8
E9
B8
C8
PC16/D16
PC17/D17
PC18/D18
PC19/D19
PC20/D20
PC21/D21
PC22/D22
PC23/D23
PC24/D24
PC25/D25
PC26/D26
PC27/D27
PC28/D28
PC29/D29
PC30/D30
PC31/D31
PC0/DQM2
PC1/DQM3
PC2/A19
PC3/A20
PC4/A21/NANDALE
PC5/A22/NANDCLE
PC6/A23
PC7/A24
PC8/CFCE1
PC9/CFCE2/RTS2
PC10/NCS4/CFCS0/TCLK2
PC11/NCS5/CFCS1/CTS2
PC12/A25/CFRNW
PC13/NCS2
PC14/NCS3/NANDCS
PC15/NWAIT
C34
18pF
C38
18pF
C41
15pF
C45
15pF
VDDBU
{2}
NTRST
{2}
TDI
TMS
TCK
TDO
SHDN
C32
R16 39R
R17 39R
R18 39R
R19 39R
100nF
RTCK
NRST
WAKE UP
Y2
PD0/TK0/PWM3
PD1/TF0
PD2/TD0
PD3/RD0
PD4/RK0
PD5/RF0
PD6/AC97RX
PD7/AC97TX/TIOA5
PD8/AC97FS/TIOB5
PD9/97CK/TCLK5
PD10/TD1
PD11/RD1
PD12/TK1/PCK0
PD13/RK1
PD14/TF1
PD15/RF1
PD16/RTS1
PD17/CTS1
PD18/SPI1_NPCS2/IRQ
PD19/SPI0_NPCS3/FIQ
PD20/TIOA0
PD21/TIOA1
PD22/TIOA2
PD23/TCLK0
PD24/SPI0_NPCS1/PWM0
PD25/SPI0_NPCS2/PWM1
PD26/PCK0/PWM2
PD27/PCK1/SPI0_NPCS3
PD28/TSADTRG/SPI1_NPCS1
PD29/TCLK1/SCK1
PD30/TIOB0/SCK2
PD31/TIOB1/PWM1
F2
G1
H1
H2
P9
L10
T10
L11
D2
E1
F1
G2
N9
V9
R9
T9
V8
L9
U9
M9
P8
R8
U8
T8
M8
V7
N8
U7
R7
T7
L8
V6
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD27
PD28
PD29
PD30
PD31
32.768 kHz
T18
R18
T17
R17
V15
V16
U15
U16
U11
U12
V12
HFSDPA
HFSDMA
HHSDPA
HHSDMA
DFSDP/HFSDPB
DFSDM/HFSDMB
DHSDP/HHSDPB
DHSDM/HHSDMB
VDDOSC
GNDOSC
XIN
V11
C1
XOUT
XIN32
D1
XOUT32
E4
N10
R10
P10
U10
R11
V10
M10
F3
JTAGSEL
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
SHDN
3V3
2
{8,11,12} PE[0..31]
PD[0..31] {2,7,8,9,10,11,12}
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
VDDBU
GNDBU
VDDPLLUTMI
VDDUTMIC
GNDUTMI
VDDUTMII
D4
D3
V13
U18
U17
V17
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP2
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
K9
K10
H3
V14
E18
G12
G13
H11
K13
L12
L13
M14
D16
F6
G10
G11
VDDPLLA
P11
TSADVREF
VDDANA
E2
E3
GNDANA
C2
C26
C29
100nF
C27 100nF
C28 100nF
100nF
C30
C31
C36
C39
C44
C47
100nF
100nF
100nF
100nF
0R R21
C52
100nF
C53
100nF
1
K8
L3
L2
L4
K5
K6
K3
K7
J8
K1
K4
K2
J2
J6
J7
J1
J5
H4
J3
J4
G6
H7
H8
G8
G7
H5
G3
H6
G4
F4
G5
F5
PE0/LCDPWR/PCK0
PE1/LCDMOD
PE2/LCDCC
PE3/LCDVSYNC
PE4/LCDHSYNC
PE5/LCDDOTCK
PE6/LCDDEN
PE7/LCDD0/LCDD2
PE8/LCDD1/LCDD3
PE9/LCDD2/LCDD4
PE10/LCDD3/LCDD5
PE11/LCDD4/LCDD6
PE12/LCDD5/LCDD7
PE13/LCDD6/LCDD10
PE14/LCDD7/LCDD11
PE15/LCDD8/LCDD12
PE16/LCDD9/LCDD13
PE17/LCDD10/LCDD14
PE18/LCDD11/LCDD15
PE19/LCDD12/LCDD18
PE20/LCDD13/LCDD19
PE21/LCDD14/LCDD20
PE22/LCDD15/LCDD21
PE23/LCDD16/LCDD22
PE24/LCDD17/LCDD23
PE25/LCDD18
PE26/LCDD19
PE27/LCDD20
PE28/LCDD21
PE29/LCDD22
PE30/LCDD23
PE31/PWM2/PCK1
VDDBU {2}
VDDPLLUTMI {2}
VDDUTMIC {2}
VDDUTMII {2}
VDDIOP0 {2}
VDDIOP1 {2}
VDDIOP2 {2,12}
VDDCORE {2}
VDDIOM0 {2}
VDDIOM1 {2}
VDDPLLA {2}
VDDANA {2}
D
C
B
6 5
DNP
SG-BGA-CA89405MF
BOOT MODE SELECT
Opened
Closed
=
=
Internal ROM BOOT
NCS0
4
R25
4.7K
3
AT91SAM9G45-EKES
SAM9 chip
E
D
C
B
A
REV
SCALE
INIT EDIT
MODIF.
1/1
2
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
3
12
1
A
C
B
D
6 8 7
EBI Bus Impedance Adaptor
{3} EBI1_D[0..15]
{3} EBI0_D[0..15] DDR_D[0..15] {5}
EBI0
2
1
3
2
3
4
4
2
1
2
1
4
4
3
1
3
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
7
8
6
7
6
5
5
7
8
7
8
5
5
6
8
6
DDR_A[0..13] {5}
{3} EBI0_A[0..13]
3
4
2
1
4
3
1
2
3
2
1
3
4
2
4
1
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
6
5
7
8
5
6
8
7
6
7
8
6
5
7
5
8
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
1
2
3
4
3
4
1
2
1
2
1
2
4
3
3
4
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
2
3
4
3
4
2
1
1
4
3
2
1
4
3
2
1
{3} EBI0_CKE
{3} EBI0_CLK
{3} EBI0_NCLK
{3} EBI0_BA0
{3} EBI0_BA1
{3} EBI0_WE
{3} EBI0_CS
4
1
3
2
R26 27R
R27 27R
R28 27R
5
8
6
7
DDR_CKE {5}
DDR_CLK {5}
DDR_NCLK {5}
DDR_BA0 {5}
DDR_BA1 {5}
DDR_WE {5}
DDR_CS {5}
{3} EBI1_SDCKE
{3} EBI1_SDCK
{3} EBI1_NSDCK
EBI1_A16
EBI1_A17
{3} EBI1_NCS1/SDCS
{3} EBI1_SDWE
A
{3} EBI0_RAS
{3} EBI0_CAS
{3} EBI0_DQM0
{3} EBI0_DQM1
3
4
1
2
6
5
8
7
DDR_RAS {5}
DDR_CAS {5}
DDR_DQM0 {5}
DDR_DQM1 {5}
{3} EBI1_RAS
{3} EBI1_CAS
{3} EBI1_DQM0
{3} EBI1_DQM1
{3} EBI0_DQS0
{3} EBI0_DQS1
R32 27R
R33 27R
DDR_DQS0 {5}
DDR_DQS1 {5}
{3} EBI1_DQS0
{3} EBI1_DQS1
{3} EBI1_SDA10
SDA10
8 7 6
5
2
3
4
1
1
3
2
1
8
7
6
5
6
5
8
7
8
7
8
7
5
6
6
5
7
6
5
6
5
7
8
8
5
6
7
8
5
6
7
8
EBI1_FLASH_D0
EBI1_NAND_FSH_D0
EBI1_FLASH_D1
EBI1_NAND_FSH_D1
EBI1_FLASH_D2
EBI1_NAND_FSH_D2
EBI1_FLASH_D3
EBI1_NAND_FSH_D3
EBI1_FLASH_D4
EBI1_NAND_FSH_D4
EBI1_FLASH_D5
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_FLASH_D7
EBI1_NAND_FSH_D7
EBI1_FLASH_D8
EBI1_NAND_FSH_D8
EBI1_FLASH_D9
EBI1_NAND_FSH_D9
EBI1_FLASH_D10
EBI1_NAND_FSH_D10
EBI1_FLASH_D11
EBI1_NAND_FSH_D11
EBI1_FLASH_D12
EBI1_NAND_FSH_D12
EBI1_FLASH_D13
EBI1_NAND_FSH_D13
EBI1_FLASH_D14
EBI1_NAND_FSH_D14
EBI1_FLASH_D15
EBI1_NAND_FSH_D15
R29 27R
R30 27R
R31 27R
R34 27R
R35 27R
8
6
7
8
7
6
5
8
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
4
1
2
3
2
1
4
3
3
1
2
4
1
3
2
4
4
CAUTION
6
7
5
8
Pin assignemts at
PCB layout time
EBI1_FLASH_D[0..15]
CKE_EBI1 {6}
CLK_EBI1 {6}
NCLK_EBI1 {6}
BA0_EBI1 {6}
BA1_EBI1 {6}
CS_EBI1 {6}
WE_EBI1 {6}
RAS_EBI1 {6}
CAS_EBI1 {6}
DQM0_EBI1 {6}
DQM1_EBI1 {6}
5
8
7
8
5
6
6
8
7
6
7
5
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
{6}
{3} EBI1_A[1..18]
{3}
{3}
PC2
PC3
{3,6} PC4
3
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
2
EBI1_DDR_D[0..15] {6}
EBI1_NAND_FSH_D[0..15] {6}
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
SDA10
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
3
4
1
4
1
2
3
4
1
4
3
2
4
2
4
4
3
3
3
2
1
1
2
2
3
4
1
2
4
1
2
3
6
5
8
5
8
7
6
5
8
5
6
7
5
7
5
5
6
6
6
7
8
8
7
7
6
5
8
7
5
8
7
6
EBI1_A16
EBI1_A17
(A19)
(A20)
(A21)
EBI1_A18 1
2
3
4
8
7
6
5
EBI1_FLASH_A1
EBI1_DDR_A2
EBI1_FLASH_A2
EBI1_DDR_A3
EBI1_FLASH_A3
EBI1_DDR_A4
EBI1_FLASH_A4
EBI1_DDR_A5
EBI1_FLASH_A5
EBI1_DDR_A6
EBI1_FLASH_A6
EBI1_DDR_A7
EBI1_FLASH_A7
EBI1_DDR_A8
EBI1_FLASH_A8
EBI1_DDR_A9
EBI1_FLASH_A9
EBI1_DDR_A10
EBI1_FLASH_A10
EBI1_DDR_A11
EBI1_FLASH_A11
EBI1_DDR_A12 (SDA10)
EBI1_FLASH_A12
EBI1_DDR_A13
EBI1_FLASH_A13
EBI1_DDR_A14
EBI1_FLASH_A14
EBI1_DDR_A15
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
DQS0_EBI1 {6}
DQS1_EBI1 {6}
B
A
E
D
C
E
B
A
D
C
B
A
E
D
C
4 3
AT91SAM9G45-EKES
RES.ARRAYS-EBI0_EBI1
2
1
EBI1_FLASH_A[1..21] {6}
EBI1
EBI1_DDR_A[2..15] {6}
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
E
4
12
1
D
C
B
A
5
8
D
{4} DDR_D[0..15]
{4} DDR_A[0..13]
7 6 5 4 3 2 1
C
B
A
8
{4}
{4}
DDR_BA0
DDR_BA1
{4} DDR_CKE
{4}
{4}
DDR_CLK
DDR_NCLK
{4} DDR_CS
{4}
{4}
DDR_CAS
DDR_RAS
{4} DDR_WE
BA0
BA1
CKE
CK
NCK
CS
CAS
RAS
NWE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
K8
K3
H2
K7
L2
L8
J8
J3
J7
K2
H8
H3
H7
J2
G2
G3
A8
A9
A10
A11
A12
A13
A4
A5
A6
A7
A0
A1
A2
A3
BA0
BA1
F9
ODT
F2
E8
F8
CKE
CK
CK
G8
G7
F7
F3
CS
CAS
RAS
WE
G1
L3
L7
RFU1
RFU2
RFU3
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VSSDL
B7
A8
B3
A2
A1
E9
H9
L1
D1
D9
B1
B9
C8
C2
D7
D3
E1
A9
C1
C3
C7
C9
A7
B2
B8
D2
D8
E7
E2
A3
E3
J1
K9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
1V8
DDR_VREF
DDR_DQS0 {4}
DDR_DQM0 {4}
C55 100nF
C57 100nF
C59 100nF
C61 100nF
C63 100nF
C65 100nF
C67 100nF
C69 100nF
C71 100nF
C73 100nF
C75
100nF
BA0
BA1
CKE
CK
NCK
CS
CAS
RAS
NWE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
K8
K3
H2
K7
L2
L8
J8
J3
J7
K2
H8
H3
H7
J2
G2
G3
A8
A9
A10
A11
A12
A13
A4
A5
A6
A7
A0
A1
A2
A3
BA0
BA1
F9
ODT
F2
E8
F8
CKE
CK
CK
G8
G7
F7
F3
CS
CAS
RAS
WE
G1
L3
L7
RFU1
RFU2
RFU3
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VSSDL
B7
A8
B3
A2
A1
E9
H9
L1
D1
D9
B1
B9
C8
C2
D7
D3
E1
A9
C1
C3
C7
C9
A7
B2
B8
D2
D8
E7
E2
A3
E3
J1
K9
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
1V8
DDR_VREF
DDR_DQS1 {4}
DDR_DQM1 {4}
C56 100nF
C58 100nF
C60 100nF
C62 100nF
C64 100nF
C66 100nF
C68 100nF
C70 100nF
C72 100nF
C74 100nF
C76
100nF
1V8
R36
1R
C78
4.7uF
C77
100nF
C79
100nF
DDR_VREF
DDR_VREF {3,6}
7 6 5 4 3
EBI0_DDR2
2
B
A
E
D
C
E
B
A
D
C
B
A
E
D
C
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
E
5
12
1
A
C
B
D
D
C
8
{4} EBI1_FLASH_D[0..15]
{4} EBI1_FLASH_A[1..21]
{4} EBI1_DDR_D[0..15]
{4} EBI1_DDR_A[2..15]
7 6
{4}
{4}
BA0_EBI1
BA1_EBI1
{4} CKE_EBI1
{4}
{4}
CLK_EBI1
NCLK_EBI1
{4} CS_EBI1
{4}
{4}
CAS_EBI1
RAS_EBI1
{4} WE_EBI1
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
(SDA10)
K8
K3
H2
K7
L2
L8
J8
J3
J7
K2
H8
H3
H7
J2
BA0_EBI1
BA1_EBI1
G2
G3
A8
A9
A10
A11
A12
A13
A4
A5
A6
A7
A0
A1
A2
A3
BA0
BA1
F9
ODT
CKE_EBI1
CLK_EBI1
NCLK_EBI1
CS_EBI1
CAS_EBI1
RAS_EBI1
WE_EBI1
(NCS1)
F2
E8
F8
CKE
CK
CK
G8
G7
F7
F3
CS
CAS
RAS
WE
G1
L3
L7
RFU1
RFU2
RFU3
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
B7
A8
B3
A2
D1
D9
B1
B9
C8
C2
D7
D3
VREF
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
E1
A9
C1
C3
C7
C9
E2
A1
E9
H9
L1
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
1V8
VREF1
C101
100nF
DQS0_EBI1 {4}
DQM0_EBI1 {4}
C80 100nF
C82 100nF
C84 100nF
C86 100nF
C88 100nF
C90 100nF
C92 100nF
C94 100nF
C96 100nF
C98 100nF
5 4 3 2 1
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
BA0_EBI1
BA1_EBI1
(SDA10)
K8
K3
H2
K7
L2
L8
J8
J3
J7
K2
H8
H3
H7
J2
G2
G3
A8
A9
A10
A11
A12
A13
A4
A5
A6
A7
A0
A1
A2
A3
BA0
BA1
F9
ODT
CKE_EBI1
CLK_EBI1
NCLK_EBI1
CS_EBI1
CAS_EBI1
RAS_EBI1
WE_EBI1
F2
E8
F8
CKE
CK
CK
G8
G7
F7
F3
CS
CAS
RAS
WE
G1
L3
L7
RFU1
RFU2
RFU3
RDQS/DM
RDQS/NU
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
VREF
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
E1
A9
C1
C3
C7
C9
E2
A1
E9
H9
L1
A7
B2
B8
D2
D8
A3
E3
J1
K9
E7
B7
A8
B3
A2
D1
D9
B1
B9
C8
C2
D7
D3
1V8
VREF1
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
C102
100nF
DQS1_EBI1 {4}
DQM1_EBI1 {4}
C81 100nF
C83 100nF
C85 100nF
C87 100nF
C89 100nF
C91 100nF
C93 100nF
C95 100nF
C97 100nF
C99 100nF
{3}
R39 100K
1V8
EBI1_NWE/NWR0/CFWE
{3} EBI1_NRD/CFOE
{3} EBI1_NCS0
{3,5} DDR_VREF
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
1V8
B6
A6
C6
D6
B5
A5
C5
D5
E6
B2
C3
D4
D3
B1
D2
C2
A2
E1
D1
C1
A1
A8
A9
A10
A11
A12
A13
A14
A15
A4
A5
A6
A7
A0
A1
A2
A3
A16
A17
A18
A19
A20
B4
A4
B3
F1
G1
RESET
WE
VPP
CE
OE
F4
G5
F5
G6
F2
G2
F3
G3
H4
E4
H5
E5
E2
H2
E3
H3
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/00
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
RDY/ BUSY
A3
NC1
NC
C4
F6
VCC
GND
GND
G4
H1
H6
1V8
C100
100nF
D
C
R40 470K
1V8
VREF1
B
A
8
{4} EBI1_NAND_FSH_D[0..15]
{3}
{3}
{3}
{3,4}
PC5
PC4
EBI1_NANDOE
EBI1_NANDWE
{3} PC14
{3} PC8
(NANDCLE)
(NANDALE)
(NCS3)
(RDY/BSY)
7
1V8
1V8
R47
DNP
RE
WE
CE
RB
WP
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
D5
C4
D4
C7
C6
C8
C3
G5
CLE
ALE
RE
WE
CE
R/B
WP
LOCK
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
VCC
VCC
VCC
VCC
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
VFBGA-63
MT29F2G08ABDHC:D
VSS
VSS
VSS
VSS
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
C5
F7
K3
K8
D3
G4
H8
J6
L9
L10
M1
M2
M9
M10
H6
G6
H7
G7
H3
J3
H5
J5
K6
J7
K7
J8
H4
J4
K4
K5
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
1V8
C103 100nF
C104 100nF
C105 100nF
C106 100nF
Optional 16bits DATA BUS
With AT29F2G16ABD Micron
6 5 4 3
EBI1_MEMORY
2
B
A
E
D
C
E
B
A
D
C
B
A
E
D
C
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
E
6
12
1
A
B
A
8 7 6 5 4 3 2 1
D
{3}
{3}
PD10
PA[0..5]
PA3
PA2
PA0
PA1
PA5
PA4
(MCI0_CD)
(MCI0_DA1)
(MCI0_DA0)
(MCI0_CK)
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
3V3
R51
10K
RR41
68K
2 3 4
R52
10K
3V3
C109 100nF
2
1
4
3
9
6
5
8
7
C
SD/MMC CARD INTERFACE - MCI0
12
11
10
{3,10}
{3}
{3}
PD29
PD11
PA[22..31]
(MCI1_WP)
(MCI1_CD)
PA24
PA23
PA31
(MCI1_DA1)
(MCI1_DA0)
(MCI1_CK)
PA22
PA26
PA25
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
PA27
PA28
PA29
PA30
(MCI1_DA4)
(MCI1_DA5)
(MCI1_DA6)
(MCI1_DA7)
R192 27R
R193 27R
R194 27R
R195 27R
R196 27R
R197 27R
R198 27R
R199 27R
R200 27R
R201 27R
2 3 4
3V3
2 3 4
RR35
68K
2 3 4
3V3
C108
100nF
2
1
4
3
9
6
5
8
7
SD/MMCPlus CARD INTERFACE - MCI1
16
15
14
13
12
11
10
D
C
B
{3,12}
{3,12}
PA21
PA20
(TWCK0)
(TWDO)
3V3
C111
100nF
6
5
8
SCL
SDA
VCC
4
GND
A0
A1
A3
1
2
3
WP
7
SERIAL EEPROM
R54
10K
3V3
8 7 6
3V3
{3}
{3}
{3}
{3}
PB0
PB1
PB2
PB3
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
{2,3,8,9,10,12} NRST
DNP
Test point
1 3
R53
470K
8
1
2
4
SO
SI
SCK
CS
3
RESET
VCC
GND
7
WP
6
5
SERIAL DATAFLASH
3V3
C110
100nF
R55
DNP
WRITE PROTECT
NORMALLY OPEN
5 4 3
MCI & TWI
2
E
D
C
B
A
E
B
A
D
C
E
D
C
B
A
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
E
7
12
1
A
B
D
C
B
A
8 7
CLOCK SELECTION - PIN STRAPING TABLE
RA=1K RB=1K CODEC ID CLK FREQ
OUT
OUT
IN
IN
OUT
IN
OUT
IN
PRIMARY
SECONDARY
PRIMARY
PRIMARY
24.576 MHz
12.288 MHz
48.000 MHz
14.318 MHz
Local XTAL
Ext. BITCLK
Ext. BITCLK (Into XTAL-IN)
Ext. BITCLK (Into XTAL-IN)
{3} PE31
{3}
{3}
PD7
PD9
{3} PD6
{3}
{2,3,7,9,10,12}
PD8
NRST
(EXT_CLK)
C120 22pF
C123 22pF
(AC97TX)
(AC97CK)
(AC97RX)
(AC97FS)
RA
RB
6
(see table)
R58 DNP
R59 DNP
C122
10uF
10V
C124
100nF
C125
100nF
3V3
7
8
9
10
11
12
5
6
1
2
3
4
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
NC1
AVDD_AC97
5 4 3
C112 100uF
C116
100nF
C117
100nF
C118
10uF
10V
AGND_AC97 C119
1uF
LINE_OUT_R
LINE_OUT_L
AVDD4
AVSS4
AFILT4
AFILT3
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
28
27
26
25
32
31
30
29
36
35
34
33
AVDD_AC97
VREFOUT
1
C134
1uF
3
C127 100nF
C128 270pF
C129 270pF
C130 270pF
C131 270pF
C132 100nF
C133 100nF
AGND_AC97
C113 100uF
R56
1K
R57
1K
L8
742792093
L9
742792093
C114
470pF
R61 22K
AGND_AC97
4
3
AVDD_AC97
R62 22K
C121
10uF
10V
6
C126 100nF
5
C135
100nF
2
1
7
AGND_AC97
8
2
3.5 PHONEJACK STEREO
3
J7
5
2
C115
470pF
1 4
HEADPHONE
LINE-OUT
1
SPEAKER OUTPUT
R63 2.2K
R65 2.2K
8 7
C144
10uF
10V
5V
R73 0R
AVDD_AC97
C146
47uF
6V3
AGND_AC97
WARNING
TO BIAS FROM VREFOUT
CHANGE R71 and R72 to 3k 5%
DO NOT INSTALL R76, R78, C150, C151
VREFOUT MUST BE PROGRAMMED TO 3.7V
USING VREFH BIT (REG 76h)
6
AGND_AC97
5
C136
1uF
C137
1uF
C140 100nF
OPTIONAL VOICE
FILTER COMPONENTS
R69 100R
C141 100nF R70 100R
C142
10nF
C143
10nF
AGND_AC97
R71
3.9K
OPTIONAL MIC BIASING FROM VREFOUT
VREFOUT
4
C150
10uF
10V
C151
10uF
10V
AGND_AC97
R72
3.9K
R67
4.7K
R68
4.7K
AGND_AC97
3
AVDD_AC97
C138
470pF
L14
742792093
C147
470pF
3.5 PHONEJACK STEREO
3
J8
5
2
C139
470pF
1 4
LINE-IN
3.5 PHONEJACK STEREO
3
J9
5
2
C148
470pF
1
C149
470pF
R74
0R
AGND_AC97
4
MONO / STEREO
MICROPHONE INPUT
AT91SAM9M10-EKES
AT91SAM9G45-EKES
AUDIO AC97
2
E
D
C
B
A
REV
E
D
C
B
A
SCALE
INIT EDIT
MODIF.
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
8
12
1
A
B
D
C
8 7
D
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
C155
100nF
C160
100nF
3V3
C153
100nF
16
15
2
6
14
7
13
8
6
1
C156
100nF
C1-
C2+
3
4
5
11
10
12
9
C158
100nF
3V3
R80
100K
R82
100K
PB13 {3}
PB12 {3}
5 4
{3} PB4
{3} PD16
{3} PB5
{3} PD17
3V3
R79
100K
R81
100K
3
1
C152
100nF
C159
100nF
5
11
10
12
9
3
4
C1-
C2+
2
6
14
7
13
8
16
15
2
3V3
C154
100nF
C157
100nF
C161
100nF
1
RS232 COM PORT
1
6
2
7
3
8
4
9
5
D
C
B
A
C162
100nF
1
4
J12
292303-1
5 6
2
3
USB HOST INTERFACE
C167
100nF
C164
33 uF
16V
C165
33 uF
16V
7
6
VBUS
DM
DP
ID
GND
3
4
1
2
5
5V
C163
100nF
8
7
OUTA
IN
ENA
FLGA
1
2
6
5
GNG
OUTB
FLGB
ENB
3
4
C166
10pF
R88 47K
R89
68K
(VBUS)
PB19 {3}
3V3
USB HOST/DEVICE INTERFACE
8
Take note of layout directive
"High speed USB platform design.PDF"
7 6
HDMA {3}
HDPA {3}
(ENA)
(FLGA)
(FLGB)
(ENB)
PD1 {3}
PD2 {3}
PD4 {3}
PD3 {3}
(IDUSB)
HDMB {3}
HDPB {3}
PD28 {3}
5 4
3V3
10
12
14
16
18
20
6
8
2
4
3V3
9
11
13
15
5
7
1
3
17
19
ICE INTERFACE
3V3
RR42
100K
6 7 8
R87
DNP
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST {3}
TDI {3}
TMS {3}
TCK {3}
RTCK {3}
TDO {3}
NRST {2,3,7,8,10,12}
3
AT91SAM9G45-EKES
SERIAL INTERFACES
2
E
D
C
E
D
C
E
D
C
B
A
REV
SCALE
INIT EDIT
MODIF.
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
9
12
1
A
C
B
8 7 6 5 4 3 2 1
D
C
B
A
3V3
{3} PA17
{3}
{3}
{3}
{3}
{3}
PA7
PA6
PA11
PA10
PA14
{3}
{3}
{3}
{3}
PA9
PA8
PA13
PA12
{3,7}
{3}
PA28
PA15
{3,7}
{3}
PA27
PA16
{3,7}
{3,7}
PA30
PA29
{3}
{3}
{3}
PA18
PA19
PD5
(TX_CLK)
(TXD3)
(TXD2)
(TXD1)
(TXD0)
(TX_EN)
(RXD3)
(RXD2)
(RXD1)
(RXD0)
(RX_CLK)
(RX_DV)
(TX_ER)
(RX_ER)
(COL)
(CRS)
(MDC)
(MDIO)
(MDINTR)
R104
R107
{2,3,7,8,9,12} NRST
1
2
2 3 4
RR43
10K
2 3 4
RR44
10K
3V3
2 3 4
RR45
10K
4
3
3V3
R92
0R
C168
100nF
C169
18pF
4
1
3
2
C170
18pF
C171
100nF
GND_ETH
3V3
42
17
18
19
20
21
22
34
37
16
38
26
27
28
29
36
35
24
25
32
39
REF_CLK/XT2
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
RX_CLK/10BTSER
RX_DV/TESTMODE
TX_ER/TXD4
RX_ER/RXD4/RPTR
COL/RMII
CRS/PHYAD4
MDC
MDIO
MDINTR
DISMDIX
41
30
23
15
33
44
10
40
DVDD
DVDD
DVDD
DGND
DGND
DGND
PWRDWN
RESET
XT1
TX+
TX-
RX+
RX-
AVDDR
AVDDR
AVDDT
AGND
AGND
AGND
BGRESG
43
7
8
3
4
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
N.C
48
31
11
12
13
14
45
1
C172 100nF
2
9
AVDDT
5
6
46
47
C178
R185 0R
100nF
L17
742792093
C175
10uF
3V3
GND_ETH
RR46
10K
2 3 4
AVDDT
R105
49R9
1%
C176
10uF
R96
49R9
1%
R97
49R9
1%
AVDDT
R106
49R9
1%
C173
100nF
C177
100nF
GND_ETH
7
8
3
5
6
4
2
1
J15
TD+
GND_ETH
3V3
RJ45 ETHERNET CONNECTOR
FULL DUPLEX
SPEED 100
LINK&ACT
R114 0R
3V3
C182
10uF
10V
R115 0R
GND_ETH
Take note of layout directive
"DM9161-LG-V11-011401S.PDF"
8 7 6 5 4 3
AT91SAM9G45-EKES
RMII ETHERNET
C
B
A
REV
B
A
E
D
C
E
D
B
A
D
C
SCALE
INIT EDIT
MODIF.
1/1
2
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
10
12
1
A
D
C
B
D
C
B
A
8
8
4.3" 480x272
TFT LCD DISPLAY
7
VLED+
D12
STPS0540Z
C202
1uF
VLED-
1
FB
MN25 TPS61161DRVT
VIN
6
CTRL
COMP
5
2
5V
C201
2.2uF
(LCDCC)
C203
220nF
R137
10K
PE2
20mA MAX 9 LEDs Back Light
7
6 5
(pinxx = display pin number )
29
30
31
32
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
37
38
39
40
33
34
35
36
41
42
43
44
45 pin34 pin33 pin32 pin31 pin30 pin29 pin28 pin27 pin26 pin25 pin24 pin23 pin22 pin21 pin20 pin19 pin18 pin17 pin45 pin44 pin43 pin42 pin41 pin40 pin39 pin38 pin37 pin36 pin35 pin16 pin15 pin14 pin13 pin12 pin11 pin10 pin9 pin8 pin7 pin6 pin5 pin4 pin3 pin2 pin1
VLED+
VLED-
YpLCD
XpLCD
YmLCD
XmLCD
3V3
R180
10K
R50 27R
4
1
2
3
4
1
2
3
4
3
4
1
1
2
2
3
3
4
1
2
1
2
3
4
RR49C
RR49D
RR50A
RR50B
5
8
7
6
5
8
7
6
5
6
5
8
8
7
7
6
6
5
8
7
8
7
6
5
C188
100nF
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
C189
10uF
10V
3V3
(LCDDEN)
(LCDPWR)
4
PE25
PE24
PE23
PE16
PE15
PE9
PE8
PE7
This Resistor is intentionally mounted in place of C210
6
C208
DNP
YpLCD
XmLCD
YmLCD
XpLCD
C210
220K
C209
DNP
C211
DNP
3
5
(AD2Yp)
(AD1Xm)
(AD3Ym)
(AD0Xp)
PD22 {3,12}
PD21 {3,12}
PD23 {3,12}
PD20 {3,12}
4
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
RED7
RED6
RED5
RED4
RED3
R169
R168
R167
R166
3
PE24
PE30
PE23
PE29
PE22
PE28
PE21
PE27
PE20
PE26
PE18
PE22
PE17
PE21
PE16
PE20
PE15
PE19
PE14
PE18
PE13
PE17
PE12
PE14
PE11
PE13
PE10
PE12
PE9
PE11
PE8
PE10
2
D
R136
4.7K
PE6
PE0
LCDDOTCK
R48 is placed near processor
{12} LCDDOTCK
R48 33R
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(LCDCC)
(LCDPWR)
PE[0..30] {3,12}
C
2
1
B
A
E
D
C
E
B
A
D
C
B
A
E
D
C
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
E
11
12
1
A
B
8 7 6 5 4 3 2 1
D
C
{3,11} PE[0..30]
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPWR)
R49 is placed near processor
PE5
R49 33R
3V3
R117 4.7K
R118 4.7K
{3,7}
{3,7}
PA20
PA21
{2,3,7,8,9,10} NRST
(TWDO)
(TWCK0)
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE3
PE4
PE6
3V3
11
12
13
14
15
17
19
9
10
7
8
5
6
3
4
46
47
48
1
2
42
43
44
45
39
40
41
20
D17
D18
D19
D20
D21
D22
D23
D9
D10
D11
D12
D13
D14
D15
D16
D4
D5
D6
D7
D8
D0
D1
D2
D3
V
H
XCLK
DE
21
22
23
24
SPD
SPC
RESET
NC
B
1 4
2 3
SG-8002JC-13.0000M-PCB
DNP C205
DNP
C207
10pF
4
1
R125
0R
3
2
VDDIO
DVDD
38
16
DGND
18
AVDD_PLL
32
AGND_PLL
31
AVDD
33
AGND
36
AVDD_DAC
25
AGND_DAC
29
ISET
CVBS
30
28
Y
27
C/CVBS
26
P-OUT
37
C206
10pF
The frequency accuracy must be +-20ppm or higher.
C190
100nF
C191
100nF
C192
10uF
10V
C194
100nF
C195
100nF
C197
100nF
L18
742792093
3V3
1V8
C193
10uF
10V
3V3
C196
10uF
10V
L24
C199
1.8uH
100pF
C200
270pF 1
3V3
2
3
Composite Video Output
{3} PB[8..11]
A
{3} PB[20..31]
PB8
PB9
PB10
PB11
(ISI_D8)
(ISI_D09)
(ISI_D10)
(ISI_D11)
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
(ISI_D0)
(ISI_D1)
(ISI_D2)
(ISI_D3)
(ISI_D4)
(ISI_D5)
(ISI_D6)
(ISI_D7)
(ISI_PCK)
(ISI_VSYNC)
(ISI_HSYNC)
(ISI_MCK)
8 7 6 5 4
{11} LCDDOTCK
{3} PD14
CONNECTOR EXTENTION FOR LARGE LCD
3V3
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
PE4
PE6
PE0
(GPIO1)
23
25
27
29
15
17
19
21
31
33
35
37
39
7
9
11
13
3
5
1
J23
26
28
30
32
18
20
22
24
34
36
38
40
10
12
14
16
6
8
2
4
PE7
PE9
PE11
PE13
PE15
PE17
PE19
PE21
PE23
PE25
PE27
PE29
PE3
PE2
PE1
(GPIO2)
PD15 {3}
{3,11}
{3,11}
PD21
PD23
{3}
{3}
{3}
PD25
PD27
PD19
3V3
(AD1Xm)
(AD3Ym)
R128
DNP
9
11
13
15
5
7
1
3
17
19
DNP
TSM-110-01-L-DV
10
12
14
16
6
8
2
4
18
20
(AD0Xp)
(AD2Yp)
PD20 {3,11}
PD22 {3,11}
PD24 {3}
PD26 {3}
PD18 {3}
5V
3V3
{2,3}
{3}
VDDISI
PD12
3
C186
100nF
IMAGE SENSOR CONNECTOR
3V3
C187
10uF
10V
C184
100nF
(CTRL1)
PA21
PB21
PB23
PB25
PB27
PB9
PB11
17
19
21
23
25
27
29
9
11
13
15
5
7
1
3
18
20
22
24
26
28
30
10
12
14
16
6
8
2
4
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13 {3}
LCD & ISI & VIDEO INTERFACE
2
E
D
C
E
D
C
E
D
C
B
A
REV
SCALE
INIT EDIT
MODIF.
1/1
LN
PP
PP
PP
PP
LN
PP
PP
PP
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08
DATE
XXX
VER.
REV.
E
XX-XXX-XX
DATE
SHEET
12
12
1
A
B
D
C
8.1
Revision History
Table 8-1.
Document
11029A
Comments
First issue.
Section 8
Revision History
Change Request
Ref.
AT91SAM9M10-EKES User Guide 8-1
11029A–ATARM–11-Jan-10
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11029A–ATARM–11-Jan-10
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Key Features
- Two high speed USB hosts and one high speed device port
- Ethernet 10/100 interface
- Two high speed multimedia card interfaces
- LCD TFT display (480*RGB*272) with touch panel
- Composite video output
- Camera interface
- Various communication peripherals