BAB-40/60 1 Specification
1.3.7
SCSI Interface Single-ended 8-bit SCSI-2 signals are fed into row A and C of the
VMEbus P2 connector (X102). An ADAP-200 is plugged onto the rear side of the backplane to interface to standard 8-bit SCSI connectors.
The NCR53C710 SCSI controller uses its own code fetching and SCSI data transfer from the DRAM. The processor executes SCSI SCRIPTS to control the actions on the SCSI and the CPU bus. SCRIPTS is a specially designed language for easy SCSI protocol handling. It dramatically reduces the CPU activities. The SCRIPTS processor starts SCSI I/O operations in approximately 500 ns where traditional intelligent host adapters require 2-8 ms.
1.3.8
Serial I/O The BAB-40/60 offers two serial I/O lines, implemented by one Z8530
SCC. CHAN.1 is a RS 232 two wire handshake interface. CHAN.2 uses a removable serial interface level converters (SILC). As shipped, a RS 232 level converter SILC is installed featuring hardware handshake as well as the XON / XOFF protocol. Additional level converter plug-ins for RS 422 and RS 485 are available.
The baud rate generator is driven by 5 MHz, allowing baud rates from
50 b/s to 38.4 kb/s.
1.3.9
CIO Counters/
Timers
The BAB-40/60 offers three independent, programmable 16-bit counters / timers integrated in the CIO.
1.3.10 Parameter
RAM and Real-
Time Clock
The real-time clock is designed with the MK48T12 timekeeper RAM. It combines a 2KBx8 CMOS SRAM (parameter RAM, NVRAM), a bytewide accessible real-time clock, a crystal, and a long-life lithium battery, all in one package. Alternatively, a MK48T18 device can be used which offers 8 KB SRAM or a DS1644 device which offers 32Kx8 KB
SRAM.
1.3.11 Revision
EEPROM
The revision EEPROM is realized by a 512x8B serial EEPROM which offers special board revision information. The lower half size of the
EEPROM is programmed by ELTEC and should not be modified by the user to guarantee board revision consistency. The upper 256 B can be used by the user to store additional information.
Hardware Manual 9
