Application Information. null

Application Information. null

LM4844

SNAS320C – JUNE 2005 – REVISED AUGUST 2007

APPLICATION INFORMATION

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Figure 31. I

2

C Timing Diagram

Figure 32. I

2

C Bus Format

14

Chip Address

ADR = 0

ADR = 1

A7

1

1

1

Mono Volume control

Left Volume control

Right Volume control

Mode control

0

0

0

0

0

0

0

0

0

MD4

0

0

0

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0

0

0

0

0

1

1

1

1

MD3

0

0

0

A6

1

1

1

D7

0

0

1

1

D6

0

1

0

1

Table 1. Chip Address

A5

1

1

1

A4

1

1

1

A3

1

1

1

Table 2. Control Registers

D5

0

LD5

RD5

CD5

D4

MD4

LD4

RD4

0

D3

MD3

LD3

RD3

CD3

A2

0

0

0

D2

MD2

LD2

RD2

CD2

A1

EC

0

1

D1

MD1

LD1

RD1

CD1

A0

0

0

0

D0

MD0

LD0

RD0

CD0

Table 3. Mono Volume Control

0

1

1

1

1

0

0

0

0

MD2

0

0

0

1

0

0

1

1

0

0

1

1

MD1

0

0

1

1

0

1

0

1

0

1

0

1

MD0

0

1

0

Gain (dB)

-34.5

-33.0

-31.5

-30.0

-28.5

-27.0

-25.5

-24.0

-22.5

-21.0

-19.5

-18.0

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1

1

1

1

1

1

1

1

1

1

1

1

1

1

MD4

0

0

0

0

1

1

0

1

1

1

1

1

1

1

1

0

0

0

0

0

LD4//RD4

0

0

0

0

0

0

0

0

0

0

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LM4844

1

0

0

0

0

0

0

0

0

1

1

1

1

1

LD3//RD3

0

0

0

0

0

0

0

0

1

1

0

1

1

1

1

1

1

1

1

0

0

0

0

0

MD3

1

1

1

1

0

0

SNAS320C – JUNE 2005 – REVISED AUGUST 2007

Table 3. Mono Volume Control (continued)

1

0

0

0

0

1

1

1

1

0

0

1

1

1

MD2

1

1

1

1

0

0

1

0

0

1

1

0

0

1

1

1

1

0

0

1

MD1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

MD0

0

1

0

1

0

1

0.0

1.5

3.0

4.5

6.0

7.5

9.0

10.5

12.0

Gain (dB)

-16.5

-15.0

-13.5

-12.0

-10.5

-9.0

-7.5

-6.0

-4.5

-3.0

-1.5

Table 4. Stereo Volume Control

1

0

0

0

0

1

1

1

1

0

0

1

1

1

LD2//RD2

0

0

0

1

1

1

0

1

0

0

1

0

0

1

1

0

0

1

1

1

1

0

0

1

LD1//RD1

0

0

1

0

1

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LD0//RD0

0

1

0

1

0

1

1

0

0

1

-18.0

-16.5

-15.0

-13.5

-12.0

-25.5

-24.0

-22.5

-21.0

-19.5

-10.5

-9.0

-7.5

-6.0

Gain (dB)

-40.5

-39.0

-37.5

-36.0

-34.5

-33.0

-31.5

-30.0

-28.5

-27.0

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SNAS320C – JUNE 2005 – REVISED AUGUST 2007

LD4//RD4

1

1

1

1

1

1

1

1

LD3//RD3

1

1

1

1

1

1

1

1

Table 4. Stereo Volume Control (continued)

LD2//RD2

0

0

0

0

1

1

1

1

LD1//RD1

0

0

1

1

1

1

0

0

LD0//RD0

0

1

0

1

0

1

0

1

7

8

9

5

6

Mode

0

1

2

3

4

10

11

12

13

14

0

1

1

0

0

CD3

0

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

1

CD2

0

0

0

0

1

1

1

15 1 1

M - M

IN

Input Level

L - L

IN

Input Level

R - R

IN

Input Level

G

M

- Mono Volume Control Gain

G

L

- Left Stereo Volume Control Gain

G

R

- Right Stereo Volume Control Gain

SD - Shutdown

MUTE - Mute

1

0

0

0

1

CD1

0

0

1

1

0

1

1

0

0

1

1

Table 5. Mixer and Output Mode

1

0

1

1

0

CD0

0

1

0

1

0

0

1

0

Loudspeaker L

SD

2(G

M x M)

2(G

M x M)

SD

2(G

L x L)

2(G

L x L)

SD

1

0

1

2(G

L x L) + 2(G

M x M)

2(G

L x L) + 2(G

M x M)

SD

Loudspeaker R

SD

Headphone L

SD

RESERVED

2(G

M x M) MUTE

2(G

M x M)

SD

(G

M x M)

(G

M x M)

RESERVED

RESERVED

2(G

R x R) MUTE

2(G

R x R)

SD

(G

L x L)

(G

L x L)

RESERVED

2(G

R

RESERVED x R) + 2(G x M)

M

MUTE

2(G

R x R) + 2(G x M)

SD

M

(G

L

(G

M x L) + x M)

(G

L

(G

M x L) + x M)

RESERVED

LD5

RD5

Table 6. Texas Instruments 3D Enhancement

0

1

0

1

Loudspeaker Texas Instruments 3D Off

Loudspeaker Texas Instruments 3D On

Headphone Texas Instruments 3D Off

Headphone Texas Instruments 3D On

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Gain (dB)

-4.5

-3.0

-1.5

0.0

1.5

3.0

4.5

6.0

Headphone R

SD

MUTE

(G

M x M)

(G

M x M)

MUTE

(G

R x R)

(G

R x R)

MUTE

(G

R

(G

M x R) + x M)

(G

R

(G

M x R) + x M)

16

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SNAS320C – JUNE 2005 – REVISED AUGUST 2007

CD5

Table 7. Wake-up Time Select

0

1

Fast Wake-up Setting

Slow Wake-up Setting

I

2

C COMPATIBLE INTERFACE

The LM4844 uses a serial bus, which conforms to the I

2

C protocol, to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I

2

C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4844.

The I

2

C address for the LM4844 is determined using the ADR pin. The LM4844's two possible I

2

C chip addresses are of the form 111110X

1

If the I

2

0 (binary), where X

1

= 0, if ADR is logic low; and X

1

= 1, if ADR is logic high.

C interface is used to address a number of chips in a system, the LM4844's chip address can be changed to avoid any possible address conflicts.

The bus format for the I

2

C interface is shown in sections:

Figure 31 . The bus format diagram is broken up into six major

The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I

2

C bus to check the incoming address against their own address.

The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.

Each address bit must be stable while the clock level is high.

After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).

Then the master sends an acknowledge clock pulse. If the LM4844 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4844.

The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high.

After the data byte is sent, the master must check for another acknowledge to see if the LM4844 received the data.

If the master has more data bytes to send to the LM4844, then the master can repeat the previous two steps until all data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The data line should be held high when not in use.

I

2

C INTERFACE POWER SUPPLY PIN (I

2

CV

DD

)

The LM4844's I

2

C interface is powered up through the I

2 voltage level set by the I

2

CV

DD is ideal whenever logic levels for the I

2

CV

DD pin. The LM4844's I

2

C interface operates at a pin which can be set independent to that of the main power supply pin V

DD

. This

C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system.

TEXAS INSTRUMENTS 3D ENHANCEMENT

The LM4844 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right speakers are too close to one another, due to system size constraints or equipment limitations.

An external RC network, shown in

Figure 1

, is required to enable the 3D effect. There are separate RC networks for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set independently for each set of stereo outputs.

The amount of the 3D effect is set by the R

The C

3D

3D resistor. Decreasing the value of R

3D low cutoff frequency at which the 3D effect starts to occur, as shown by

Equation 1 .

will increase the 3D effect.

capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C

3D will decrease the f

3D(-3dB)

= 1 / 2 π (R

3D

)(C

3D

) (1)

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Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 20k Ω /R

3D

20k Ω

). Setting R

3D to will result in a gain increase by a multiplication factor of (1+20k Ω /20k Ω ) = 2 or 6dB whenever the 3D effect is activated. The volume control can be programmed through the I

2

C compatible interface to compensate for the extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before the 3D effect is activated, the volume control should be programmed to –6dB (10111 from Table 4) immediately after the 3D effect has been activated. Setting R

3D

= 20k Ω and C pronounced 3D effect with a minimal increase in output noise.

3D

= 0.22

μ F allows the LM4844 to produce a

OUTPUT CAPACITOR-LESS (OCL) OPERATION AND LAYOUT TECHNIQUES FOR OPTIMUM CROSSTALK

The LM4844’s OCL headphone architecture eliminates output coupling capacitors. Unless the headphone is in shutdown, the OCL output will be at a bias voltage of ½V

DD

, which is applied to the stereo headphone jack’s sleeve. This voltage matches the bias voltage present on LHP and RHP outputs that drive the headphones. The headphones operate in a manner similar to a bridge-tied load (BTL). Because the same DC voltage is applied to both headphone speaker terminals there is no net DC current flow through the speaker. AC current flows through a headphone speaker as an audio signal’s output amplitude increases on the speaker’s terminal.

The headphone jack’s sleeve is not connected to circuit ground when used in OCL mode. Using the headphone output jack as a line-level output will place the LM4844’s ½V

DD bias voltage on a plug’s sleeve connection.

Since the LHP and RHP outputs of the LM4844 share the OCL output as a reference, certain layout techniques should be used in order to achieve optimum crosstalk performance. The crosstalk will depend on the parasitic resistance of the trace connecting the LM4844 OCL output to the headphone jack sleeve and on the load resistance value. Since the load resistance is often predetermined, it is advisable to use a trace that is as short and as wide as possible. Reasonable application of this layout technique will result in crosstalk values of 60dB, as specified in the electrical characteristics table.

BRIDGE CONFIGURATION EXPLANATION

The LM4844 consists of two sets of bridged-tied amplifier pairs that drive the left loudspeaker (LLS) and the right loudspeaker (RLS). For this discussion, only the LLS bridge-tied amplifier pair will be referred to. The LM4844 drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the LLS amplifier block, the output of the amplifier that drives LLS- serves as the input to the unity gain inverting amplifier that drives LLS+.

This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to as 'bridge mode'). This results in a differential or BTL gain of:

A

VD

= 2(R f

/ R i

) = 2 (2)

Both the feedback resistor, R f

, and the input resistor, R i

, are internally set.

Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped.

Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LLS- and LLS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers.

POWER DISSIPATION

Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.

A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4844 has 2 sets of bridged-tied amplifier pairs driving LLS and RLS. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From

Equation 4

, assuming a 5V power supply and an 8 Ω

Equation 3

and load, the maximum power dissipation for LLS and RLS is

634mW per channel.

P

DMAX-LLS

= 4(V

DD

)

2

/ (2 π

2

R

L

): Bridged (3)

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P

DMAX-RLS

= 4(V

DD

)

2

/ (2 π

2

R

L

): Bridged (4)

The LM4844 also has a pair of single-ended amplifiers driving LHP and RHP. The maximum internal power dissipation for ROUT and LOUT is given by

Equation 5

and

Equation 6 . From Equation 5

and

Equation 6

, assuming a 5V power supply and a 32 channel.

Ω load, the maximum power dissipation for LOUT and ROUT is 40mW per

P

DMAX-LHP

= (V

DD

)

2

/ (2 π

2

R

L

): Single-ended (5)

P

DMAX-RHP

= (V

DD

)

2

/ (2 π

2

R

L

): Single-ended (6)

The maximum internal power dissipation of the LM4844 occurs during output modes 3, 8, and 13 when both loudspeaker and headphone amplifiers are simultaneously on; and is given by

Equation 7 .

P

DMAX-TOTAL

= P

DMAX-LLS

+ P

DMAX-RLS

+ P

DMAX-LHP

+ P

DMAX-RHP

(7)

The maximum power dissipation point given by

Equation 8

:

P

DMAX

' = (T

JMAX

- T

A

) / θ

JA

Equation 7

must not exceed the power dissipation given by

(8)

The LM4844's T

JMAX

= 150°C. In the TL package, the LM4844's θ

JA is 62°C/W. At any given ambient temperature T

A

Rearranging

, use

Equation 8

Equation 8

to find the maximum internal power dissipation supported by the IC packaging.

and substituting P

DMAX-TOTAL for P

DMAX

' results in

Equation 9

. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4844's maximum junction temperature.

T

A

= T

JMAX

- P

DMAX-TOTAL

θ

JA

(9)

For a typical application with a 5V power supply, stereo 8 Ω loudspeaker load, and the stereo 32 Ω headphone load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 100°C for the TL package.

T

JMAX

= P

DMAX-TOTAL

θ

JA

+ T

A

(10)

Equation 10

gives the maximum junction temperature T

JMAX

. If the result violates the LM4844's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.

Further allowance should be made for increased ambient temperatures.

The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of

Equation 7

is greater than that of

Equation 8 ,

then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θ

JA

. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.

External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.

When adding a heat sink, the θ

JA is the sum of θ

JC

, θ

CS

, and θ

SA

. ( θ

JC is the junction-to-case thermal impedance,

θ

CS is the case-to-sink thermal impedance, and

Typical Performance Characteristics

θ

SA is the sink-to-ambient thermal impedance.) Refer to the curves for power dissipation information at lower output power levels.

POWER SUPPLY BYPASSING

As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.

However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected between the LM4844's supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4844's power supply pin and ground as short as possible.

SELECTING EXTERNAL COMPONENTS

Input Capacitor Value Selection

Amplifying the lowest audio frequencies requires a high value input coupling capacitor (C i in

Figure 1

). In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 50Hz. Applications using speakers with this limited frequency response reap little improvement; by using a large input capacitor.

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The internal input resistor (R i using

Equation 11 .

) and the input capacitor (C i

) produce a high pass filter cutoff frequency that is found f c

= 1 / (2 π R i

C i

) (11)

As an example when using a speaker with a low frequency limit of 50Hz and R i

0.19µF. The 0.22µF C i shown in response extends below 40Hz.

Figure 33

= 20k Ω , C i

, using

Equation 11

is allows the LM4844 to drive high efficiency, full range speaker whose

Bypass Capacitor Value Selection

Besides minimizing the input capacitor size, careful consideration should be paid to value of C

B connected to the BYPASS pin. Since C

B

, the capacitor determines how fast the LM4844 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4844's outputs ramp to their quiescent DC voltage (nominally V

DD

/2), the smaller the turn-on pop. Choosing C

B equal to 2.2µF along with a small value of C i

(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing C i no larger than necessary for the desired bandwidth helps minimize clicks and pops. C

B

's value should be in the range of 5 times to 10 times the value of C i

. This ensures that output transients are eliminated when the LM4844 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, C

B

, between the

BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The

PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of C

B will increase wake-up time. The selection of bypass capacitor value, C

B

, depends on desired PSRR requirements, click and pop performance, wake-up time, system cost, and size constraints.

C

S

+

1

P

F

V

DD

C

3DLS

0.22

P

F

V

DD

C

3DHP

P1

100

R k :

3DLS

4.7 k :

0.22 P F

4.7 k :

R

3DHP

P2

100 k :

Audio Input

Ci1

+

0.22 P F

Audio Input

Ci2

+

0.22 P F

Audio Input

Ci3

+

0.22 P F

M

IN

L

R

IN

IN

V

DD

BYPASS

C

B

I2CV

DD

+

2.2 P F

I2CV

DD

J2

SCL

SDA

Mono Input

-34.5 dB to +12 dB

Left Stereo Input

-40.5 dB to +6 dB

Right Stereo Input

-40.5 dB to +6 dB

Bias

Click / Pop Supression

I2C

Interface

extV

DD

I2C Interface

6 Pin Header

Mixer

&

Mode Select

National

3D

ADR

R

PU

V

DD

J1

100 k :

GND

Figure 33. Reference Design Board Schematic

LLS+

LLS-

RLS+

RLS-

OCL

RHP

LHP

8

:

8

:

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Demonstration Board Layout

Figure 34. Recommended YZR PCB Layout:

Silkscreen Layer

Figure 35. Recommended YZR PCB Layout:

Top Layer

Figure 36. Recommended YZR PCB Layout:

Mid Layer 1

Figure 37. Recommended YZR PCB Layout:

Mid Layer 2

Figure 38. Recommended YZR PCB Layout:

Bottom Layer

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LM4844

SNAS320C – JUNE 2005 – REVISED AUGUST 2007

Revision History

Rev

1.1

1.2

1.3

1.4

Date

06/01/06

07/20/07

08/07/07

08/23/07

www.ti.com

Description

Initial WEB.

Edited the Control Interface Electrical

Characteristics tables.

Changed the I

2

CVdd from 1.8V into 1.7V

(under the Operating Ratings).

Fixed one place of typo.

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

LM4844TL/NOPB

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package Qty

DSBGA YZR 30 250

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

SNAGCU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85

Top-Side Markings

(4)

GF3

LM4844TLX/NOPB ACTIVE DSBGA YZR 30 3000 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

GF3

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

14-Mar-2013

*All dimensions are nominal

Device Package

Type

Package

Drawing

Pins

LM4844TL/NOPB

LM4844TLX/NOPB

DSBGA

DSBGA

YZR

YZR

30

30

SPQ

250

3000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

178.0

8.4

178.0

8.4

A0

(mm)

2.74

2.74

B0

(mm)

3.15

3.15

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

0.76

0.76

4.0

4.0

8.0

8.0

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

14-Mar-2013

*All dimensions are nominal

Device

LM4844TL/NOPB

LM4844TLX/NOPB

Package Type

DSBGA

DSBGA

Package Drawing

YZR

YZR

Pins

30

30

SPQ

250

3000

Length (mm)

210.0

210.0

Width (mm)

185.0

185.0

Height (mm)

35.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

YZR0030xxx

0.600±0.075

D

E

TLA30XXX (Rev C)

D: Max = 3.01 mm, Min = 2.909 mm

E: Max = 2.601 mm, Min = 2.5 mm

4215057/A 12/12

NOTES:

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

www.ti.com

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