CC1150

CC1150

CC1150

Tc = 25

°

C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Current consumption

Current consumption,

315 MHz

Current consumption,

433 MHz

Current consumption,

868 MHz

Current consumption,

915 MHz

Min Typ Max

200

Unit Condition

nA Voltage regulator to digital part off, register values lost (SLEEP state)

222

µ

A Voltage regulator to digital part on, all other modules in power down (XOFF state)

1.1 mA Only voltage regulator to digital part and crystal oscillator running

(IDLE state)

7.7

25.6

14.1

26.1

14.6

29.3

15.5

29.3

15.2 mA Only the frequency synthesizer running (FSTXON state). This current consumptions also representative for the other intermediate states when going from IDLE until reaching TX, and frequency calibration states mA Transmit mode, +10 dBm output power (0xC4)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC2)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC3)

Transmit mode, 0 dBm output power (0x60)

See more in section 21 and DN012 [3]

mA Transmit mode, +10 dBm output power (0xC0)

Transmit mode, 0 dBm output power (0x50)

See more in section 21 and DN012 [3]

Table 4: Electrical Specifications

SWRS037A Page 6 of 60

CC1150

4.2 RF Transmit Section

Tc = 25

°

C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Differential load impedance

315 MHz

433 MHz

868/915 MHz

Output power, highest setting

Output power, lowest setting

Spurious emissions and harmonics,

433/868 MHz

Spurious emissions,

315/915 MHz

Harmonics 315 MHz

Harmonics 915 MHz

TX latency

Min Typ

122 + j31

116 + j41

86.5 + j43

Max Unit Condition/Note

Differential impedance as seen from the RF-port (RF_P and

RF_N) towards the antenna. Follow the CC1150EM reference

design ( [1] and [2]) available from the TI website.

+10 Output power is programmable, and full range is available across all frequency bands. Output power may be restricted by regulatory limits. See also Application Note

AN039 [4] and Design Note

DN006 [5].

Delivered to a 50

single-ended load via CC1150 EM reference

design ( [1] and [2]) RF matching network. Maximum output power

can be increased 1-2 dB by using wire-wound inductors instead of multilayer inductors in the balun and filter circuit for the 868/915

MHz band, see more in DN017 [6].

–30 Output power is programmable, and full range is available across all frequency bands.

Delivered to a 50

single-ended load via CC1150 EM reference

design ( [1] and [2]) RF matching network

–54

–30 dBm dBm

25 MHz - 1 GHz

47-74, 87.5 - 118, 174 - 230, 470 - 862 MHz

Otherwise above 1 GHz

Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate

at without violating regulatory restrictions, see more in AN039 [4].

See also section 7.5 for information regarding additional filtering.

dBm

EIRP

<200

µ

V/m at 3 m below 960 MHz.

–41.2 dBm

EIRP

<500

µ

V/m at 3 m above 960 MHz

–20

–41.2 dBc dBm

2 nd

, 3 rd

and 4 th

harmonic when the output power is maximum 6 mV/m at 3 m (-19.6 dBm EIRP)

5 th

harmonic

–20

–41.2 dBc dBm

2 nd

harmonic with +10 dBm output power

3 rd

, 4 th

and 5 th

harmonic

8 Bits Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports.

Table 5: RF Transmit Parameters

SWRS037A Page 7 of 60

CC1150

4.3 Crystal Oscillator

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference

design ( [1] and [2]).

Parameter

Crystal frequency

Tolerance

Min Typ Max Unit Condition/Note

26 26 27 MHz

±40 ppm This is the total tolerance including a) initial tolerance, b) aging and c) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth

10 13 20 pF Simulated over operating conditions Load capacitance

Start-up time 150 µ s

Measured on the CC1150EM reference design ( [1] and [2]). This

parameter is to a large degree crystal dependent.

Table 6: Crystal Oscillator Parameters

4.4 Frequency Synthesizer Characteristics

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design

( [1] and [2]).

Parameter

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

RF carrier phase noise

PLL turn-on / hop time 85.1

PLL calibration time

Min

397 F

Typ Max

XOSC

2

16

±40

/ 412

694

–82

–86

–90

–98

–106

–113

–119

–127

88.4

18739

721

88.4

721

Unit Condition/Note

Hz ppm

26 MHz-27 MHz crystals. The resolution (in Hz) is equal for all frequency bands.

Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. dBc/Hz @ 50 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 100 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 200 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 500 kHz offset from carrier, carrier at 868 MHz dBc/Hz @ 1 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 2 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 5 MHz offset from carrier, carrier at 868 MHz dBc/Hz @ 10 MHz offset from carrier, carrier at 868 MHz

µ s

XOSC cycles

µ s

Time from leaving the IDLE state until arriving in the

FSTXON or TX state, when not performing calibration.

Crystal oscillator running.

Calibration can be initiated manually or automatically before entering or after leaving TX.

Min/typ/max time is for 27/26/26 MHz crystal frequency.

Table 7: Frequency Synthesizer Parameters

SWRS037A Page 8 of 60

CC1150

4.5 Analog Temperature Sensor

Tc = 25

°

C, VDD = 3.0 V if nothing else is stated. Note that it is necessary to write 0xBF to the PTEST register to use the

analog temperature sensor in the IDLE state.

Parameter

Output voltage at –40

°

C

Output voltage at 0

°

C

Output voltage at +40

°

C

Output voltage at +80

°

C

Temperature coefficient

Absolute error in calculated temperature

Min Typ Max Unit Condition/Note

0.651 V

0.747 V

0.847 V

0.945 V

–2

*

2.45 mV/

°

C Fitted from –20

°

C to +80

°

C

°

C From

°

C to +80

°

C when using 2.45 mV /

°

C, after 1-point calibration at room temperature

*

Indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

0.3 mA Current consumption increase when enabled

Table 8: Analog Temperature Sensor Parameters

Tc = 25

°

C if nothing else stated.

Digital Inputs/Outputs

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage

Logic "1" output voltage

Logic "0" input current

Logic "1" input current

Min

0

VDD-0.7

0

VDD-0.3

N/A

N/A

Max

0.7

VDD

0.5

VDD

–1

1

Unit

V

V

V

V

µ

A

µ

A

Condition

For up to 4 mA output current

For up to 4 mA output current

Input equals 0 V

Input equals VDD

Table 9: DC Characteristics

4.7 Power on Reset

For proper Power-On-Reset functionality, the power supply must comply with the requirements in

Table 10 below. Otherwise, the chip should be assumed to have unknown state until transmitting

an

SRES

strobe over the SPI interface. See section 16.1 on page 31 for a description of the

recommended start up sequence after turning power on.

Parameter

Power-up ramp-up time

Power off time

Min Typ Max Unit Condition/Note

1

5 ms ms

From 0 V until reaching 1.8 V

Minimum time between power-on and power-off

Table 10: Power-on Reset Requirements

SWRS037A Page 9 of 60

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