CC1150

CC1150

CC1150

Figure 8: SmartRF Studio User Interface

10 4-wire Serial Configuration and Data Interface

CC1150 is configured via a simple 4-wire SPIcompatible interface (

SI

,

SO

,

SCLK

and

CSn

) where

CC1150

is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address. and data transfer on the SPI interface is shown

in Figure 9 with reference to Table 15.

When

CSn

is pulled low, the MCU must wait until the

CC1150

SO

pin goes low before starting to transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the

SLEEP or XOFF states, the

SO

pin will always go low immediately after taking

CSn

low.

During address and data transfer, the

CSn

pin

(Chip Select, active low) must be kept low. If

CSn

goes high during the access, the transfer will be cancelled. The timing for the address

SWRS037A Page 18 of 60

t sp t ch t cl t sd t hd t ns

CC1150

SCLK:

CSn:

Write to register:

SI

SO

X

Hi-Z

SI

X

SO

Hi-Z

0

S7

Read from register:

1

A6 A5 A4 A3 A2

S7

A6

S

S

6

6

A5

S

S

5

5

A4

S4

S4

A3

S

S

3

3

A2

S

S

2

2

A1

S

A1

S

1

1

A0

S0

A0

S0

X D

W

7 D

W

6

S7

D

R

7

S6

D

R

6

D

W

5

S5

D

R

5

D

W

4 D

W

3

S4

D

R

4

S3

X

D

R

3

D

W

2

S2

D

R

2

D

W

1

S1

D

R

1

D

W

0

S0

D

R

0

S7

X

Hi-Z

Hi-Z

Figure 9: Configuration Registers Write and Read Operations

Min

t ch t cl t rise t fall t sd

Parameter Description

f

SCLK

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

t sp,pd

SCLK

frequency, single access

No delay between address and data byte

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

CSn

low to positive edge on

SCLK

, in power-down mode t sp

CSn

low to positive edge on

SCLK

, in active mode t hd

Clock rise time

Clock fall time

Setup data (negative

SCLK edge) to positive edge on

SCLK

(t sd

applies between address and data bytes, and between data bytes)

Hold data after positive edge on

SCLK

Single access

Burst access t ns

Negative edge on

SCLK

to

CSn

high

Max Units

9

6.5

150 - µ s

20 - ns

-

-

55

76

-

-

5

5 ns ns ns ns

20 - ns

20 - ns

Table 15: SPI Interface Timing Requirements

Note that the minimum t sp,pd

figure in Table 15 can be used in cases where the user does not read the

CHIP_RDYn

signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 µs in Table 15 is the crystal oscillator

start-up time measured using crystal AT-41CD2 from NDK.

When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is sent by the

CC1150

on the

SO

pin.

The status byte contains key status signals, useful for the MCU. The first bit, s7, is the

CHIP_RDYn

signal; this signal must go low

before the first positive edge of

SCLK

. The

CHIP_RDYn

signal indicates that the crystal is

running and the regulated digital supply voltage is stable.

Bit 6, 5 and 4 comprises the

STATE

value. This

value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down.

The frequency and channel configuration should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

The last four bits (3:0) in the status byte contains

FIFO_BYTES_AVAILABLE.

This field

SWRS037A Page 19 of 60

CC1150 contains the number of bytes free for writing into the TX FIFO. When

FIFO_BYTES_AVAILABLE=15

, 15 or more

bytes are free. Table 16 gives a status byte

summary.

Bits Name

7 CHIP_RDYn

6:4 STATE[2:0]

Description

Stays high until power and crystal have stabilized. Should always be low when using the SPI interface.

Indicates the current main state machine mode

Value State Description

000 Idle

001 Not used state

(Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error)

Not used

010 TX

011 FSTXON

100 CALIBRATE

101 SETTLING

110 Not used

Fast TX ready

Frequency synthesizer calibration is running

PLL is settling

Not used

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO.

The configuration registers on the

CC1150

are located on SPI addresses from 0x00 to 0x2E.

Table 26 on page 43 lists all configuration

registers. The detailed description of each

register is found in Section 25.1, starting on page 45.

Table 16: Status Byte Summary

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting

CSn

high.

All configuration registers can be both written and read. The read/write bit controls if the register should be written or read. When writing to registers, the status byte is sent on the

SO

pin each time a header byte or data byte is transmitted on the

SI

pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

For register addresses in the range 0x30-

0x3D, the burst bit is used to select between status registers (burst bit is 1) and command strobes (burst bit is 0). See more in section

10.3 below. Because of this, burst access is

not available for status registers, so they must be read one at a time. The status registers can only be read.

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC1150

Errata Notes [8] for more details.

Command Strobes may be viewed as single byte instructions to

CC1150

. By addressing a

Command Strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, flush the TX FIFO etc. The nine

SWRS037A Page 20 of 60

command strobes are listed in Table 25 on page 42.

CC1150

Note that an SIDLE strobe will clear all pending command strobes until IDLE state is reached. This means that if for example an

SIDLE strobe is issued while the radio is in TX state, any other command strobes issued before the radio reaches IDLE state will be ignored.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the

SO

pin.

However, if an

SRES

command strobe is being issued, on will have to wait for the

SO

pin to go low before the next command strobe can be

issued as shown in Figure 10.The command

strobes are executed immediately, with the exception of the

SPWD

and the

SXOFF

strobes that are executed when

CSn

goes high.

Figure 10: SRES Command Strobe

A command strobe may be followed by any other SPI access without pulling

CSn

high.

The 64-byte TX FIFO is accessed through the

0x3F addresses. When the read/write bit is zero, the TX FIFO is accessed. The TX FIFO is write-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte.

After the data byte a new address is expected; hence,

CSn

can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting

CSn

high.

The following header bytes access the FIFO:

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on

SO

, as shown in Figure 10. This status

byte can be used to detect TX FIFO underflow

CSn:

Command strobe(s):

Read or write register(s):

Read or write consecutive registers (burst):

Read or write n+1 bytes from/to RF FIFO:

Combinations:

ADDR strobe

ADDR reg

ADDR reg

DATA

ADDR reg n

DATA

ADDR

FIFO n

DATA while writing data to the TX FIFO. Note that the status byte contains the number of bytes free

before

writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The TX FIFO may be flushed by issuing a

SFTX

command strobe. The

SFTX

command

strobe can only be issues in the IDLE or

TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.

Figure 11 gives a brief overview of different

register access types possible.

...

DATA

...

...

DATA

Figure 11: Register Access Types

DATA

...

DATA byte n

ADDR

FIFO

DATA byte 0

DATA

...

SWRS037A Page 21 of 60

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