4.6 Read/write Circuit. Fujitsu MPE3XXXAT

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4.6 Read/write Circuit. Fujitsu MPE3XXXAT | Manualzz

4.6

Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC).

4.6.1

Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an 4 or 8-channel read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the serial port (SDEN, SCLK, SDATA).

The IC generates a write error sense signal (WUS) when a write error occurs due to head shortcircuit or head disconnection.

4.6.2

Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC with synchronizing with the write clock. The NRZ write data is converted from 16-bits data to 17-bits data by the encoder circuit then sent to the

PreAMP, and the data is written onto the media.

(1) 16/17 GCR

The disk drive converts data using the 16/17 (0, 6, 8) group coded recording (GCR) algorithm.

This code format is 0 to 6 code bit "0"s are placed between "1"s.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non-linearity generated at reading.

4.6.3

Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 16/17 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

C141-E077-01EN 4 - 11

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

(3) Adaptive equalizer circuit

This circuit is 5-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the Extended Partial Response Class 4 (EPR4) waveform.

(4) Viterbi detection circuit

The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) Data separator circuit

The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.

(6) 16/17 GCR decoder

This circuit converts the 17-bits read data into the 16-bits NRZ data.

4.6.4

Time base generator circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.2

describes the data transfer rate and recording density (BPI) of each zone.

4 - 12 C141-E077-01EN

Table 4.2

Transfer rate of each zone

For MPE3064AT, MPE3136AT, MPE3273AT

Zone

Cylinder

0

0 to

410

1

411 to

2320

2

2321 to

3110

3

3111 to

4600

Transfer rate

[MB/s]

29.80

28.63

28.09

27.06

4

4601 to

6060

26.01

5

6061 to

7200

25.14

6

7201 to

8260

24.31

7

8261 to

9970

22.90

Zone

Cylinder

8

9971 to

11180

9

11181 to

11850

10

11851 to

12900

11

12901 to

13830

12

13831 to

14970

13

14971 to

16130

14

16131 to

16347

21.85

21.26

20.29

19.43

18.34

17.18

16.13

Transfer rate

[MB/s]

For MPE3102AT, MPE3170AT, MPE3204AT

Zone

Cylinder

0

0 to

1260

1

1261 to

2280

2

2281 to

3190

3

3191 to

4100

Transfer rate

[MB/s]

30.43

29.80

28.63

28.62

4

4101 to

4880

28.09

5

4881 to

6315

27.06

6

6316 to

7680

26.01

7

7681 to

8760

25.14

Zone

Cylinder

8

8761 to

10030

9

10031 to

11370

10

11371 to

12510

11

12511 to

13060

12

13061 to

14125

13

14126 to

15410

14

15411 to

16347

24.06

22.90

21.85

21.33

20.29

19.00

17.18

Transfer rate

[MB/s]

The MPU transfers the data transfer rate setup data (SDATA/SCLK) to the RDC that includes the time base generator circuit to change the data transfer rate.

C141-E077-01EN 4 - 13

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