CHAPTER 5 INTERFACE. Fujitsu MPE3XXXAT

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CHAPTER 5 INTERFACE. Fujitsu MPE3XXXAT | Manualzz

CHAPTER 5 INTERFACE

5.1

Physical Interface

5.2

Logical Interface

5.3

Host Commands

5.4

Command Protocol

5.5

Ultra DMA feature set

5.6

Timing

C141-E077-01EN 5 - 1

5.1

Physical Interface

5.1.1

Interface signals

Table 5.1 shows the interface signals.

Table 5.1

Interface signals

Description Host

Cable select

Chip select 0

Chip select 1

Data bus bit 0

Data bus bit 1

Data bus bit 2

Data bus bit 3

Data bus bit 4

Data bus bit 5

Data bus bit 6

Data bus bit 7

Data bus bit 8

Data bus bit 9

Data bus bit 10

Data bus bit 11

Data bus bit 12

Data bus bit 13

Data bus bit 14

Data bus bit 15

Device active or slave present

Device address bit 0

Device address bit 1

Device address bit 2

DMA acknowledge

DMA request

Interrupt request

I/O read

DMA ready during Ultra DMA data in bursts

Data strobe during Ultra DMA data out bursts

I/O ready

DMA ready during Ultra DMA data out bursts

Data strobe during Ultra DMA data in bursts

I/O write

Stop during Ultra DMA data bursts

Passed diagnostics

Cable type detection

Reset

Dir see note

↔ see note see note

Dev

Note See signal descriptions

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

DASP–

DA0

DA1

DA2

DMACK–

DMARQ

Acrorym

CSEL

CS0–

CS1–

DD0

DD1

DD2

DD3

DD4

INTRQ

DIOR–

HDMARDY–

HSTROBE

IORDY

DDMARDY–

DSTROBE

DIOW–

STOP

PDIAG–

CBLID–

RESET–

5 - 2 C141-E077-01EN

5.1.2

Signal assignment on the connector

Table 5.2 shows the signal assignment on the interface connector.

Pin No.

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

Table 5.2

Signal assignment on the interface connector

Signal

RESET–

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GND

DMARQ

DIOW–, STOP

DIOR–, HDMARDY–, HSTROBE

IORDY, DDMARDY–,

DSTROBE

DMACK–

INTRQ

DA1

DA0

CS0–

DASP–

Pin No.

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

Signal

GND

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

(KEY)

GND

GND

GND

CSEL

GND reserved

PDIAG–, CBLID–

DA2

CS1–

GND

[signal]

RESET–

DATA 0-15

DIOW–, STOP

[I/O] [Description]

I Reset signal from the host. This signal is low active and is asserted for a minimum of 25

µ s during power on. The device has a 10 k

pull-up resistor on this signal.

I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer

I DIOW– is the strobe signal asserted by the host to write device registers or the data port.

DIOW– shall be negated by the host prior to initiation of an Ultra

DMA burst. STOP shall be negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra

DMA burst.

C141-E077-01EN 5 - 3

5 - 4

DIOR–

HDMARDY–

HSTROBE

INTRQ

CS0–

CS1–

DA 0-2

KEY

[signal]

PIDAG–

CBLID–

DASP–

[I/O] [Description]

I

I DIOR– is the strobe signal asserted by the host to read device registers or the data port.

HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.

The host may negate HDMARDY- to pause an Ultra DMA data in burst.

I HSTROBE is the data out strobe signal from the host for an Ultra

DMA data out burst. Both the rising and falling edge of

HSTROBE latch the data from DATA 0-15 into the device. The host may stop generating HSTROBE edges to pause an Ultra

DMA data out burst.

O Interrupt signal to the host.

This signal is negated in the following cases:

– assertion of RESET– signal

– Reset by SRST of the Device Control register

– Write to the command register by the host

– Read of the status register by the host

– Completion of sector data transfer

(without reading the Status register)

When the device is not selected or interrupt is disabled, the

INTRQ

Signal shall be in a high impedance state.

I

I

I Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers.

Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

Binary decoded address signals asserted by the host to access task file registers.

Key pin for prevention of erroneous connector insertion –

I/O This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This signal is used to detect the cable type (80 or 40-conductor cable) installed in the system. This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This is a time-multiplexed signal that indicates that the device is active and a slave device is present.

This signal is pulled up to +5 V through 10 k

resistor at each device.

C141-E077-01EN

[signal]

IORDY

DDMARDY–

DSTROBE

CSEL

DMACK–

DMARQ

GND

[I/O] [Description]

O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request.

O DDMARDY– is a flow control signal for Ultra DMA data out bursts.

This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate DDMARDY– to pause an Ultra DMA data out burst.

O DSTROBE is the data in strobe signal from the device for an Ultra

DMA data in burst. Both the rising and falling edge of

DSTROBE latch the data from DATA 0-15 into the host. The device may stop generating DSTROBE edges to pause an Ultra

DMA data in burst.

I

I

This signal to configure the device as a master or a slave device.

When CSEL signal is grounded, the IDD is a master device.

When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 10 k

resistor.

The host system asserts this signal as a response that the host system receive data or to indicate that data is valid.

O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system

(at reading) or from the host system (at writing).

The direction of data transfer is controlled by the IOR- and IOWsignals. In other word, the device negates the DMARQ signal after the host system asserts the DMACK– signal. When there is another data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCW16–, CS0– and

CS1- signals are not asserted. The DMA data transfer is a 16-bit data transfer. The device has a 10 k

pull-down resistor on this signal.

– Grounded

Note:

"I" indicates input signal from the host to the device.

"O" indicates output signal from the device to the host.

"I/O" indicates common output or bi-directional signal between the host and the device.

C141-E077-01EN 5 - 5

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinderhead-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the

Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of

LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE

DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.)

×

(Number of head) + (Head No.))

×

(Number of sector/track)]

+ (Sector No.) – 1

5.2.1

I/O registers

Communication between the host system and the device is done through input-output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the host system. Table 5.3. shows the coding address and the function of I/O registers.

5 - 6 C141-E077-01EN

CS0– CS1– DA2

1

1

1

1

1

1

Command block registers

1 0 0 0

0

0

0

0

0

0

0

0

0

1

1

1

0

Control block registers

0

0

1

1 1

1

1

1

X

1

1

0

0

1

1

X

0

1

1

1

1

DA1

Table 5.3

I/O registers

DA0

I/O registers

Read operation Write operation

0

1

0

1

0

1

0

1

X

0

1

Data

Error Register

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

(Invalid)

Alternate Status

Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

(Invalid)

Device Control

Host I/O address

X'1F0'

X'1F1'

X'1F2'

X'1F3'

X'1F4'

X'1F5'

X'1F6'

X'1F7'

X'3F6'

X'3F7'

Notes:

1.

The Data register for read or write operation can be accessed by 16 bit data bus

(DATA0 to DATA15).

2.

The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.

When reading the Drive Address register, bit 7 is high-impedance state.

4.

The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and

Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E077-01EN 5 - 7

5.2.2

Command block registers

(1) Data register (X'1F0')

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode.

(2) Error register (X'1F1')

The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE

DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7

ICRC

X: Unused

Bit 6

UNC

Bit 5

X

Bit 4

IDNF

Bit 3

X

Bit 2

ABRT

Bit 1

TK0NF

Bit 0

AMNF

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Interface CRC error (ICRC). This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers.

Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

Unused

ID Not Found (IDNF). This bit indicates an error except for, uncorrectable error and SB not found, and Aborted Command.

Unused

Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready, Write Fault) or the command code was invalid.

Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

Address Mark Not Found. This bit indicates that an SB not found error has been encountered.

5 - 8 C141-E077-01EN

[Diagnostic code]

X'01': No Error Detected.

X'02': HDC Register Compare Error

X'03': Data Buffer Compare Error.

X'05': ROM Sum Check Error.

X'80': Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X'01' to X'05').

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X'1F1')

The Features register provides specific feature to a command. For instance, it is used with SET

FEATURES command to enable or disable caching.

(4) Sector Count register (X'1F2')

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is

X'00', the sector count is 256.

When this register indicates X'00' at the completion of the command execution, this indicates that the command is completed successfully. If the command is not completed successfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands; INITIALIZE

DEVICE PARAMETERS, FORMAT TRACK, SET FEATURES, IDLE, STANDBY and SET

MULTIPLE MODE.

(5) Sector Number register (X'1F3')

The contents of this register indicates the starting sector number for the subsequent command.

The sector number should be between X'01' and [the number of sectors per track defined by

INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E077-01EN 5 - 9

(6) Cylinder Low register (X'1F4')

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

(7) Cylinder High register (X'1F5')

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X'1F6')

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines "the number of heads minus 1".

Bit 7

X

Bit 6

L

Bit 5

X

Bit 4

DEV

Bit 3

HS3

Bit 2

HS2

Bit 1

HS1

Bit 0

HS0

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Unused

L. 0 for CHS mode and 1 for LBA mode.

Unused

DEV bit. 0 for the master device and 1 for the slave device.

HS3 CHS mode head address 3 (2

3

). LBA bit 27.

HS2 CHS mode head address 3 (2

2

). LBA bit 26.

HS1 CHS mode head address 3 (2

1

). LBA bit 25.

HS0 CHS mode head address 3 (2

0

). LBA bit 24.

5 - 10 C141-E077-01EN

(9) Status register (X'1F7')

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

Busy (BSY) bit. This bit is set whenever the Command register is accessed.

Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested

(DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control register, the BSY bit is set. the BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the Command register.

(c) Within 5

µ s following transfer of 512 bytes data during execution of the

READ SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE

BUFFER command.

Within 5

µ s following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command.

Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected

(not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

C141-E077-01EN 5 - 11

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

Always 0.

Always 0.

Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

(10) Command register (X'1F7')

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the

Command register is written.

5 - 12 C141-E077-01EN

5.2.3

Control block registers

(1) Alternate Status register (X'3F6')

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply

Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7

BSY

Bit 6

DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

(2) Device Control register (X'3F6')

The Device Control register contains device interrupt and software reset.

Bit 7

X

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2 Bit 1

SRST nIEN

Bit 0

0

- Bit 2:

- Bit 1:

SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the high-impedance state.

5.3

Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

C141-E077-01EN 5 - 13

5.3.1

Command code and parameters

Table 5.4 lists the supported commands, command code and the registers that needed parameters are written.

Table 5.4

Command code and parameters (1 of 2)

Command name

READ SECTOR(S)

READ MULTIPLE

READ DMA

READ VERIFY SECTOR(S)

WRITE MULTIPLE

WRITE DMA

WRITE VERIFY

Command code (Bit) Parameters used

7 6 5 4 3 2 1 0 FR SC SN CY DH

0 0 1 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 0 N Y Y Y Y

1 1 0 0 1 0 0 R N Y Y Y Y

0 1 0 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 1 N Y Y Y Y

1 1 0 0 1 0 1 R N Y Y Y Y

0 0 1 1 1 1 0 0 N Y Y Y Y

WRITE SECTOR(S)

RECALIBRATE

0 0 1 1 0 0 0 R N Y Y Y Y

0 0 0 1 X X X X N N N N D

SEEK 0 1 1 1 X X X X N N Y Y Y

INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

EXECUTE DEVICE DIAGNOSTIC

FORMAT TRACK

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

1

1

1

1

1

0

1

1

0

0

0

1

1

1

0

1

1

0

0

1

0

0

0

0

N

N

N

N

N

N

N

N

N

N

N

N

D

D

1 1 1 0 1 1 1 1 Y N* N N D

1 1 0 0 0 1 1 0 N Y N N D

D*

0 1 0 1 0 0 0 0 N N Y* Y Y

0 0 1 0 0 0 1 R N Y Y Y Y

0 0 1 1 0 0 1 R N Y Y Y Y

1 1 1 0 0 1 0 0 N N N N D

1

1

1

1

1 1 1 0 1 0 0 0 N N N N D

1

1

0

1

0

1

1

0

0

0

1

0

1

1

1

1

N Y N N D

0

1

0

1

0

1

0

1

1

0

1

0

0

0

0

0

1

0

1

0

0

0

1

1

1

1

0

0

N

N

N

Y

N

N

N

N

D

D

5 - 14 C141-E077-01EN

Table 5.4

Command code and parameters (2 of 2)

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

SMART

Command name

FLUSH CACHE

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

1

1

1

1

Command code (Bit) Parameters used

7 6 5 4 3 2 1 0 FR SC SN CY DH

0

1

0

1

0

1

0

1

1

0

1

0

0

0

1

0

1

0

0

1

0

0

0

1

0

0

1

0

N

N

N

N

N

N

N

N

D

D

1

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

N N N N D

1 0 1 1 0 0 0 0 Y Y Y Y D

1 1 1 0 0 1 1 1 N N N N D

1 1 1 1 0 1 1 0 N N N N D

1 1 1 1 0 0 1 1 N N N N D

1 1 1 1 0 1 0 0 N N N N D

1 1 1 1 0 1 0 1 N N N N D

1 1 1 1 0 0 0 1 N N N N D

1 1 1 1 0 0 1 0 N N N N D

1 1 1 1 1 0 0 1 N Y Y Y Y

1 1 1 1 1 0 0 0 N N N N D

Notes:

FR : Features Register CY: Cylinder Registers

SC : Sector Count Register DH : Drive/Head Register

SN : Sector Number Register

R: R = 0 or 1

Y: Necessary to set parameters

Y*: Necessary to set parameters under the LBA mode.

N: Necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device and the slave device execute it.

X: Do not care

C141-E077-01EN 5 - 15

5.3.2

Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.

Example: READ SECTOR(S)

Bit

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

7

0

×

6 5 4 3 2 1 0

0

L

1 0 0 0 0 0

×

DV Head No. / LBA [MSB]

Start cylinder address [MSB] / LBA

Start cylinder address [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count xx

1F7

1F6

At command completion (I/O registers contents to be read)

Bit

1F5

H

H

H

(ST)

(DH)

(CH)

1F4

H

(CL)

7

×

6 5 4 3 2

End cylinder address [LSB] / LBA

End sector No.

1

/ LBA [LSB]

0

L

Error information

×

DV End Head No. / LBA [MSB]

End cylinder address [MSB] / LBA

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

X‘00’

Error information

CM: Command register

DH: Device/Head register

CH: Cylinder High register

CL: Cylinder Low register

SN: Sector Number register

SC: Sector Count register

FR: Features register

ST: Status register

ER: Error register

L: LBA (logical block address) setting bit

DV: Device address. bit x, xx: Do not care (no necessary to set)

5 - 16 C141-E077-01EN

Note:

1.

When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the

CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB

(most significant bit) and bits of the SN register are the LSB (least significant bit).

2.

At error occurrence, the SC register indicates the remaining sector count of data transfer.

3.

In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X'20' or X'21')

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device reads the target sector.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

If an error occurs in a sector, the read operation is terminated at the sector where the error occurred.

Command block registers contain the cylinder, the head, and the sector addresses of the sector

(in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

0

L

1 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E077-01EN 5 - 17

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X'C4')

This command operates similarly to the READ SECTOR(S) command. The device does not generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is generated after the transfer of a block of sectors for which the number is specified by the SET

MULTIPLE MODE command.

The implementation of the READ MULTIPLE command is identical to that of the READ

SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE

MODE command are transferred without intervening interrupts. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the

SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command.

When the READ MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector

Count register is less than the defined block count (the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors

[block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of ("number of sectors"/"block count").

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ

MULTIPLE command with an ABORTED COMMAND error.

If an error occurs, reading sector is stopped at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred, and remaining number of sectors that had not transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.

5 - 18 C141-E077-01EN

Figure 5.1 shows an example of the execution of the READ MULTIPLE command.

Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block)

READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

Number of sectors in incomplete block = remainder of 9/4 =1

BSY

DRDY

Parameter

Write

~

INTRQ

DRQ

Sector transferred

Command Issue

Status read

1 2 3 4

Block

Status read

5 6 7 8

Block

Status read

9

Partial block

Figure 5.1

Execution example of READ MULTIPLE command

1F7

H

(CM)

1F6

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

H

At command issuance (I/O registers setting contents)

(DH)

(CH)

(CL)

(SN)

(SC)

(FR)

1

×

1

L

0 0 0 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00

H

(*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.

C141-E077-01EN 5 - 19

(3) READ DMA (X'C8' or X'C9')

This command operates similarly to the READ SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES command.

1) Multiword DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command

2) Ultra DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

(CH)

(CL)

(SN)

(SC)

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1

×

1

L

0 0 1 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

5 - 20 C141-E077-01EN

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X'40' or X'41')

This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.

If an error occurs, the verify operation is terminated at the sector where the error occurred. The command block registers contain the cylinder, the head, and the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.

The Sector Count register indicates the number of sectors that have not been verified.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

0

×

1

L

0 0 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E077-01EN 5 - 21

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X'30' or X'31')

This command writes data of sectors from the address specified in the Device/Head, Cylinder

High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied seek. After the head reaches to the specified track, the device writes the target sector.

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

0

×

0

L

1 1 0 0 0 R

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

5 - 22 C141-E077-01EN

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(6) WRITE MULTIPLE (X'C5')

This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE

MODE command.

The implementation of the WRITE MULTIPLE command is identical to that of the WRITE

SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE

MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE command operation, the DRQ bit of the Status register is required to set only at the start of the data block, not on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the

SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command.

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector

Count register is less than the defined block count the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors

[block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of ("number of sectors"/"block count").

If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE

MULTIPLE command with an ABORTED COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred. Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block.

C141-E077-01EN 5 - 23

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

L

0 0 0 1 0 1

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00

H

/ LBA [LSB]

Error information

Note:

When the command terminates due to error, only the DV bit and the error information field are valid.

(7) WRITE DMA (X'CA' or X'CB')

This command operates similarly to the WRITE SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command.

A host system can be select the following transfer mode using the SET FEATURES command.

5 - 24 C141-E077-01EN

1) Multiword DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command

2) Ultra DMA transfer mode 2:

Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

L

0 0 1 0 1 R

×

DV Start head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X'3C')

This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

0

×

0

L

1 1 1 1 0 0

×

DV Start head No. /LBA [MSB]

Start cylinder No. [MSB]/ LBA

Start cylinder No. [LSB] / LBA

Start sector No.

/ LBA [LSB]

Transfer sector count

xx

C141-E077-01EN 5 - 25

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

×

L

Status information

×

DV End head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No.

00 (*1)

/ LBA [LSB]

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X'1x', x: X'0' to X'F')

This command performs the rezero. Upon receipt of this command, the device sets BSY bit of the Status register and performs a rezero. When the device completes the rezero, the device updates the Status register, clears the BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

0

×

0

×

1

DV x x xx x

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx x

5 - 26 C141-E077-01EN

(10) SEEK (X'7x', x : X'0' to X'F')

This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt.

The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.

In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

1

L

1

×

1

DV x x x x

Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

xx

/ LBA [LSB]

xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

H

(DH)

(CH)

(CL)

(SN)

(SC)

(ER)

×

L

Status information

×

DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

xx

/ LBA [LSB]

Error information

C141-E077-01EN 5 - 27

(11) INITIALIZE DEVICE PARAMETERS (X'91')

The host system can set the number of sectors per track and the maximum head number

(maximum head number is "number of heads minus 1") per cylinder with this command.

Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.

When the SC register is specified to X'00', an ABORTED COMMAND error is posted. Other than X'00' is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting.

In LBA mode

The device ignores the L bit specification and operates with the CHS mode specification. An accessible area of this command within head moving in the LBA mode is always within a default area. It is recommended that the host system refers the addressable user sectors (total number of sectors) in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

0

×

0

×

1

DV

0 0 0

Max. head No.

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Number of sectors/track xx

1

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV Max. head No.

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error Information

(12) IDENTIFY DEVICE (X'EC')

The host system issues the IDENTIFY DEVICE command to read parameter information (512 bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer. The device then sets the

DRQ bit of the Status register, and generates an interrupt. After that, the host system reads the information out of the sector buffer. Table 5.5 shows the arrangements and values of the parameter words and the meaning in the buffer.

5 - 28 C141-E077-01EN

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

C141-E077-01EN 5 - 29

Table 5.5

Information to be read by IDENTIFY DEVICE command (1 of 4)

89

90

91

92

93

86

87

88

94-127

128

129-255

68

69-79

80

81

82

83

84

85

65

66

67

62

63

64

52

53

54

55

56

57-58

59

60-61

27-46

47

48

49

50

51

5

6

7-9

10-19

20

21

22

23-26

Word

0

1

2

3

4

X‘000x’

X‘4000’

X‘xx1F’

X‘0000’

X‘0000’

X‘00xx’

X‘0000’

X‘x000’

X‘00’

X‘xx’

X‘00’

X‘0000’

X‘xx07’

X‘0003’

X‘0078’

X‘0078’

X‘0078’

X‘0078’

X‘00’

X‘001E’

X‘0000’

X‘346B’

X‘4008’

X‘4000’

X‘00xx’

X‘8010’

X‘0000’

X‘0B00’

X‘0000’

X‘0200’

X‘0000’

X‘0007’

(Variable)

(Variable)

(Variable)

(Variable)

*10

*11

Value

X‘045A’

*2

X‘0000’

*3

X‘0000’

General Configuration *1

Number of cylinders

Reserved

Number of Heads

Retired

Description

X‘0000’

X‘003F’

Retired

Number of sectors per track

X‘000000000000’ Retired

X‘0000’

X‘0400’

X‘0004’

Serial number (ASCII code) *4

Retired

Buffer size in 512 byte increments

Number of ECC bytes transferred at READ LONG or WRITE LONG command

Firmware revision (ASCII code) *5

Model number (ASCII code) *6

Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command

Reserved

Capabilities *7

Reserved

PIO data transfer mode *8

Retired

Enable/disable setting of words 54-58, 64-70 and 88 *9

Number of current Cylinders

Number of current Head

Number of current sectors per track

Total number of current sectors

Transfer sector count currently set by READ/WRITE MULTIPLE command

Total number of user addressable sectors (LBA mode only)

Retired

Multiword DMA transfer mode *12

Advance PIO transfer mode support status *13

Minimum multiword DMA transfer cycle time per word : 120 [ns]

Manufacturer's recommended DMA transfer cycle time : 120 [ns]

Minimum PIO transfer cycle time without flow control : 120 [ns]

Minimum PIO transfer cycle time with IORDY flow control : 120 [ns]

Reserved

Major version number *14

Minor version number (not reported)

Support of command sets *15

Support of command sets *16

Support of command set/feature extension (fixed)

Enable/disable Command set/feature enabled. *17

Enable/disable Command set/feature enabled. *18

Default of command set/feature (fixed)

Ultra DMA modes *19

Time required for security erase unit completion

Time required for Enhanced security erase completion

Current advanced power management value

Reserved

CBLID detection results *20

Reserved

Security Status

Reserved

5 - 30 C141-E077-01EN

Table 5.5

Information to be read by IDENTIFY DEVICE command (2 of 4)

*1 Word 0: General configuration

Bit 15: 0 = ATA device

Bit 14-8: Vendor specific

Bit 7: 1 = Removable media device

Bit 6: 1 = not removable controller and/or device

Bit 5-1: Vendor specific

Bit 0: Reserved

*2 Number of Cylinders, *3 Number of Heads,

*11 Total number of user addressable sectors (LBA mode only.)

*2

MPE3064AT MPE3102AT MPE3136AT MPE3170AT MPE3204AT MPE3273AT

X‘3462’ X‘3FFF’

*3 X‘0F’ X‘10’

*11 X‘00C15DC2’ X‘01316CDC’ X‘01973C40’ X‘01FD0AC4’ X‘0262D9B8’ X‘032E7960’

0

1

0

0

0

0

*4 Word 10-19: Serial number; ASCII code (20 characters, right-justified)

*5 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)

*6 Word 27-46: Model number;

ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20')

One of the following model numbers;

MPE3064AT, MPE3102AT, MPE3136AT, MPE3170AT, MPE3204AT, MPE3273AT

*7 Word 49: Capabilities

Bit 15-14: Reserved

Bit 13: Standby timer value 0 = Standby timer values shall be managed by the device

Bit 12: Reserved

Bit 11: IORDY support 1=Supported

Bit 10: IORDY inhibition 0=Disable inhibition

Bit 9: LBA support 1=Supported

Bit 8: DMA support 1=Supported

Bit 7-0: Vendor specific

*8 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X'02'=PIO mode 2

Bit 7-0: Vendor specific

*9 Word 53: Enable/disable setting of word 54-58 ,64-70 and 88

Bit 15-3: Reserved

Bit 2: Enable/disable setting of word 88 1=Enable

Bit 1: Enable/disable setting of word 64-70 1=Enable

Bit 0: Enable/disable setting of word 54-58 1=Enable

C141-E077-01EN 5 - 31

5 - 32

Table 5.5

Information to be read by IDENTIFY DEVICE command (3 of 4)

*10 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command

Bit 15-9: Reserved

Bit 8: Multiple sector transfer 1=Enable

Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt supports 2, 4, 8 and 16 sectors.

*12 Word 63: Multiword DMA transfer mode

Bit 15-8: Currently used multiword DMA transfer mode

Bit 7-0: Supportable multiword DMA transfer mode

Bit 2=1 Mode 2

Bit 1=1 Mode 1

Bit 0=1 Mode 0

*13 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved

Bit 7-0: Advance PIO transfer mode

Bit 1=1 Mode 4

Bit 0=1 Mode 3

*14 Word 80: Major version number

Bit 15-5: Reserved

Bit 4: ATA-4 Supported=1

Bit 3: ATA-3 Supported=1

Bit 2: ATA-2 Supported=1

Bit 1: ATA-1 Supported=1

Bit 0: Undefined

*15 Word 82: Support of command sets

Bit 15: Reserved

Bit 14: NOP command supported = 0

Bit 13: Read Buffer command supported = 1

Bit 12: Write Buffer command supported = 1

Bit 11: Write Verify command supported (Old Spec.) = 0

Bit 10: Host Protected Area feature command supported = 1

Bit 9: Device Reset command supported = 0

Bit 8: SERVICE Interrupt supported = 0

Bit 7: Release Interrupt supported = 0

Bit 6: Lock Ahead supported = 1

Bit 5: Write-cache supported = 1

Bit 4: Packet command feature set supported = 0

Bit 3: Power Management feature set supported=1

Bit 2: Removable feature set supported=0

Bit 1: Security feature set supported=1

Bit 0: SMART feature set supported=1

C141-E077-01EN

Table 5.5

Information to be read by IDENTIFY DEVICE command (4 of 4)

*16 Word 83: Support of command sets

Bit 15: 0

Bit 14: 1

Bit 13-5: Reserved

Bit 4: Removable Media Status Notification feature set supported = 0

Bit 3: Advanced Power Management feature set supported = 1

Bit 2: CFA feature set supported = 0

Bit 1: READ/WRITE DMA QUEUED supported = 0

Bit 0: DOWNLOAD MICROCODE command supported = 0

*17 Word 85: Enable/disable Command set/feature enabled

Bit 15: Reserved

Bit 14: NOP command supported = 0

Bit 13: READ BUFFER command supported = 0

Bit 12: WRITE BUFFER command supported = 0

Bit 11: Reserved

Bit 10: Host Protected Area feature set supported = 0

Bit 9: DEVICE RESET command supported = 0

Bit 8: SERVICE interrupt enabled = 0

Bit 7: Release interrupt enabled = 0

Bit 6: Look-ahead enabled = 1

Bit 5: Write cache enabled = 1

Bit 4: PACKET Command feature set supported = 0

Bit 3: Power Management feature set supported = 0

Bit 2: Removable Media feature set supported = 0

Bit 1: Security Mode feature set enabled = 1

Bit 0: SMART feature set enabled = 1

*18 Word 86: Enable/disable Command set/feature enabled

Bit 15-5: Reserved

Bit 4: Removable Media Status Notification feature set enabled = 0

Bit 3: Advanced Power Management feature set enabled = 1

Bit 2: CFA feature set supported = 0

Bit 1: READ/WRITE DMA QUEUED command supported = 0

Bit 0: DOWNLOAD MICROCODE command supported = 0

*19 Word 88: Ultra DMA modes

Bit 15-13: Reserved

Bit 12-8: Currently used Ultra DMA transfer modes

Bit 7-5: Reserved

Bit 4-0: Supportable Ultra DMA transfer mode

Bit 4=1 Mode 4

Bit 3=1 Mode 3

Bit 2=1 Mode 2

Bit 1=1 Mode 1

Bit 0=1 Mode 0

*20 Word 93: CBLID– detection results

Bit 15-14: Reserved

Bit 13: Device detected CBLID– above V

IH

(80-conductor cable) = 1

Device detected CBLID– below V

IL

(40-conductor cable) = 0

Bit 12-0: Reserved

C141-E077-01EN 5 - 33

(13) IDENTIFY DEVICE DMA (X'EE')

When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

0

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(14) SET FEATURES (X'EF')

The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. For the transfer mode

(Feature register = 03), detail setting can be done using the Sector Count register.

Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register. Then, the device clears the BSY bit, and generates an interrupt.

If the value in the Features register is not supported or it is invalid, the device posts an

ABORTED COMMAND error.

Table 5.6 lists the available values and operational modes that may be set in the Features register.

5 - 34 C141-E077-01EN

Table 5.6

Features register values and settable modes

Features Register

X‘02’

X‘03’

Drive operation mode

Enables the write cache function.

Specifies the transfer mode. Supports PIO mode 4, single word DMA mode

2, and multiword DMA mode regardless of Sector Count register contents.

No operation.

X‘04’

X‘05’

X‘33’

X‘54’

X‘55’

X‘66’

X‘77’

X‘81’

X‘82’

X‘84’

X‘85’

X‘88’

X‘89’

X‘AA’

X‘AB’

X‘BB’

X‘CC’

Enable the advanced power management function.

No operation.

No operation.

Disables read cache function.

Disables the reverting to power-on default settings after software reset.

No operation.

No operation.

Disables the write cache function.

No operation.

Disable the advanced power management function.

No operation.

No operation.

Enables the read cache function.

No operation.

Specifies the transfer of 4-byte ECC for READ LONG and WRITE LONG commands.

Enables the reverting to power-on default settings after software reset.

C141-E077-01EN 5 - 35

5 - 36

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

0

DV

1 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx or transfer mode

[See Table 5.6]

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

1

The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value.

However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.

The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode

PIO flow control transfer mode X

Multiword DMA transfer mode X

Ultra DMA transfer mode X

00000 000 (X‘00’)

00001 000 (X‘08’: Mode 0)

00001 001 (X‘09’: Mode 1)

00001 010 (X‘0A’: Mode 2)

00001 011 (X‘0B’: Mode 3)

00001 100 (X‘0C’: Mode 4)

00100 000 (X‘20’: Mode 0)

00100 001 (X‘21’: Mode 1)

00100 010 (X‘22’: Mode 2)

01000 000 (X‘40’: Mode 0)

01000 001 (X‘41’: Mode 1)

01000 010 (X‘42’: Mode 2)

01000 011 (X‘43’: Mode 3)

01000 100 (X‘44’: Mode 4)

C141-E077-01EN

(15) SET MULTIPLE MODE (X'C6')

This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.

The number of sectors per block is written into the Sector Count register. The IDD supports 2,

4, 8 and 16 (sectors) as the block counts.

Upon receipt of this command, the device sets the BSY bit of the Status register and checks the contents of the Sector Count register. If the contents of the Sector Count register is valid and is a supported block count, the value is stored for all subsequent READ MULTIPLE and

WRITE MULTIPLE commands. Execution of these commands is then enabled. If the value of the Sector Count register is not a supported block count, an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

When the SET MULTIPLE MODE command operation is completed, the device clears the

BSY bit and generates an interrupt.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

×

0

×

0

DV

0 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Sector count/block xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx

Sector count/block

Error information

0

After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.

C141-E077-01EN 5 - 37

Regarding software reset, the mode set prior to software reset is retained after software reset.

The parameters for the multiple commands which are posted to the host system when the

IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the

IDENTIFY DEVICE command.

Word 47 = 8010:

Word 59 = 0000:

= 01xx:

Maximum number of sectors that can be transferred per interrupt by the

READ MULTIPLE and WRITE MULTIPLE commands are 16 (fixed).

The READ MULTIPLE and WRITE MULTIPLE commands are disabled.

The READ MULTIPLE and WRITE MULTIPLE commands are enabled. "xx" indicates the current setting for number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE

MULTIPLE commands.

e.g. 0110 = Block count of 16 has been set by the SET MULTIPLE

MODE command.

(16) EXECUTE DEVICE DIAGNOSTIC (X'90')

This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.

If device 1 is present:

Both devices shall execute self-diagnosis.

The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.

If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X'80' to its own diagnostic status.

The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.)

A diagnostic status of the device 0 is read by the host system. When a diagnostic failure of the device 1 is detected, the host system can read a status of the device 1 by setting the

DV bit (selecting the device 1).

When device 1 is not present:

The device 0 posts only the results of its own self-diagnosis.

The device 0 clears the BSY bit of the Status register, and generates an interrupt.

Table 5.7 lists the diagnostic code written in the Error register which is 8-bit code.

If the device 1 fails the self-diagnosis, the device 0 "ORs" X'80' with its own status and sets that code to the Error register.

5 - 38 C141-E077-01EN

Code

X‘01’

X‘03’

X‘05’

X‘8x’

Table 5.7

Diagnostic code

Result of diagnostic

No error detected.

Data buffer compare error

ROM sum check error

Failure of device 1

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

0

×

0

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

At command completion (I/O registers contents to be read)

H

(ST) Status information

00 1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

00

00

01

01

H

H

Diagnostic code

0

(17) FORMAT TRACK (X'50')

Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512byte format parameter transfer from the host system. After completion of transfer, the device clears the DRQ bits, sets the BSY bit. However the device does not perform format operation, but the drive clears the BYS bit and generates an interrupt soon. When the command execution completes, the device clears the BSY bit and generates an interrupt.

The drive supports this command for keep the compatibility with previous drive only.

(18) READ LONG (X'22' or X'23')

This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.

C141-E077-01EN 5 - 39

The READ LONG command supports only single sector operation.

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

0

×

0

L

1

×

0

DV

0 0 1 R

Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

R = 0 or 1

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

Number of sectors to be transferred

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, this register indicates 01.

(19) WRITE LONG (X'32' or X'33')

This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.

This command is operated under the following conditions:

The command is issued in a sequence of the READ LONG or WRITE LONG (to the same address) command issuance. (WRITE LONG command can be continuously issued after the READ LONG command.)

If above condition is not satisfied, the command operation is not guaranteed.

5 - 40 C141-E077-01EN

1F5

1F4

1F3

1F2

1F1

H

H

H

H

H

(CH)

(CL)

(SN)

(SC)

(FR)

R = 0 or 1

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

0

×

0

L

1 1

×

DV

0 0 1 R

Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

Number of sectors to be transferred

xx

At command completion (I/O registers contents to be read)

1F7

1F6

H

H

(ST)

(DH)

×

L

×

Status information

DV Head No. /LBA [MSB]

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No.

/ LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, this register indicates 01.

(20) READ BUFFER (X'E4')

The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

1

×

1

×

1

×

0

DV

0 1 xx

0 xx xx xx xx xx

0

C141-E077-01EN 5 - 41

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(21) WRITE BUFFER (X'E8')

The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the

BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the sector buffer, then generates an interrupt.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

1

×

1

×

1

×

0

DV

1 0 xx

0 xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

0

5 - 42 C141-E077-01EN

(22) IDLE (X'97' or X'E3')

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.

If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown immediately. When the timer reaches the specified time, the device enters the standby mode.

If the contents of the Sector Count register is 0, the automatic power-down function is disabled.

Enabling the automatic power-down function means that the device automatically enters the standby mode after a certain period of time. When the device enters the idle mode, the timer starts countdown. If any command is not issued while the timer is counting down, the device automatically enters the standby mode. If any command is issued while the timer is counting down, the timer is initialized and the command is executed. The timer restarts countdown after completion of the command execution.

The period of timer count is set depending on the value of the Sector Count register as shown below.

0

1 to 240 [X'01' to X'F0']

241 to 251 [X'F1' to X'FB']

252

253

Sector Count register value

[X'00']

[X'FC']

[X'FD']

254 to 255 [X'FE' to X'FF']

Point of timer

Disable of timer

(Value

×

5) seconds

(Value – 240)

×

30 minutes

21 minutes

8 hours

21 minutes 15 seconds

1F7

1F6

H

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

× ×

X'97' or X'E3'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Period of timer xx

C141-E077-01EN 5 - 43

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(23) IDLE IMMEDIATE (X'95' or X'E1')

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

× ×

X'95' or X'E1'

×

DV xx xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

5 - 44 C141-E077-01EN

(24) STANDBY (X'96' or X'E2')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.

If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown when the device returns to idle mode.

When the timer value reaches 0 (passed a specified time), the device enters the standby mode.

If the contents of the Sector Count register is 0, the automatic power-down function is disabled.

Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as the READ SECTOR(s) command is received, the device processes the command after driving the spindle motor.

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'96' or X'E2'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx

Period of timer xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(25) STANDBY IMMEDIATE (X'94' or X'E0')

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence.

C141-E077-01EN 5 - 45

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'94' or X'E0'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx xx

Error information xx

(26) SLEEP (X'99' or X'E6')

This command is the only way to make the device enter the sleep mode.

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode.

In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All

I/O register outputs are in high-impedance state.

The only way to release the device from sleep mode is to execute a software or hardware reset.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

At command issuance (I/O registers setting contents)

× ×

X'99' or X'E6'

×

DV xx xx xx xx xx xx

5 - 46 C141-E077-01EN

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

(27) CHECK POWER MODE (X'98' or X'E5')

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers.

The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.

Power save mode

• During moving to standby mode

• Standby mode

• During returning from the standby mode

• Idle mode

• Active mode

Sector Count register

X'00'

X'80'

X'FF'

C141-E077-01EN 5 - 47

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'98' or X'E5'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV xx xx xx

X'00' or X'FF'

Error information xx

(28) SMART (X'B0)

This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted

Command error is posted.

It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command. If the keys are set incorrectly, the Aborted Command error is posted.

When the failure prediction feature is disabled, the Aborted Command error is posted in response to subcommands other than SMART Enable Operations (FR register = D8h).

When the failure prediction feature is enabled, the device collects or updates several items to forecast failures. In the following sections, note that the values of items collected or updated by the device to forecast failures are referred to as attribute values.

5 - 48 C141-E077-01EN

Table 5.8 Features Register values (subcommands) and functions

Features Resister

X’D0’

X’D1’

X’D2’

X’D3’

X’D8’

X’D9’

X’DA’

Function

SMART Read Attribute Values:

A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512byte attribute value information to the host.

* For information about the format of the attribute value information, see Table 5.9.

SMART Read Attribute Thresholds:

This subcommand is used to transfer 512-byte insurance failure threshold value data to the host.

* For information about the format of the insurance failure threshold value data, see Table 5.10.

SMART Enable-Disable Attribute AutoSave:

This subcommand is used to enable (SC register !!XX!! 00h) or disable (SC register = 00h) the setting of the automatic saving feature for the device attribute data. The setting is maintained every time the device is turned off and then on.

When the automatic saving feature is enabled, the attribute values are saved after

15 minutes passed since the previous saving of the attribute values. However, if the failure prediction feature is disabled, the attribute values are not automatically saved.

When the device receives this subcommand, it asserts the BSY bit, enables or disables the automatic saving feature, then clears the BSY bit.

SMART Save Attribute Values:

When the device receives this subcommand, it asserts the BSY bit, saves device attribute value data, then clears the BSY bit.

SMART Enable Operations:

This subcommand enables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, enables the failure prediction feature, then clears the BSY bit.

SMART Disable Operations:

This subcommand disables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, disables the failure prediction feature, then clears the BSY bit.

SMART Return Status:

When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers. If there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded into the CL and CH registers. After the settings for the CL and CH registers have been determined, the device clears the BSY bit

The host must regularly issue the SMART Read Attribute Values subcommand (FR register =

D0h), SMART Save Attribute Values subcommand (FR register = D3h), or SMART Return

Status subcommand (FR register = DAh) to save the device attribute value data on a medium.

C141-E077-01EN 5 - 49

Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.

The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers.

If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life . In this case, the host recommends that the user quickly backs up the data.

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

0

×

1

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Key (C2h)

Key (4Fh) xx xx

Subcommand

1F7

H

(ST)

1F6

H

At command completion (I-O registers setting contents)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Key-failure prediction status (C2h-2Ch)

Key-failure prediction status (4Fh-F4h) xx xx

Error information

0

5 - 50 C141-E077-01EN

The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register =

D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Thresholds subcommand (FR register = D1h).

06

07 to

0C

0D

0E to

169

16A to

16F

170

171

Byte

00

01

02

03

04

05

172 to

181

182 to

1FE

1FF

Table 5.9 Format of device attribute value data

Attribute 1

Item

Data format version number

Attribute ID

Status flag

Current attribute value

Attribute value for worst case so far

Raw attribute value

Attribute 2 to attribute 30

Reserved

Reserved

(The format of each attribute value is the same as that of bytes 02 to 0D.)

Failure prediction capability flag

Reserved

Vendor specific

Check sum

C141-E077-01EN 5 - 51

Table 5.10 Format of insurance failure threshold value data

Byte

00

01

02

03

04

Attribute 1

Threshold 1

(Threshold of attribute 1)

Reserved

Item

Data format version number

Attribute ID

Insurance failure threshold to

0D

0E to

169

16A to

17B

17C to

1FE

1FF

Threshold 2 to threshold 30

(The format of each threshold value is the same as that of bytes 02 to 0D.)

Reserved

Unique to vendor

Check sum

Data format version number

The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.

5 - 52 C141-E077-01EN

Attribute ID

The attribute ID is defined as follows:

Attribute ID Attribute name

7

8

9

4

5

2

3

0

1

(Indicates unused attribute data.)

Read error rate

Throughput performance

Spin up time

Number of times the spindle motor is activated

Number of alternative sectors

Seek error rate

Seek time performance

Power-on time

10

12

Number of retries made to activate the spindle motor

Number of power-on-power-off times

13 to 198 (Reserved)

199 Ultra ATA CRC Error Rate

200 Write error rate

201 to 255 (Unique to vendor)

Status flag

Bit 0: If this bit is 1, the attribute is within the insurance range of the device when the attribute exceeds the threshold.

If this bit is 0, the attribute is outside the insurance range of the device when the attribute exceeds the threshold.

Bits 1 to 15: Reserved bits

Current attribute value

The current attribute value is the normalized raw attribute data. The value varies between

01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The device compares the attribute values with thresholds. When the attribute values are larger than the thresholds, the device is operating normally.

Attribute value for the worst case so far

This is the worst attribute value among the attribute values collected to date. This value indicates the state nearest to a failure so far.

C141-E077-01EN 5 - 53

Raw attribute value

Raw attributes data is retained.

Failure prediction capability flag

Bit 0: The attribute value data is saved to a medium before the device enters power saving mode.

Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation.

Bits 2 to 15: Reserved bits

Check sum

Two's complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.

Insurance failure threshold

The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.

5 - 54 C141-E077-01EN

(29) FLUSH CACHE (X ‘E7’)

This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The device should use all error recovery methods available to ensure the data is written successfully. The flushing of write cache may take several seconds to complete depending upon the amount of data to be flushed and the success of the operation.

NOTE - This command may take longer than 30 s to complete.

If the command is not supported, the device shall set the ABRT bit to one. An unrecoverable error encountered during execution of writing data results in the termination of the command and the Command Block registers contain the sector address of the sector where the first unrecoverable error occurred. The sector is removed from the cache. Subsequent FLUSH

CACHE commands continue the process of flushing the cache.

1F7

H

(CM)

1F6

H

At command issuance (I/O registers setting contents)

(DH)

× ×

X'E7'

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

At command completion (I/O registers contents to be read)

(DH)

× ×

Status information

×

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

C141-E077-01EN 5 - 55

(30) SECURITY DISABLE PASSWORD (F6h)

This command invalidates the user password already set and releases the lock function.

The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password.

If the user password or master password transferred from the host does not match, the Aborted

Command error is returned.

Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted

Command error.

(The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and FROZEN MODE.)

Table 5.11 Contents of security password

Word Contents

0 Control word

Bit 0: Identifier

0 = Compares the user passwords.

1 = Compares the master passwords.

1 to 16

Bits 1 to 15: Reserved

Password (32 bytes)

17 to 255 Reserved

5 - 56 C141-E077-01EN

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

(31) SECURITY ERASE PREPARE (F3h)

The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY

ERASE PREPARE command and then the SECURITY ERASE UNIT command. The

SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command.

Issuing this command during FROZEN MODE returns the Aborted Command error.

C141-E077-01EN 5 - 57

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

1

(32) SECURITY ERASE UNIT (F4h)

This command erases all user data. This command also invalidates the user password and releases the lock function.

The host transfers the 512-byte data shown in Table 1.1 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set. The device erases user data, invalidates the user password, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password.

If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.

Issuing this command while in FROZEN MODE returns the Aborted Command error.

5 - 58 C141-E077-01EN

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

(33) SECURITY FREEZE LOCK (F5h)

This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN

MODE.

SECURITY SET PASSWORD

SECURITY UNLOCK

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

FROZEN MODE is canceled when the power is turned off. If this command is reissued in

FROZEN MODE, the command is completed and FROZEN MODE remains unchanged.

Issuing this command during LOCKED MODE returns the Aborted Command error.

The following medium access commands return the Aborted Command error when the device is in LOCKED MODE:

C141-E077-01EN 5 - 59

READ DMA

READ LONG

WRITE DMA

WRITE LONG

READ MULTIPLE

WRITE MULTIPLE

READ SECTORS

WRITE SECTORS

WRITE VETIFY

SECURITY DISABLE PASSWORD

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 1 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I-O registers setting contents)

× ×

Status information

×

DV xx xx xx xx

Error information xx

1

(34) SECURITY SET PASSWORD (F1h)

This command enables a user password or master password to be set.

The host transfers the 512-byte data shown in Table 1.2 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and

Security level bit in the transferred data. (Table 1.3)

Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted

Command error.

5 - 60 C141-E077-01EN

Table 5.12 Contents of SECURITY SET PASSWORD data

Word Contents

0 Control word

Bit 0 Identifier

0 = Sets a user password.

1 = Sets a master password.

Bits 1 to 7 Reserved

Bit 8 Security level

0 = High

1 = Maximum

1 to 16

Bits 9 to 15 Reserved

Password (32 bytes)

17 to 255 Reserved

Table 5.13

Relationship between combination of Identifier and Security level, and operation of the lock function

Indentifier

User

Master

User

Master

Level

High

High

Description

The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password or the master password already set.

The specified password is saved as a new master password. The lock function is not enabled.

Maximum The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password only. The master password already set cannot cancel LOCKED

MODE.

Maximum The specified password is saved as a new master password. The lock function is not enabled.

C141-E077-01EN 5 - 61

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

1

(35) SECURITY UNLOCK (F2h)

This command cancels LOCKED MODE.

The host transfers the 512-byte data shown in Table 1.1 to the device. Operation of the device varies as follows depending on whether the host specifies the master password or user password.

When the master password is selected

When the security level in LOCKED MODE is high, the password is compared with the master password already set. If the passwords are the same, LOCKED MODE is canceled.

Otherwise, the Aborted Command error is returned. If the security level in LOCKED

MODE is set to the highest level, the Aborted Command error is always returned.

When the user password is selected

The password is compared with the user password already set. If the passwords are the same, LOCKED MODE is canceled. Otherwise, the Aborted Command error is returned.

If the password comparison fails, the device decrements the UNLOCK counter. The

UNLOCK counter initially has a value of five. When the value of the UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted

Command error until the device is turned off and then on, or until a hardware reset is executed. Issuing this command with LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter.

Issuing this command in FROZEN MODE returns the Aborted Command error.

5 - 62 C141-E077-01EN

1F7

1F6

H

H

At command issuance (I-O registers setting contents)

(CM)

(DH)

1

×

1

×

1

×

1

DV

0 0 xx

1

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

× × ×

Status information

DV xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER) xx xx xx xx

Error information

0

(36) SET MAX ADDRESS (F9)

This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.

The new address information set by this command is reflected in Words 1, 54, 57, 58, 60 and

61 of IDENTIFY DEVICE information. If an attempt is made to perform a read or write operation for an address beyond the new address space, an ID Not Found error will result.

When SC register bit 0, VV (Value Volatile), is 1, the value set by this command is held even after power on and the occurrence of a hard reset. When the VV bit is 0, the value set by this command becomes invalid when the power is turned on or a hard reset occurs, and the maximum address returns to the value (default value if not set) most lately set when VV bit =

1.

After power on and the occurrence of a hard reset, the host can issue this command only once when VV bit = 1. If this command with VV bit = 1 is issued twice or more, any command following the first time will result in an Aborted Command error.

C141-E077-01EN 5 - 63

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1

×

1

L

1 1

×

DV

1 0 0 1

Max head/LBA [MSB]

Max. cylinder [MSB]/Max. LBA

Max. cylinder [LSB]/Max. LBA

Max. sector/Max. LBA [LSB] xx xx

VV

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

1F4

1F3

H

H

H

(CH)

(CL)

(SN)

1F2

H

(SC)

× ×

Status information

×

DV Max head/LBA [MSB]

Max. cylinder [MSB]/Max. LBA

Max. cylinder [LSB]/Max. LBA

Max. sector/Max. LBA [LSB] xx

1F1

H

(ER) Error information

(37) READ NATIVE MAX ADDRESS (F8)

This command posts the maximum address intrinsic to the device, which can be set by the

SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1

×

1

L

1

×

1

DV

1 0 xx

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

0

5 - 64 C141-E077-01EN

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

At command completion (I/O registers contents to be read)

× ×

Status information

×

DV Max head/LBA [MSB]

Max. cylinder [MSB]/Max. LBA

Max. cylinder [LSB]/Max. LBA

Max. sector/Max. LBA [LSB] xx

Error information

C141-E077-01EN 5 - 65

5.3.3

Error posting

Table 5.14 lists the defined errors that are valid for each command.

Table 5.14 Command code and parameters

Command name

READ SECTOR(S)

WRITE SECTOR(S)

READ MULTIPLE

WRITE MULTIPLE

READ DMA

WRITE DMA

WRITE VERIFY

READ VERIFY SECTOR(S)

RECALIBRATE

SEEK

INITIALIZE DEVICE PARAMETERS

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

EXECUTE DEVICE DIAGNOSTIC

FORMAT TRACK

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

CHECK POWER MODE

SMART

FLUSH CACHE

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

Invalid command

V: Valid on this command

*: See the command descriptions.

Error register (X'1F1') Status register (X'1F7')

ICRC UNC INDF ABRT TR0NF DRDY

V

V

*

V

V

V

V

V

*

V

V

V

V

V

V

V

V

V

*

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

*

V

V

V

V

V

V

V

V

V

V

V

V

V

*

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

DWF

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

ERR

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

5 - 66 C141-E077-01EN

5.4

Command Protocol

The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0.

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

5.4.1

Data transferring commands from device to host

The execution of the following commands involves data transfer from the device to the host.

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

READ SECTOR(S)

READ LONG

READ BUFFER

SMART: SMART Read Attribute Values, SMART Read Attribute Thresholds

The execution of these commands includes the transfer one or more sectors of data from the device to the host. In the READ LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head registers.

b) The host writes a command code to the Command register.

c) The device sets the BSY bit of the Status register and prepares for data transfer.

d) When one sector (or block) of data is available for transfer to the host, the device sets

DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.

e) After detecting the INTRQ signal assertion, the host reads the Status register. The host reads one sector of data via the Data register. In response to the Status register being read, the device negates the INTRQ signal.

f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the

BSY bit and steps d) and after are repeated.

Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit.

Whether or not to transfer the data is determined for each host. In other words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the

DRQ status by resetting.

Figure 5.2 shows an example of READ SECTOR(S) command protocol, and Figure 5.3

shows an example protocol for command abort.

C141-E077-01EN 5 - 67

BSY

DRDY

Parameter write

~ a

Command b c

DRQ d

Status read e

• • • • f d e

Status read

• • • •

INTRQ

Data transfer

DRQ

Command

Expanded

Min. 30

µ s (*1)

INTRQ

Data Reg.

Selection

• • •

Data

IOR-

• • • •

• • • •

• • • •

Word 0 1 2 255

IOCS16-

*1 When the IDD receives a command that hits the cache data during read-ahead, and

transfers data from the buffer without reading from the disk medium.

Figure 5.2

Read Sector(s) command protocol

Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data transfer. It is up to the host whether data is transferred. In other words, the host should receive the data of the sector (512 bytes of uninsured dummy data) or release the DRQ by resetting.

5 - 68 C141-E077-01EN

Note:

For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.

BSY

DRDY

Parameter write

~

DRQ

Command

Status read

INTRQ

Data transfer

* Transfers dummy data

* The host should receive 512-byte dummy data or release the DRQ set state by resetting.

Figure 5.3

Protocol for command abort

5.4.2

Data transferring commands from host to device

The execution of the following commands involves Data transfer from the host to the drive.

FORMAT TRACK

WRITE SECTOR(S)

WRITE LONG

WRITE BUFFER

WRITE VERIFY

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

SECURITY SET PASSWORD

SECURITY UNLOCK

The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline.

C141-E077-01EN 5 - 69

a) The host writes any required parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head registers.

b) The host writes a command code in the Command register. The drive sets the BSY bit of the Status register.

c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit.

d) The host writes one sector of data through the Data register.

e) The device clears the DRQ bit and sets the BSY bit.

f) When the drive completes transferring the data of the sector, the device clears BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit.

g) After detecting the INTRQ signal assertion, the host reads the Status register.

h) The device resets INTRQ (the interrupt signal).

I) If transfer of another sector is requested, steps d) and after are repeated.

Figure 5.4 shows an example of WRITE SECTOR(S) command protocol, and Figure 5.3

shows an example protocol for command abort.

5 - 70

BSY

Parameter write

~ a

DRDY

DRQ b

Command

INTRQ

Data transfer d

Command

Expanded

DRQ Max. 1

µ s c e

Data Reg. Selection

Data

IOR-

IOCS16

Word 0 1 f

Status read g d h

• • •

• • • •

Status read g

• • • •

2

• • • •

• • • •

• • • •

255

Figure 5.4 WRITE SECTOR(S) command protocol

C141-E077-01EN

Note:

For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the

DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred. If the timing to read the Status register does not meet above condition, normal data transfer operation is not assured guaranteed.

When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed.

5.4.3

Commands without data transfer

Execution of the following commands does not involve data transfer between the host and the device.

RECALIBRATE

SEEK

READY VERIFY SECTOR(S)

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

SET FEATURES

SET MULTIPLE MODE

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

CHECK POWER MODE

FLUSH CACHE

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

SMART: except for SMART Read Attribute values and SMART Read Attribute

Thresholds

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

Figure 5.5 shows the protocol for the command execution without data transfer.

BSY

Parameter write

~

DRDY

INTRQ

Command

Status read

Figure 5.5

Protocol for the command execution without data transfer

C141-E077-01EN 5 - 71

5.4.4

Other commands

READ MULTIPLE

SLEEP

WRITE MULTIPLE

See the description of each command.

5.4.5

DMA data transfer commands

READ DMA

WRITE DMA

Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE

SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

The interrupt processing for the DMA transfer differs the following point.

The interrupt processing for the DMA transfer differs the following point.

a) The host writes any parameters to the Features, Sector Count, Sector Number,

Cylinder, and Device/Head register.

b) The host initializes the DMA channel c) The host writes a command code in the Command register.

d) The device sets the BSY bit of the Status register.

e) The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts either the BSY bit during DMA data transfer.

f) When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal.

g) The host reads the Status register.

h) The host resets the DMA channel.

5 - 72 C141-E077-01EN

BSY

Parameter write a

~

DRDY

INTRQ

DRQ

Data transfer

Command c, d e

• •

• •

• • f

Expanded

[Multiword DMA transfer]

DRQ

DMARQ

DMACK-

IOR- or

IOW-

Word 0

• • • •

• • • •

• • • •

• • • •

1 n-1

Figure 5.6

Normal DMA data transfer n

Status read g

C141-E077-01EN 5 - 73

5.5

Ultra DMA Feature Set

5.5.1

Overview

Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra

DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a

READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts

DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0) is generated by the same agent (either host or device) that drives the data onto the bus.

Ownership of DD (15:0) and this data strobe signal are given either to the device during an

Ultra DMA data in burst or to the host for an Ultra DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a

STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. The highest fundamental frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the maximum frequency for PIO Mode 4 and DMA Mode 2).

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the

Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time. All timing requirements for a selected Ultra DMA Mode shall be satisfied. Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and

1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence. An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non-Ultra DMA Modes after executing a

Power on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its

CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

5 - 74 C141-E077-01EN

5.5.2

Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra

DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).

In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or

HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or

HSTROBE. The following are general Ultra DMA rules.

a) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to the subsequent negation of DMACK-.

b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst.

5.5.3

Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of

DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall negate HDMARDY-.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The host shall release DD (15:0) within t

AZ

after asserting DMACK-.

8) The device may assert DSTROBE t

ZIORDY

after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.

9) The host shall negate STOP and assert HDMARDY- within t

ENV

after asserting DMACK-.

After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

10) The device shall drive DD (15:0) no sooner than t

ZAD

after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

C141-E077-01EN 5 - 75

11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10).

12) To transfer the first word of data the device shall negate DSTROBE within t

FS

after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than t

DVS

after driving the first word of data onto DD (15:0).

5.5.3.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.3 and 5.6.3.2 for specific timing requirements):

1) The device shall drive a data word onto DD (15:0).

2) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS after changing the state of DD (15:0). The device shall generate a DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t

CYC

for the selected Ultra DMA mode.

3) The device shall not change the state of DD (15:0) until at least t

DVH

after generating a

DSTROBE edge to latch the data.

4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.3.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.4 and 5.6.3.2 for specific timing requirements).

a) Device pausing an Ultra DMA data in burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.

NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t

RP

before asserting STOP.

3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

b) Host pausing an Ultra DMA data in burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by negating HDMARDY-.

5 - 76 C141-E077-01EN

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.5 and 5.6.3.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating

DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last

DSTROBE edge. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated DMARQ.

The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (4) and (5) may occur at the same time.

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5):

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

C141-E077-01EN 5 - 77

5 - 78

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

13) The host shall not negate STOP no assert HDMARDY- until at least t

ACK

after negating DMACK-.

14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):

1) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall assert STOP no sooner than t

RP

after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

6) The device shall negate DMARQ within t

LI

after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

9) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).

C141-E077-01EN

10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

11) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

14) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

15) The host shall neither negate STOP nor assert HDMARDY- until at least t

ACK

after the host has negated DMACK-.

16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.4

Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst.

3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall assert HSTROBE.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4), and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The device may negate DDMARDY- t

ZIORDY

after the host has asserted DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8) The host shall negate STOP within t

ENV

after asserting DMACK-. The host shall not assert

STOP until after the first negation of HSTROBE.

C141-E077-01EN 5 - 79

9) The device shall assert DDMARDY- within t

LI

after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

LI

after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than t

DVS

after the driving the first word of data onto DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):

1) The host shall drive a data word onto DD (15:0).

2) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3) The host shall not change the state of DD (15:0) until at least t

DVH

after generating an

HSTROBE edge to latch the data.

4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).

a) Host pausing an Ultra DMA data out burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate

DDMARDY- and wait t

RP

before negating DMARQ.

3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

5 - 80 C141-E077-01EN

b) Device pausing an Ultra DMA data out burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by negating DDMARDY-.

3) The host shall stop generating HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):

1) The host shall initiate termination of an Ultra DMA burst by not generating

HSTROBE edges.

2) The host shall assert STOP no sooner than t

SS

after it last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

3) The device shall negate DMARQ within t

LI

after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4) The device shall negate DDMARDY- with t

LI

after the host has negated STOP. The device shall not assert DDMARDY- again until after the Ultra DMA burst termination is complete.

5) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

6) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)

7) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

C141-E077-01EN 5 - 81

5 - 82

9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10) The device shall release DDMARDY- within t

IORDYZ

after the host has negated

DMACK-.

11) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating DMACK-.

12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements):

1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.

3) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall negate DMARQ no sooner than t

RP

after negating DDMARDY-.

The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

6) The host shall assert STOP with t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

7) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

C141-E077-01EN

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DDMARDY- within t

IORDYZ

after the host has negated DMACK-.

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after negating

DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.5

Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a) Both the host and the device shall have a 16-bit CRC calculation function.

b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous

Ultra DMa burst in the same command. If a miscompare error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one.

ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

C141-E077-01EN 5 - 83

I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

5.5.6

Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.15 Recommended series termination for Ultra DMA

Signal

DIOR-:HDMARDY-:HSTROBE

DIOW-:STOP

CS0-, CS1-

DA0, DA1, DA2

DMACK-

DD15 through DD0

DMARQ

INTRQ

IORDY:DDMARDY-:DSTROBE

Host Termination

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

Device Termination

120 ohm A.I.

*1

82 ohm

82 ohm

82 ohm

82 ohm

120 ohm A.I.

*1

22 ohm

22 ohm

22 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA

Mode. For signals also requiring a pull-up or pull-down resistor at the host see

Figure 5.7.

*1: “A.I.” means an Active Inductance.

5 - 84

Figure 5.7

Ultra DMA termination with pull-up or pull-down

C141-E077-01EN

5.6

Timing

5.6.1

PIO data transfer

Figure 5.8 shows of the data transfer timing between the device and the host system.

t0

Addresses t1 t9

DIOR-/DIOWt2 t2i

Write data

DD0-DD15 t3 t4

Read data

DD0-DD15 t5 t6 t10 t11

IORDY t12 t10 t11 t12 t6 t9 t4 t5

Symbol t0 t1 t2 t2i t3

Timing parameter

Cycle time

Data register selection setup time for DIOR-/DIOW-

Pulse width of DIOR-/DIOW-

Recovery time of DIOR-/DIOW-

Data setup time for DIOW-

Data hold time for DIOW-

Time from DIOR- assertion to read data available

Data hold time for DIOR-

Data register selection hold time for DIOR-/DIOW-

Time from DIOR-/DIOW- assertion to IORDY "low" level

Time from validity of read data to IORDY "high" level

Pulse width of IORDY

Figure 5.8

PIO data transfer timing

Min.

Max.

Unit

120

25

— ns ns

70

25

20

— ns ns ns

10 —

— 50

5

10

0

35

— 1,250 ns ns ns ns ns ns ns

C141-E077-01EN 5 - 85

5.6.2

Multiword data transfer

Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system.

t0

DMARQ

DMACK-

DIOR-/DIOWtI tC tD tJ tK

Write data

DD0-DD15 tG tH

Read data

DD0-DD15 tE tF

Symbol t0 tC

Timing parameter

Cycle time

Delay time from DMACK assertion to DMARQ negation tH tI tJ tD tE tF tG tK

Pulse width of DIOR-/DIOW-

Data setup time for DIOR-

Data hold time for DIOR-

Data setup time for DIOW-

Data hold time for DIOW-

DMACK setup time for DIOR-/DIOW-

DMACK hold time for DIOR-/DIOW-

Continuous time of high level for DIOR-/DIOW-

Figure 5.9

Multiword DMA data transfer timing (mode 2)

10

0

5

25

Min.

Max.

Unit

120 — ns

— 35 ns

70

5

20

30

— ns ns ns ns

— ns ns ns ns

5 - 86 C141-E077-01EN

5.6.3

Ultra DMA data transfer

Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.

Table 5.16 contains the values for the timings for each of the Ultra DMA Modes.

5.6.3.1 Initiating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.10 Initiating an Ultra DMA data in burst

C141-E077-01EN 5 - 87

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2) t t t t t t t t t t t t t t t t t t t

NAME

2CYCTYP

CYC

2CYC

DS

DH

DVS

DVH

FS

LI

MLI

UI

AZ

ZAH

ZAD

ENV

SR

RFS

RP

IORDYZ

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)

240 160 120 90 60 Typical sustained average two cycle time

112 73 54 39 25 Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)

230 154 115 86 57

15

5

70

6

0

0

20

230

150

10

5

48

6

0

0

20

200

150

7

5

30

6

0

0

20

170

150

7

5

20

6

0

0

20

130

100

5

5

6

6

0

0

20

Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)

Data setup time (at recipient)

(see Note 4)

Data hold time (at recipient)

(see Note 4)

Data valid setup time at sender (from data valid until STROBE edge)

(see Note 5)

Data valid hold time at sender (from

STROBE edge until data may become invalid) (see Note 5)

120 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

100 Limited interlock time (see Note 3)

Interlock time with minimum

(see Note 3)

0 0 0 0 0

20

0

20

160

10

70

50

75

20

20

0

20

125

10

70

30

70

20

20

0

20

100

10

70

20

60

20

20

0

20

100

10

55

NA

60

20

20

0

20

100

Unlimited interlock time (see Note 3)

10 Maximum time allowed for output drivers to release (from asserted or negated)

Minimum delay time required for output

Drivers to assert or negate (from released)

55 Envelope time (from DMACK- to

STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation)

NA STROBE-to-DMARDY-time (if

DMARDY- is negated before this long after STROBE edge, the recipient shall receive no more than one additional data word)

60 Ready-to-final-STROBE time (no

STROBE edges shall be sent this long after negation of DMARDY-)

Ready-to-pause time (that recipient shall wait to pause after negating

DMARDY-)

20 Maximum time before releasing

IORDY

5 - 88 C141-E077-01EN

Table 5.16 Ultra DMA data burst timing requirements (2 of 2) t

NAME

ZIORDY

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)

0 0 0 0 0 Minimum time before driving

IORDY t

ACK

20 20 20 20 20 Setup and hold times for DMACK-

(before assertion or negation) t

SS

50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of

STOP (when sender terminates a burst)

Notes:

1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter

RFS

after the negation of

DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.

2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.

3) t

UI

, t

MLI

and t

LI

indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for

UI

is an unlimited interlock that has no maximum time value. t is a

LI

is a limited time-out that has a defined maximum.

4) Special cabling shall be required in order to meet data setup (t ) and data hold (t

DH

) times in modes 3 and 4.

5) Timing for t

DVS

and t

DVH

shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.

C141-E077-01EN 5 - 89

5.6.3.3 Sustained Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

Figure 5.11 Sustained Ultra DMA data in burst

5 - 90 C141-E077-01EN

5.6.3.4 Host pausing an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t

RP

after HDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the host may receive zero, one or two more data words from the device.

Figure 5.12 Host pausing an Ultra DMA data in burst

C141-E077-01EN 5 - 91

5.6.3.5 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.13 Device terminating an Ultra DMA data in burst

5 - 92 C141-E077-01EN

5.6.3.6 Host terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.14 Host terminating an Ultra DMA data in burst

C141-E077-01EN 5 - 93

5.6.3.7 Initiating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.15 Initiating an Ultra DMA data out burst

5 - 94 C141-E077-01EN

5.6.3.8 Sustained Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

Figure 5.16 Sustained Ultra DMA data out burst

C141-E077-01EN 5 - 95

5.6.3.9 Device pausing an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t

RP

after DDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the device may receive zero, one or two more data words from the host.

Figure 5.17 Device pausing an Ultra DMA data out burst

5 - 96 C141-E077-01EN

5.6.3.10 Host terminating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.18 Host terminating an Ultra DMA data out burst

C141-E077-01EN 5 - 97

5.6.3.11 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.19 Device terminating an Ultra DMA data out burst

5 - 98 C141-E077-01EN

5.6.4

Power-on and reset

Figure 5.20 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

Clear Reset *1

Power-on

RESET-

Software reset tM tN

BSY

DASPtP

*1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset.

(2) Master and slave devices are present (2-drives configuration)

[Master device]

BSY

DASP-

[Slave device]

BSY

PDIAG-

DASP-

Clear Reset tN tP tQ tS tR

Symbol tM Pulse width of RESET-

Timing parameter tN tP tQ tR tS

Time from RESET- negation to BSY set

Time from RESET- negation to DASP- or DIAG- negation

Self-diagnostics execution time

Time from RESET- negation to DASP- assertion (slave device)

Duration of DASP- assertion

Figure 5.20 Power-on Reset Timing

Min.

Max.

Unit

25 —

µ s

— 400 ns

— 1

— 30 ms s

— 400

— 31 ms s

C141-E077-01EN 5 - 99

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