5.1 Physical Interface. Fujitsu MPE3XXXAT

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5.1

Physical Interface

5.1.1

Interface signals

Table 5.1 shows the interface signals.

Table 5.1

Interface signals

Description Host

Cable select

Chip select 0

Chip select 1

Data bus bit 0

Data bus bit 1

Data bus bit 2

Data bus bit 3

Data bus bit 4

Data bus bit 5

Data bus bit 6

Data bus bit 7

Data bus bit 8

Data bus bit 9

Data bus bit 10

Data bus bit 11

Data bus bit 12

Data bus bit 13

Data bus bit 14

Data bus bit 15

Device active or slave present

Device address bit 0

Device address bit 1

Device address bit 2

DMA acknowledge

DMA request

Interrupt request

I/O read

DMA ready during Ultra DMA data in bursts

Data strobe during Ultra DMA data out bursts

I/O ready

DMA ready during Ultra DMA data out bursts

Data strobe during Ultra DMA data in bursts

I/O write

Stop during Ultra DMA data bursts

Passed diagnostics

Cable type detection

Reset

Dir see note

↔ see note see note

Dev

Note See signal descriptions

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

DASP–

DA0

DA1

DA2

DMACK–

DMARQ

Acrorym

CSEL

CS0–

CS1–

DD0

DD1

DD2

DD3

DD4

INTRQ

DIOR–

HDMARDY–

HSTROBE

IORDY

DDMARDY–

DSTROBE

DIOW–

STOP

PDIAG–

CBLID–

RESET–

5 - 2 C141-E077-01EN

5.1.2

Signal assignment on the connector

Table 5.2 shows the signal assignment on the interface connector.

Pin No.

25

27

29

31

17

19

21

23

33

35

37

39

9

11

13

15

5

7

1

3

Table 5.2

Signal assignment on the interface connector

Signal

RESET–

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GND

DMARQ

DIOW–, STOP

DIOR–, HDMARDY–, HSTROBE

IORDY, DDMARDY–,

DSTROBE

DMACK–

INTRQ

DA1

DA0

CS0–

DASP–

Pin No.

26

28

30

32

18

20

22

24

34

36

38

40

10

12

14

16

6

8

2

4

Signal

GND

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

(KEY)

GND

GND

GND

CSEL

GND reserved

PDIAG–, CBLID–

DA2

CS1–

GND

[signal]

RESET–

DATA 0-15

DIOW–, STOP

[I/O] [Description]

I Reset signal from the host. This signal is low active and is asserted for a minimum of 25

µ s during power on. The device has a 10 k

pull-up resistor on this signal.

I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer

I DIOW– is the strobe signal asserted by the host to write device registers or the data port.

DIOW– shall be negated by the host prior to initiation of an Ultra

DMA burst. STOP shall be negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra

DMA burst.

C141-E077-01EN 5 - 3

5 - 4

DIOR–

HDMARDY–

HSTROBE

INTRQ

CS0–

CS1–

DA 0-2

KEY

[signal]

PIDAG–

CBLID–

DASP–

[I/O] [Description]

I

I DIOR– is the strobe signal asserted by the host to read device registers or the data port.

HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts.

The host may negate HDMARDY- to pause an Ultra DMA data in burst.

I HSTROBE is the data out strobe signal from the host for an Ultra

DMA data out burst. Both the rising and falling edge of

HSTROBE latch the data from DATA 0-15 into the device. The host may stop generating HSTROBE edges to pause an Ultra

DMA data out burst.

O Interrupt signal to the host.

This signal is negated in the following cases:

– assertion of RESET– signal

– Reset by SRST of the Device Control register

– Write to the command register by the host

– Read of the status register by the host

– Completion of sector data transfer

(without reading the Status register)

When the device is not selected or interrupt is disabled, the

INTRQ

Signal shall be in a high impedance state.

I

I

I Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers.

Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

Binary decoded address signals asserted by the host to access task file registers.

Key pin for prevention of erroneous connector insertion –

I/O This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This signal is used to detect the cable type (80 or 40-conductor cable) installed in the system. This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This is a time-multiplexed signal that indicates that the device is active and a slave device is present.

This signal is pulled up to +5 V through 10 k

resistor at each device.

C141-E077-01EN

[signal]

IORDY

DDMARDY–

DSTROBE

CSEL

DMACK–

DMARQ

GND

[I/O] [Description]

O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request.

O DDMARDY– is a flow control signal for Ultra DMA data out bursts.

This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate DDMARDY– to pause an Ultra DMA data out burst.

O DSTROBE is the data in strobe signal from the device for an Ultra

DMA data in burst. Both the rising and falling edge of

DSTROBE latch the data from DATA 0-15 into the host. The device may stop generating DSTROBE edges to pause an Ultra

DMA data in burst.

I

I

This signal to configure the device as a master or a slave device.

When CSEL signal is grounded, the IDD is a master device.

When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 10 k

resistor.

The host system asserts this signal as a response that the host system receive data or to indicate that data is valid.

O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system

(at reading) or from the host system (at writing).

The direction of data transfer is controlled by the IOR- and IOWsignals. In other word, the device negates the DMARQ signal after the host system asserts the DMACK– signal. When there is another data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCW16–, CS0– and

CS1- signals are not asserted. The DMA data transfer is a 16-bit data transfer. The device has a 10 k

pull-down resistor on this signal.

– Grounded

Note:

"I" indicates input signal from the host to the device.

"O" indicates output signal from the device to the host.

"I/O" indicates common output or bi-directional signal between the host and the device.

C141-E077-01EN 5 - 5

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