5.5 Ultra DMA Feature Set. Fujitsu MPE3XXXAT

Add to My manuals
191 Pages

advertisement

5.5 Ultra DMA Feature Set. Fujitsu MPE3XXXAT | Manualzz

5.5

Ultra DMA Feature Set

5.5.1

Overview

Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra

DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a

READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts

DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0) is generated by the same agent (either host or device) that drives the data onto the bus.

Ownership of DD (15:0) and this data strobe signal are given either to the device during an

Ultra DMA data in burst or to the host for an Ultra DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a

STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. The highest fundamental frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the maximum frequency for PIO Mode 4 and DMA Mode 2).

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the

Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time. All timing requirements for a selected Ultra DMA Mode shall be satisfied. Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and

1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence. An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non-Ultra DMA Modes after executing a

Power on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its

CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

5 - 74 C141-E077-01EN

5.5.2

Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra

DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).

In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or

HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or

HSTROBE. The following are general Ultra DMA rules.

a) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to the subsequent negation of DMACK-.

b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst.

5.5.3

Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of

DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall negate HDMARDY-.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The host shall release DD (15:0) within t

AZ

after asserting DMACK-.

8) The device may assert DSTROBE t

ZIORDY

after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.

9) The host shall negate STOP and assert HDMARDY- within t

ENV

after asserting DMACK-.

After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

10) The device shall drive DD (15:0) no sooner than t

ZAD

after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

C141-E077-01EN 5 - 75

11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10).

12) To transfer the first word of data the device shall negate DSTROBE within t

FS

after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than t

DVS

after driving the first word of data onto DD (15:0).

5.5.3.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.3 and 5.6.3.2 for specific timing requirements):

1) The device shall drive a data word onto DD (15:0).

2) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS after changing the state of DD (15:0). The device shall generate a DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t

CYC

for the selected Ultra DMA mode.

3) The device shall not change the state of DD (15:0) until at least t

DVH

after generating a

DSTROBE edge to latch the data.

4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.3.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.4 and 5.6.3.2 for specific timing requirements).

a) Device pausing an Ultra DMA data in burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.

NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t

RP

before asserting STOP.

3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

b) Host pausing an Ultra DMA data in burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by negating HDMARDY-.

5 - 76 C141-E077-01EN

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.5 and 5.6.3.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating

DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last

DSTROBE edge. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated DMARQ.

The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated. Steps (4) and (5) may occur at the same time.

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5):

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

C141-E077-01EN 5 - 77

5 - 78

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

13) The host shall not negate STOP no assert HDMARDY- until at least t

ACK

after negating DMACK-.

14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):

1) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall assert STOP no sooner than t

RP

after negating HDMARDY-. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

6) The device shall negate DMARQ within t

LI

after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

9) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).

C141-E077-01EN

10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

11) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

14) The device shall release DSTROBE within t

IORDYZ

after the host negates DMACK-.

15) The host shall neither negate STOP nor assert HDMARDY- until at least t

ACK

after the host has negated DMACK-.

16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.4

Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst.

3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert

STOP.

4) The host shall assert HSTROBE.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,

DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4), and (5) shall have occurred at least t

ACK

before the host asserts DMACK-.

The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7) The device may negate DDMARDY- t

ZIORDY

after the host has asserted DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8) The host shall negate STOP within t

ENV

after asserting DMACK-. The host shall not assert

STOP until after the first negation of HSTROBE.

C141-E077-01EN 5 - 79

9) The device shall assert DDMARDY- within t

LI

after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

LI

after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than t

DVS

after the driving the first word of data onto DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):

1) The host shall drive a data word onto DD (15:0).

2) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3) The host shall not change the state of DD (15:0) until at least t

DVH

after generating an

HSTROBE edge to latch the data.

4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra

DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).

a) Host pausing an Ultra DMA data out burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate

DDMARDY- and wait t

RP

before negating DMARQ.

3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

5 - 80 C141-E077-01EN

b) Device pausing an Ultra DMA data out burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra

DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by negating DDMARDY-.

3) The host shall stop generating HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):

1) The host shall initiate termination of an Ultra DMA burst by not generating

HSTROBE edges.

2) The host shall assert STOP no sooner than t

SS

after it last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

3) The device shall negate DMARQ within t

LI

after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4) The device shall negate DDMARDY- with t

LI

after the host has negated STOP. The device shall not assert DDMARDY- again until after the Ultra DMA burst termination is complete.

5) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

6) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)

7) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

C141-E077-01EN 5 - 81

5 - 82

9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10) The device shall release DDMARDY- within t

IORDYZ

after the host has negated

DMACK-.

11) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating DMACK-.

12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

b) Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements):

1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.

3) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating

DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an

HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall negate DMARQ no sooner than t

RP

after negating DDMARDY-.

The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

6) The host shall assert STOP with t

LI

after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.

7) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted

HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of

DMACK-.

C141-E077-01EN

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DDMARDY- within t

IORDYZ

after the host has negated DMACK-.

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after negating

DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK after negating DMACK.

5.5.5

Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a) Both the host and the device shall have a 16-bit CRC calculation function.

b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of DMACK-.

f) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous

Ultra DMa burst in the same command. If a miscompare error occurs during one or more

Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one.

ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

C141-E077-01EN 5 - 83

I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last.

5.5.6

Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.15 Recommended series termination for Ultra DMA

Signal

DIOR-:HDMARDY-:HSTROBE

DIOW-:STOP

CS0-, CS1-

DA0, DA1, DA2

DMACK-

DD15 through DD0

DMARQ

INTRQ

IORDY:DDMARDY-:DSTROBE

Host Termination

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

Device Termination

120 ohm A.I.

*1

82 ohm

82 ohm

82 ohm

82 ohm

120 ohm A.I.

*1

22 ohm

22 ohm

22 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA

Mode. For signals also requiring a pull-up or pull-down resistor at the host see

Figure 5.7.

*1: “A.I.” means an Active Inductance.

5 - 84

Figure 5.7

Ultra DMA termination with pull-up or pull-down

C141-E077-01EN

advertisement

Related manuals

advertisement

Table of contents