5.6 Timing. Fujitsu MPE3XXXAT

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5.6 Timing. Fujitsu MPE3XXXAT | Manualzz

5.6

Timing

5.6.1

PIO data transfer

Figure 5.8 shows of the data transfer timing between the device and the host system.

t0

Addresses t1 t9

DIOR-/DIOWt2 t2i

Write data

DD0-DD15 t3 t4

Read data

DD0-DD15 t5 t6 t10 t11

IORDY t12 t10 t11 t12 t6 t9 t4 t5

Symbol t0 t1 t2 t2i t3

Timing parameter

Cycle time

Data register selection setup time for DIOR-/DIOW-

Pulse width of DIOR-/DIOW-

Recovery time of DIOR-/DIOW-

Data setup time for DIOW-

Data hold time for DIOW-

Time from DIOR- assertion to read data available

Data hold time for DIOR-

Data register selection hold time for DIOR-/DIOW-

Time from DIOR-/DIOW- assertion to IORDY "low" level

Time from validity of read data to IORDY "high" level

Pulse width of IORDY

Figure 5.8

PIO data transfer timing

Min.

Max.

Unit

120

25

— ns ns

70

25

20

— ns ns ns

10 —

— 50

5

10

0

35

— 1,250 ns ns ns ns ns ns ns

C141-E077-01EN 5 - 85

5.6.2

Multiword data transfer

Figure 5.9 shows the multiword DMA data transfer timing between the device and the host system.

t0

DMARQ

DMACK-

DIOR-/DIOWtI tC tD tJ tK

Write data

DD0-DD15 tG tH

Read data

DD0-DD15 tE tF

Symbol t0 tC

Timing parameter

Cycle time

Delay time from DMACK assertion to DMARQ negation tH tI tJ tD tE tF tG tK

Pulse width of DIOR-/DIOW-

Data setup time for DIOR-

Data hold time for DIOR-

Data setup time for DIOW-

Data hold time for DIOW-

DMACK setup time for DIOR-/DIOW-

DMACK hold time for DIOR-/DIOW-

Continuous time of high level for DIOR-/DIOW-

Figure 5.9

Multiword DMA data transfer timing (mode 2)

10

0

5

25

Min.

Max.

Unit

120 — ns

— 35 ns

70

5

20

30

— ns ns ns ns

— ns ns ns ns

5 - 86 C141-E077-01EN

5.6.3

Ultra DMA data transfer

Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.

Table 5.16 contains the values for the timings for each of the Ultra DMA Modes.

5.6.3.1 Initiating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.10 Initiating an Ultra DMA data in burst

C141-E077-01EN 5 - 87

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.16 Ultra DMA data burst timing requirements (1 of 2) t t t t t t t t t t t t t t t t t t t

NAME

2CYCTYP

CYC

2CYC

DS

DH

DVS

DVH

FS

LI

MLI

UI

AZ

ZAH

ZAD

ENV

SR

RFS

RP

IORDYZ

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)

240 160 120 90 60 Typical sustained average two cycle time

112 73 54 39 25 Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)

230 154 115 86 57

15

5

70

6

0

0

20

230

150

10

5

48

6

0

0

20

200

150

7

5

30

6

0

0

20

170

150

7

5

20

6

0

0

20

130

100

5

5

6

6

0

0

20

Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)

Data setup time (at recipient)

(see Note 4)

Data hold time (at recipient)

(see Note 4)

Data valid setup time at sender (from data valid until STROBE edge)

(see Note 5)

Data valid hold time at sender (from

STROBE edge until data may become invalid) (see Note 5)

120 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

100 Limited interlock time (see Note 3)

Interlock time with minimum

(see Note 3)

0 0 0 0 0

20

0

20

160

10

70

50

75

20

20

0

20

125

10

70

30

70

20

20

0

20

100

10

70

20

60

20

20

0

20

100

10

55

NA

60

20

20

0

20

100

Unlimited interlock time (see Note 3)

10 Maximum time allowed for output drivers to release (from asserted or negated)

Minimum delay time required for output

Drivers to assert or negate (from released)

55 Envelope time (from DMACK- to

STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation)

NA STROBE-to-DMARDY-time (if

DMARDY- is negated before this long after STROBE edge, the recipient shall receive no more than one additional data word)

60 Ready-to-final-STROBE time (no

STROBE edges shall be sent this long after negation of DMARDY-)

Ready-to-pause time (that recipient shall wait to pause after negating

DMARDY-)

20 Maximum time before releasing

IORDY

5 - 88 C141-E077-01EN

Table 5.16 Ultra DMA data burst timing requirements (2 of 2) t

NAME

ZIORDY

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)

0 0 0 0 0 Minimum time before driving

IORDY t

ACK

20 20 20 20 20 Setup and hold times for DMACK-

(before assertion or negation) t

SS

50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of

STOP (when sender terminates a burst)

Notes:

1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter

RFS

after the negation of

DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.

2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.

3) t

UI

, t

MLI

and t

LI

indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for

UI

is an unlimited interlock that has no maximum time value. t is a

LI

is a limited time-out that has a defined maximum.

4) Special cabling shall be required in order to meet data setup (t ) and data hold (t

DH

) times in modes 3 and 4.

5) Timing for t

DVS

and t

DVH

shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.

C141-E077-01EN 5 - 89

5.6.3.3 Sustained Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

Figure 5.11 Sustained Ultra DMA data in burst

5 - 90 C141-E077-01EN

5.6.3.4 Host pausing an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t

RP

after HDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the host may receive zero, one or two more data words from the device.

Figure 5.12 Host pausing an Ultra DMA data in burst

C141-E077-01EN 5 - 91

5.6.3.5 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.13 Device terminating an Ultra DMA data in burst

5 - 92 C141-E077-01EN

5.6.3.6 Host terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.14 Host terminating an Ultra DMA data in burst

C141-E077-01EN 5 - 93

5.6.3.7 Initiating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

Figure 5.15 Initiating an Ultra DMA data out burst

5 - 94 C141-E077-01EN

5.6.3.8 Sustained Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

Figure 5.16 Sustained Ultra DMA data out burst

C141-E077-01EN 5 - 95

5.6.3.9 Device pausing an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Notes:

1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t

RP

after DDMARDY- is negated.

2) If the t

SR

timing is not satisfied, the device may receive zero, one or two more data words from the host.

Figure 5.17 Device pausing an Ultra DMA data out burst

5 - 96 C141-E077-01EN

5.6.3.10 Host terminating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.18 Host terminating an Ultra DMA data out burst

C141-E077-01EN 5 - 97

5.6.3.11 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Figure 5.19 Device terminating an Ultra DMA data out burst

5 - 98 C141-E077-01EN

5.6.4

Power-on and reset

Figure 5.20 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

Clear Reset *1

Power-on

RESET-

Software reset tM tN

BSY

DASPtP

*1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset.

(2) Master and slave devices are present (2-drives configuration)

[Master device]

BSY

DASP-

[Slave device]

BSY

PDIAG-

DASP-

Clear Reset tN tP tQ tS tR

Symbol tM Pulse width of RESET-

Timing parameter tN tP tQ tR tS

Time from RESET- negation to BSY set

Time from RESET- negation to DASP- or DIAG- negation

Self-diagnostics execution time

Time from RESET- negation to DASP- assertion (slave device)

Duration of DASP- assertion

Figure 5.20 Power-on Reset Timing

Min.

Max.

Unit

25 —

µ s

— 400 ns

— 1

— 30 ms s

— 400

— 31 ms s

C141-E077-01EN 5 - 99

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