M9506A 5-Slot AXIe Chassis
User Guide
7
For Module Developers
This chapter provides a detailed look at the AXIe chassis backplane and connectors, provided as a quick reference for AXIe module developers.
Module Types 120
ATCA and AXIe Requirements 121
ATCA Requirements and Exceptions for AXIe 1.0
121
AXIe Extensions to AdvancedTCA ® 123
Chassis Backplane Connections 124
M9506A Backplane 124
Zone 1 Connector Layout 125
Zone 1 Connector Usage 125
Zone 1 Pin Assignments 126
Zone 2 Connector Layout 127
Zone 2 Connector Usage 128
Zone 2 Pin Assignments 129
119
For Module Developers Module Types
Module Types
The AXIe chassis provide a wealth of options for high speed, low voltage differential (LVDS) signaling. Whether you can develop individual instrument modules or modular instrumentation sets, communication between modules may travel across the backplane.
Depending on your application, you have the flexibility to create a variety of module types.
Instrument Module: An instrument module can go in any slot and will typically use the AXIe trigger bus resources. It will not typically use the local bus unless it is part of an instrumentation set.
Instrumentation Sets: AXIe provides the opportunity for you to create scalable, modular measurement and test systems which can occupy two or more chassis slots.
– If you create a two-module instrumentation set intended to occupy adjacent slots, you can utilize up to 62 LVDS backplane local bus lines.
This set could be designed to function in any two adjacent slots of the
M9506A.
– You can also create instrumentation sets with up to five AXIe modules,and may implement backplane features and specify module placement as required.
– Your multiple module instrumentation set can include an instrument hub module installed in slot 1. That hub may use AXIe trigger bus features, communicate between adjacent modules using the local bus, and provide the hub for a secondary x4 backplane data fabric to slots 2 through 5.
120 Keysight M9506A 5-Slot AXIe Chassis User Guide
ATCA and AXIe Requirements For Module Developers
ATCA and AXIe Requirements
The Keysight AXIe (ATCA eXtensions for Instrumentation) chassis backplanes used in the M9506A comply with the AXIe 1.0 Base Architecture Specification.
AXIe 1.0 is based on AdvancedTCA® (ATCA) architecture, expanded with several eXtensions , all of which will remain electrically compatible with standard ATCA blades. These modifications provide timing, triggering, local bus signaling and data transport features.
Keysight provides this chapter as a quick backplane reference for developers of
AXIe instrument and instrument hub modules. It gives a brief explanation of how the M9506A chassis implement AXIe features, and provides signal connection pin assignments for module backplane connectors.
This summary of AXIe requirements is not intended to replace the applicable module design standards, which specify mechanical, electrical, and logical interfaces between module and chassis. AXIe modules must comply with:
AXIe 1.0 Base Architecture Specification, available at http://www.axiestandard.org
AdvancedTCA® PICMG 3.0® Specification, available at http://www.picmg.org
Most ATCA modules should be able to work in an AXIe environment. Conversely, developers should design AXIe modules to be compatible in an ATCA environment.
ATCA Requirements and Exceptions for AXIe 1.0
Mechanical
AXIe modules must meet all ATCA mechanical requirements for modules.
Exception: AXIe 1.0 chassis do not accommodate rear transition modules
(RTM).
Hardware Platform (shelf) Management
AXIe modules must incorporate the
ATCA hardware platform management features.
Exceptions:
– AXIe uses an intelligent platform bus (IPMB) for platform management communication between the intelligent FRUs (for example: shelf manager, module IPMC) in a chassis. This IPMB conforms to the ATCA requirements for IPMB-0, but with no IPMB redundancy.
– AXIe modules are not required to support the complete hot swap capabilities of ATCA. However, the module’s FRUs are required to support all of the operational states required for ATCA front boards.
Keysight M9506A 5-Slot AXIe Chassis User Guide 121
122
For Module Developers ATCA and AXIe Requirements
– AXIe modules are not required to have the handle switches that sense the module’s insertion and impending removal from the chassis nor the blue hot-swap LEDs.
– AXIe modules do not implement ATCA electronic keying, metallic test bus, and ringing bus.
Power Distribution
Dual power supplies are provided to each slot. AXIe
Modules may use either or both supply feeds, and must be able to operate over a range from –53VDC to –45VDC.
Data Transport
AXIe modules must comply with all ATCA requirements for
Zone 2 base and fabric interfaces.
Exceptions:
– AXIe modules only implement a single base interface channel (LAN channel 1).
– AXIe modules may connect to data fabric channel 1 or channel 2, or both.
– Data fabric channel 1, if used by the AXIe module, must implement a PCIe connection, operated from the supplied 100MHz reference clock (FCLK).
– Data fabric channel 2, if used by the AXIe module, may implement proprietary protocols.
– AXIe modules may connect to any of the CLK100, SYNC or STRIG signal pairs, any of the 12 AXIe TRIG pairs, and any number of available pairs on either or both local bus ports.
Synchronization Clock
AXIe backplanes maintain the bused topology of most
Synchronization Clock signals, and devices implement the same MLVDS signaling levels as ATCA. The following table provides a brief description of the timing interface signals:
Clock Signal Description
FCLK
CLK100
100 MHz PCIe Reference Clock
Functions as the chassis clock. Slot-to-Slot skew must be less than 100 pS.
SYNC
STRIG
Trigger/Clock synchronization signal. Slot-to-Slot skew must be less than 100 pS.
Direct connection for triggering between the system slot and instrument slots,
Less than 20 pS skew is allowed.
Exceptions:
– AXIe architecture expands the use of the ATCA Synchronization Clock
Interface. The signals and connector pin assignments for AXIe modules differ from ATCA.
Keysight M9506A 5-Slot AXIe Chassis User Guide
ATCA and AXIe Requirements For Module Developers
No Update Channel Interface
Exception:
– The AXIe architecture does not implement the ATCA Update Channel
Interface. AXIe backplanes implement a single bused MLVDS topology for the signals connecting to those Zone 2 connector contacts, and devices implement different signaling schemes as defined in the AXIe specification. AXIe modules must implement electronic keying appropriate to prevent incompatible connections between AXIe and
ATCA devices installed in either system environment.
AXIe Extensions to AdvancedTCA
®
AXIe expands the ATCA specification with several eXtensions , Zone 2 customizations which include:
The AXIe timing interface , providing for specific clock distribution and signaling between the ESM and instrument slots 1 through 5 .
This interface includes timing resources SYNC, CLK100, and STRIG. See
“Clocks and Triggering” on page 84 for a complete functional description
of these timing resources.
A 12 pair MLVDS trigger bus , TRIG[0,11], bused across all slots (the ESM
slot and instrument slots 1 through 5). See “Triggering” on page 88.
A 62 pair local bus for signaling between adjacent instrument slots.
The data transport fabric , Single Star x16 PCIe Gen 3 fabric:
– Channel 1 connects the ESM slot in a star configuration to provide an x16 link to each instrument slot
– Uses a distributed PCIe fabric reference clock (FCLK) driven from the
ESM
AXIe chassis implement an extended set of electronic keying records to assure consistent use of AXIe-defined backplane fabrics and resources.
In the AXIe chassis, the ESM acts as logical slot 1 for base fabric signaling
(LAN) and channel 1 data fabric signaling (PCIe) signaling in addition to shelf management.
Keysight M9506A 5-Slot AXIe Chassis User Guide 123
For Module Developers Chassis Backplane Connections
Chassis Backplane Connections
M9506A Backplane
The photo below reveals the M9506A backplane, with modules removed from all slots. The backplane provides connectors P20 through P24 and J10. Connector designations are shown for instrument slot 1.
A typical module connector layout is illustrated below the backplane photo, with the mating connectors J20 through J24 and P10.
Zone 2 Zone 1
Instrument Slot 5
Logical Slot 6
Instrument Slot 4
Logical Slot 5
Instrument Slot 3
Logical Slot 4
Instrument Slot 2
Logical Slot 3
Instrument Slot 1
Logical Slot 2
ESM Slot
Logical Slot 1
AXIe Module Rear (mating) Edge
124
Depending on module type, you may implement all or none of J20-J24. You will always need connector P10 to power the module.
Keysight M9506A 5-Slot AXIe Chassis User Guide
Chassis Backplane Connections For Module Developers
Zone 1 Connector Layout
The blue jack at far right in each slot is J10, the AXIe Zone 1 backplane connector. Through J10, the chassis distributes power feeds and provides shelf management. AXIe modules should be capable of operating normally from either feed, over a range from –53V to –45V. Your module must provide mating connector P10.
The photo below shows slot 1 from the M9506A, normal chassis orientation. The pin layout for J10 (all slots) is illustrated below the photo.
Zone 1 Backplane Connector J10
Hardware
Management
Unused
Contacts
Power Supplies and mating contacts
Zone 1 Connector Usage
Zone 1 provides these connections to each module slot:
Dual redundant –48 VDC power supplies, per the ATCA specification.
Hardware management circuits. including the Intelligent Platform
Management Bus (IPMB) and Hardware Addressing (HA), per the ATCA specification.
Metallic test and ringing generator buses are not provided in AXIe 1.0.
Connector J10 will physically accommodate P10 pins 17-24 from a legacy
ATCA module, but with no functionality.
Complete circuit definitions and design specifications can be found in the ATCA
3.0 base specification. Pin assignments are listed on the following page.
Keysight M9506A 5-Slot AXIe Chassis User Guide 125
For Module Developers Chassis Backplane Connections
126
Zone 1 Pin Assignments
The Zone 1 pin assignments and circuit definitions for backplane connector J10 and module connector P10 are listed below:
31
32
33
34
27
28
29
30
Power Circuit Contacts for J10/P10
Contact
Number
25
26
ATCA
Designation
Description
SHELF_GND Connection to Shelf Ground and safety ground
LOGIC_GND Ground reference and return for Front Board-to-Front Board logic signals
ENABLE_B Short pin for power sequencing, Feed B, tied to VRTN_B on backplanes
VRTN_A
VRTN_A
EARLY_A
EARLY_B
–48 v return, Feed A
–48 v return, Feed B
–48 v input, Feed A pre-charge
–48 v input, Feed B pre-charge
ENABLE_A Short pin for power sequencing, Feed A, tied to VRTN_A on backplanes
–48V_A
–48V_B
–48 v input, Feed A, uses ENABLE_A to enable converters
–48 v input, Feed B, uses ENABLE_B to enable converters
Legacy ATCA Test Circuit Pins for J10/P10
19
20
21
22
23
24
Contact
Number
17
18
ATCA
Designation
MT1_TIP
MT2_TIP
–RING_A
–RING_B
MT1_RING
MT2_RING
RRTN_A
RRTN_B
Description
These backplane J10 contacts will physically accept pins from ATCA modules, but do not provide ATCA metallic test and ringing generator bus circuits.
Hardware Management Circuit Contacts for J10/P10
13
14
15
16
9
10
11
12
7
8
5
6
Contact
Number
1-4
ATCA
Designation
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7/P
SCL_A
SDA_A
SCL_B
SDA_B
Description
Reserved, do not connect
Hardware address bit 0
Hardware address bit 1
Hardware address bit 2
Hardware address bit 3
Hardware address bit 4
Hardware address bit 5
Hardware address bit 6
Hardware address bit 7 (odd parity bit)
IPMB clock, Port A
IPMB data, Port A
IPMB clock, Port B
IPMB data, Port B
Keysight M9506A 5-Slot AXIe Chassis User Guide
Chassis Backplane Connections For Module Developers
Zone 2 Connector Layout
The Zone 2 connectors provide pins for up to 200 differential signaling pairs per slot (40 pairs per connector), although most slots and many modules will not feature all these connectors.
Zone 2 provides the signal connections for the data transport fabric and AXIe extensions, using P20 through P24; the white plugs in each instrument slot For complete backplane photos, see
“M9506A Backplane” on page 124.
Each Zone 2 plug provides 40 differential signal contact pairs with ground in 10 columns, four pairs to a column. The pin layout for P20 (typical for all Zone 2 connectors) is illustrated below the slot photo.
These plugs use male contacts; the mating module connectors J20 through J24 use female contacts. Note the areas shown with red boxes; these are for alignment/keying.
Keysight M9506A 5-Slot AXIe Chassis User Guide 127
128
For Module Developers Chassis Backplane Connections
Zone 2 Connector Usage
Your module may implement any or none of the Zone 2 connectors. If you want:
to utilize the AXIe trigger, timing, data, and local bus (22 pair) features in your module, load connectors J20 and J23.
to expand the local bus up to 62 pair, load connectors J24 and J21.
to complete a five-slot star hub for data fabric channel 2—used in instrument hub modules only—load connector J22.
The table below provides a locational map linking each AXIe Zone 2 interface type (function) with its backplane connectors
Interface Type
Trigger Bus
Timing Bus
Local Bus
Interface
TRIG[0,11]
STRIG, SYNC, CLK100 and FCLK pairs 0 through 7 pairs 8 through 17 pairs 18 through 37 pairs 38 through 41 pairs 42 through 61
Number of
Signal Pairs
20
4
20
4
12
4
8
10
P20
P23
P24
P20
Chassis
Backplane
Connector
P20
P20
P21
P22 Fabric Channel 3
(PCIe x16)
Fabric Channel 4
(PCIe x16)
Fabric Channel 5
Fabric Channel 6
Fabric Channel 7
Base Channel
Fabric Channel 1
(PCIe x4)
Fabric Channel 2
(PCIe x8) from ESM star hub
4
4
4
4
4
4
4
P22
P22
P22
P22
P23
P23
P23
Keysight M9506A 5-Slot AXIe Chassis User Guide
Chassis Backplane Connections For Module Developers
Complete circuit definitions and design specifications can be found in the ATCA and AXIe specifications. Pin assignments are listed on the following page.
Zone 2 Pin Assignments
The Zone 2 pin assignments and circuit definitions for connector pairs P20/J20 through P24/J24 are listed below. For the local bus assignments:
Pin designations beginning with LBL connect to the adjacent lower slot
Pin designations beginning with LBR connect to the adjacent upper slot
P20/J20
Row Interface Instrument Slot 1-5 (Logical Slot 2-6)
7
8
5
6
9
10
3
4
1
2
Trigger
Trigger
Trigger
Timing
Local Bus ab
LBL[2]+
LBL[4]+
LBL[6]+ cd ef
LBL[7]+ LBL[7]– LBR[6]+
LBR[0]–
LBR[2]–
LBR[4]–
LBR[6– gh
TRIG[0]+ TRIG[0]– TRIG[1]+ TRIG[1]– TRIG[2]+ TRIG[2]– TRIG[3]+ TRIG[3]–
TRIG[4]+ TRIG[4]– TRIG[5]+ TRIG[5]– TRIG[6]+ TRIG[6]– FCLK+
TRIG[7]+ TRIG[7]– TRIG[8]+ TRIG[8]– TRIG[9]+ TRIG[9]– TRIG[0]+ TRIG[0]–
TRIG[11]+ TRIG[11]– STRIG+
LBL[0]+
STRIG– SYNC100+ SYNC100– CLK100+ CLK100–
LBL[0]– LBL[1]+ LBL[1]– LBR[0]+
LBL[2]– LBL[3]+ LBL[3]– LBR[2]+
LBL[4]– LBL[5]+ LBL[5]– LBR[4]+
LBL[6–
LBR[1]+
LBR[3]+
LBR[5]+
LBR[7]+
FCLK–
LBR[1]–
LBR[3]–
LBR[5]–
LBR[7]–
LBL[38]+ LBL[38]– LBL[39]+ LBL[39]– LBR[38]+ LBR[38]– LBR[39]+ LBR[39]–
LBL[40]+ LBL[40]– LBL[41]+ LBL[41]– LBR[40]+ LBR[40]– LBR[41]+ LBR[41]–
P21/J21
7
8
5
6
9
10
3
4
1
2
Row Interface Instrument Slot 1-5 (Logical Slot 2-6) ab cd ef gh
LBL[42]+ LBL[42]– LBL[43]+ LBL[43]– LBR[42]+ LBR[42]– LBR[43]+ LBR[43]–
Add for
62-Pair
Local Bus
LBL[44]+
LBL[46]+
LBL[48]+
LBL[50]+
LBL[44]– LBL[45]+ LBL[45]– LBR[44]+
LBL[46]– LBL[47]+ LBL[47]– LBR[46]+
LBL[48]– LBL[49]+ LBL[49]– LBR[48]+
LBL[50]– LBL[51]+ LBL[51]– LBR[50]+
LBR[44]–
LBR[46]–
LBR[48]–
LBR[50]–
LBR[45]+ LBR[45]–
LBR[47]+ LBR[47]–
LBR[49]+ LBR[49]–
LBR[51]+ LBR[51]–
LBL[52]+ LBL[52]– LBL[53]+ LBL[53]– LBR[52]+ LBR[52]– LBR[53]+ LBR[53]–
LBL[54]+ LBL[54]– LBL[55]+ LBL[55]– LBR[54]+ LBR[54]– LBR[55]+ LBR[55]–
LBL[56]+ LBL[56]– LBL[57]+ LBL[57]– LBR[56]+ LBR[56]– LBR[57]+ LBR[57]–
LBL[58]+ LBL[58]– LBL[59]+ LBL[59]– LBR[58]+ LBR[58]– LBR[59]+ LBR[59]–
LBL[60]+ LBL[60]– LBL[61]+ LBL[61]– LBR[60]+ LBR[60]– LBR[61]+ LBR[61]–
Keysight M9506A 5-Slot AXIe Chassis User Guide 129
130
For Module Developers Chassis Backplane Connections
7
8
5
6
3
4
1
2
9
10
Row Interface
Fabric
Channel 7
Fabric
Channel 6
Fabric
Channel 5
Fabric
Channel 4
Fabric
Channel 3
P22/J22
Instrument Slot 1-5 (Logical Slot 2-6) ab
TX2[7]+
TX0[7]+
TX2[6]+
TX0[6]+
TX2[5]+
TX0[5]+
TX2[4]+
TX0[4]+
TX2[3]+
TX0[3]+ cd ef
TX2[7]– RX2[7]+ RX2[7]– TX3[7]+
TX0[7]–
TX2[6]–
TX2[6]–
TX2[5]–
TX0[5]–
TX2[4]–
TX2[4]–
TX2[3]–
TX0[3]–
RX0[7]+
RX2[6]+
RX0[6]+
RX2[5]+
RX0[5]+
RX2[4]+
RX0[4]+
RX2[3]+
RX0[3]+
RX0[7]–
RX2[6]–
RX0[6]–
RX2[5]–
RX0[5]–
RX2[4]–
RX0[4]–
RX2[3]–
RX0[3]–
TX1[7]+
TX3[6]+
TX1[6]+
TX3[5]+
TX1[5]+
TX3[4]+
TX1[4]+
TX3[3]+
TX1[3]+
TX3[7]–
TX1[7]–
TX3[6]–
TX1[6]–
TX3[5]–
TX1[5]–
TX3[4]–
TX1[4]–
TX3[3]–
TX1[3]– gh
RX3[7]+ RX3[7]–
RX1[7]+ RX1[7]–
RX3[6]+ RX3[6]–
RX1[6]+ RX1[6]–
RX3[5]+ RX3[5]–
RX1[5]+ RX1[5]–
RX3[4]+ RX3[4]–
RX1[4]+ RX1[4]–
RX3[3]+ RX3[3]–
RX1[3]+ RX1[3]–
P23/J23
Row Interface Instrument Slot 1-5 (Logical Slot 2-6)
8
9
6
7
10
3
4
1
2
5
Fabric
Channel 2
Fabric
Channel 1
Base
Channel 1
Local Bus ab
TX2[2]+
TX0[2]+
TX2[1]+
TX0[1]+
BI_DA1+
(Tx1+)
LBL[8]+ cd ef
TX2[2]– RX2[2]+ RX2[2]– TX3[2]+
TX0[2]– RX0[2]+ RX0[2]– TX1[2]+
TX2[1]– RX2[1]+ RX2[1]– TX3[1]+
TX0[1]–
BI_DA1–
(Tx1–)
RX0[1]+
BI_DB1+
(Rx1+)
RX0[1]–
BI_DB1–
(Rx1–)
TX1[1]+
BI_DC1+ BI_DC1– BI_DD1+ BI_DD1–
LBL[8]– LBL[9]+ LBL[9]– LBR[8]+
TX3[2]–
TX1[2]–
TX3[1]–
TX1[1]–
LBR[8]– gh
RX3[2]+
RX1[2]+
RX3[1]+
RX3[2]–
RX1[2]–
RX3[1]–
RX1[1]+ RX1[1]–
LBR[9]+ LBR[9]–
LBL[10]+ LBL[10]– LBL[11]+ LBL[11]– LBR[10]+ LBR[10]– LBR[11]+ LBR[11]–
LBL[12]+ LBL[12– LBL[13]+ LBL[13]– LBR[12]+ LBR[12– LBR[13]+ LBR[13]–
LBL[14]+ LBL[14]– LBL[15]+ LBL[15]– LBR[14]+ LBR[14]– LBR[15]+ LBR[15]–
LBL[16]+ LBL[16]– LBL[17]+ LBL[17]– LBR[16]+ LBR[16]– LBR[17]+ LBR[17]–
P24/J24
7
8
5
6
9
10
3
4
1
2
Row Interface Instrument Slot 1-5 (Logical Slot 2-6) ab cd ef gh
LBL[18]+ LBL[18]– LBL[19]+ LBL[19]– LBR[18]+ LBR[18]– LBR[19]+ LBR[19]–
Add for
42-Pair
Local Bus
LBL[20]+
LBL[22]+
LBL[24]+
LBL[26]+
LBL[20]– LBL[21]+ LBL[21]– LBR[20]+
LBL[22]– LBL[23]+ LBL[23]– LBR[22]+
LBL[24]– LBL[25]+ LBL[25]– LBR[24]+
LBL[26]– LBL[27]+ LBL[27]– LBR[26]+
LBR[20]–
LBR[22]–
LBR[24]–
LBR[26]–
LBR[21]+ LBR[21]–
LBR[23]+ LBR[23]–
LBR[25]+ LBR[25]–
LBR[27]+ LBR[27]–
LBL[28]+ LBL[28]– LBL[29]+ LBL[29]– LBR[28]+ LBR[28]– LBR[29]+ LBR[29]–
LBL[30]+ LBL[30]– LBL[31]+ LBL[31]– LBR[30]+ LBR[30]– LBR[31]+ LBR[31]–
LBL[32]+ LBL[32]– LBL[33]+ LBL[33]– LBR[32]+ LBR[32]– LBR[33]+ LBR[33]–
LBL[34]+ LBL[34]– LBL[35]+ LBL[35]– LBR[34]+ LBR[34]– LBR[35]+ LBR[35]–
LBL[36]+ LBL[36]– LBL[37]+ LBL[37]– LBR[36]+ LBR[36]– LBR[37]+ LBR[37]–
Keysight M9506A 5-Slot AXIe Chassis User Guide
