4.6 Read/write Circuit. Fujitsu C141-E090-02EN

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4.6 Read/write Circuit. Fujitsu C141-E090-02EN | Manualzz


Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the synthesizer in the read channel (RDC).


Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an 4 or 8-channel read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head. The head IC switches the heads by the serial port (SDEN, SCLK, SDATA).

The IC generates a write error sense signal (WUS) when a write error occurs due to head shortcircuit or head disconnection.


Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC with synchronizing with the write clock. The NRZ write data is converted from 48-bits data to 51-bits data by the encoder circuit then sent to the

PreAMP, and the data is written onto the media.

(1) 48/51 GCR

The disk drive converts data using the 48/51 group coded recording (GCR) algorithm.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non-linearity generated at reading.

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Read circuit

The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 48/51 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) VGA circuit

The VGA circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The VGA output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the parallel data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

(3) Adaptive equalizer circuit

This circuit is 10-tap adaptive digital FIR filter circuit that cosine-equalizes the head read signal to the Extended Partial Response Class 4 (EPR4) waveform.

(4) Viterbi detection circuit

The digital data output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) Data separator circuit

The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.

(6) 48/51 GCR decoder

This circuit converts the 48-bits read data into the 51-bits NRZ data.

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