5.2 Logical Interface. Fujitsu C141-E090-02EN

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5.2 Logical Interface. Fujitsu C141-E090-02EN | Manualzz

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinderhead-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the

Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of

LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE

DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.)

×

(Number of head) + (Head No.))

×

(Number of sector/track)]

+ (Sector No.) – 1

5.2.1

I/O registers

Communication between the host system and the device is done through input-output (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the host system. Table 5.3 shows the coding address and the function of I/O registers.

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CS0– CS1– DA2

1

1

1

1

1

1

Command block registers

1 0 0 0

0

0

0

0

0

0

0

0

0

1

1

1

0

Control block registers

0

0

1

1 1

1

1

1

X

1

1

0

0

1

1

X

0

1

1

1

1

DA1

Table 5.3

I/O registers

DA0

I/O registers

Read operation Write operation

0

1

0

1

0

1

0

1

X

0

1

Data

Error Register

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

(Invalid)

Alternate Status

Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

(Invalid)

Device Control

Host I/O address

X'1F0'

X'1F1'

X'1F2'

X'1F3'

X'1F4'

X'1F5'

X'1F6'

X'1F7'

X'3F6'

X'3F7'

Notes:

1.

The Data register for read or write operation can be accessed by 16 bit data bus

(DATA0 to DATA15).

2.

The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.

When reading the Drive Address register, bit 7 is high-impedance state.

4.

The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and

Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E090-01EN 5 - 7

5.2.2

Command block registers

(1) Data register (X'1F0')

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode.

(2) Error register (X'1F1')

The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE

DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7

ICRC

X: Unused

Bit 6

UNC

Bit 5

X

Bit 4

IDNF

Bit 3

X

Bit 2

ABRT

Bit 1

TK0NF

Bit 0

AMNF

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Interface CRC error (ICRC). This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer. The content of this bit is not applicable for Multiword DMA transfers.

Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

Unused

ID Not Found (IDNF). This bit indicates an error except for, uncorrectable error and SB not found, and Aborted Command.

Unused

Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready, Write Fault) or the command code was invalid.

Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

Address Mark Not Found. This bit indicates that an SB not found error has been encountered.

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[Diagnostic code]

X'01': No Error Detected.

X'02': HDC Register Compare Error

X'03': Data Buffer Compare Error.

X'05': ROM Sum Check Error.

X'80': Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X'01' to X'05').

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X'1F1')

The Features register provides specific feature to a command. For instance, it is used with SET

FEATURES command to enable or disable caching.

(4) Sector Count register (X'1F2')

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is

X'00', the sector count is 256.

When this register indicates X'00' at the completion of the command execution, this indicates that the command is completed successfully. If the command is not completed successfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands; INITIALIZE

DEVICE PARAMETERS, FORMAT TRACK, SET FEATURES, IDLE, STANDBY and SET

MULTIPLE MODE.

(5) Sector Number register (X'1F3')

The contents of this register indicates the starting sector number for the subsequent command.

The sector number should be between X'01' and [the number of sectors per track defined by

INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E090-01EN 5 - 9

(6) Cylinder Low register (X'1F4')

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

(7) Cylinder High register (X'1F5')

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X'1F6')

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines "the number of heads minus 1".

Bit 7

X

Bit 6

L

Bit 5

X

Bit 4

DEV

Bit 3

HS3

Bit 2

HS2

Bit 1

HS1

Bit 0

HS0

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Unused

L. 0 for CHS mode and 1 for LBA mode.

Unused

DEV bit. 0 for the master device and 1 for the slave device.

HS3 CHS mode head address 3 (2

3

). LBA bit 27.

HS2 CHS mode head address 3 (2

2

). LBA bit 26.

HS1 CHS mode head address 3 (2

1

). LBA bit 25.

HS0 CHS mode head address 3 (2

0

). LBA bit 24.

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(9) Status register (X'1F7')

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

- Bit 7:

- Bit 6:

- Bit 5:

- Bit 4:

Busy (BSY) bit. This bit is set whenever the Command register is accessed.

Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested

(DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control register, the BSY bit is set. the BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the Command register.

(c) Within 5

µ s following transfer of 512 bytes data during execution of the

READ SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE

BUFFER command.

Within 5

µ s following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command.

Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected

(not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

C141-E090-01EN 5 - 11

- Bit 3:

- Bit 2:

- Bit 1:

- Bit 0:

Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

Always 0.

Always 0.

Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

(10) Command register (X'1F7')

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the

Command register is written.

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