CHAPTER 5 Interface. Fujitsu MHT2040AT, MHT2030AT, MHT2080AT, MHT2020AT, MHT2060AT

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CHAPTER 5 Interface. Fujitsu MHT2040AT, MHT2030AT, MHT2080AT, MHT2020AT, MHT2060AT | Manualzz

CHAPTER 5 Interface

5.1

5.2

5.3

5.4

5.5

5.6

Physical Interface

Logical Interface

Host Commands

Command Protocol

Ultra DMA Feature Set

Timing

This chapter gives details about the interface, and the interface commands and timings.

C141-E192-01EN 5-1

Interface

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

Host

DATA 0-15: DATA BUS

DMACK-: DMA ACKNOWLEDGE

DMARQ: DMA REQUEST

INTRO: INTERRUPT REQUEST

DIOW-: I/O WRITE

STOP: STOP DURING ULTRA DMA DATA BURSTS

DIOR-:I/O READ

HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS

HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST

PDIAG-: PASSED DIAGNOSTICS

CBLID-: CABLE TYPE IDENTIFIER

DASP-: DEVICE ACTIVE/SLAVE PRESENT

IORDY:I/O READY

DDMARDY:DMA READY DURING ULTRA DMA DATA OUT BURSTS

DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS

DA 0-2: DEVICE ADDRESS

CS0-: CHIP SELECT 0

CS1-: CHIP SELECT 1

RESET-: RESET

CSEL: CABLE SELECT

MSTR: Master

ENCSEL: ENABLE CSEL

+5V DC: +5 volt

GND: GROUND

IDD

Figure 5.1 Interface signals

5-2 C141-E192-01EN

5.1 Physical Interface

5.1.2 Signal assignment on the connector

Table 5.1 shows the signal assignment on the interface connector.

Table 5.1 Signal assignment on the interface connector

29

31

33

35

37

39

41

43

Pin No.

15

17

19

5

7

9

11

13

21

23

25

E

1

3

A

C

27

Signal

MSTR

PUS-

(KEY)

RESET–

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

GND

DMARQ

DIOW-, STOP

DIOR-, HDMRDY,

HSTROBE

IORDY, DDMARDY,

DSTROBE

DMACK–

INTRQ

DA1

DA0

CS0–

DASP–

+5 VDC

GND

Pin No.

22

24

26

16

18

20

6

8

10

12

14

F

2

B

D

4

Signal

MSTR/ENCSEL

ENCSEL

(KEY)

GND

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

(KEY)

GND

GND

GND

28

30

32

34

36

38

40

42

44

CSEL

GND reserved (IOCS16-)

PDIAG–, CBLID–

DA2

CS1–

GND

+5 VDC unused

C141-E192-01EN 5-3

Interface

[signal] [I/O] [Description]

ENCSEL I

MSTR-

STOP

I

I

Short: Sets master/slave using the CSEL signal is enabled.

MSTR, I, Master/slave setting

Pin A, B, C, D open: Master setting

Pin A, B Short: Slave setting

When pin C is grounded, the drive does not spin up at power on.

PUSI

RESETI Reset signal from the host. This signal is low active and is asserted for a minimum of 25

µ s during power on.

DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device. These signals are used for data transfer

DIOWI Signal asserted by the host to write to the device register or data port.

DIOW- must be negated by the host before starting the Ultra

DMA transfer. The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer. During data transfer in Ultra DMA mode, the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended.

DIOR-

This signal is used to set master/slave using the CSEL signal (pin 28).

Pins B and D Open: Sets master/slave using the CSEL signal is disabled.

HDMARDY-

HSTROBE

INTRQ

I

I

Read strobe signal from the host to read the device register or data port

Flow control signal for Ultra DMA data In transfer (READ DMA command). This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer. The host can negate the HDMARDY- signal to suspend the Ultra DMA data In transfer.

I Data Out Strobe signal from the host during Ultra DMA data Out transfer (WRITE DMA command). Both the rising and falling edges of the HSTROBE signal latch data from Data 15-0 into the device. The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfer.

O Interrupt signal to the host.

This signal is negated in the following cases:

− assertion of RESET- signal

Reset by SRST of the Device Control register

Write to the command register by the host

Read of the status register by the host

Completion of sector data transfer

(without reading the Status register)

The signal output line has a high impedance when no devices are selected or interruption is disabled.

5-4 C141-E192-01EN

5.1 Physical Interface

[signal]

CS0-

CS1-

DA 0-2

[I/O]

I

I

I

[Description]

Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers.

Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

Binary decoded address signals asserted by the host to access task file registers.

KEY

PDIAG-

CBLID-

DASP-

IORDY

Key pin for prevention of erroneous connector insertion

I/O This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration. This signal indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This signal is used to detect the type of cable installed in the system.

This signal is pulled up to +5 V through 10 k

resistor at each device.

I/O This is a time-multiplexed signal that indicates that the device is active and a slave device is present.

This signal is pulled up to +5 V through 10 k

Ω resistor at each device.

O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system.

DDMARDYO Flow control signal for Ultra DMA data Out transfer (WRITE

DMA command). This signal is asserted by the device to inform the host that the device is ready to receive the Ultra DMA data

Out transfer. The device can negate the DDMARDY- signal to suspend the Ultra DMA data Out transfer.

DSTROBE O Data In Strobe signal from the device during Ultra DMA data In transfer. Both the rising and falling edges of the DSTROBE signal latch data from Data 15-0 into the host. The device can suspend the inversion of the DSTROBE signal to suspend the

Ultra DMA data In transfer.

CSEL I

DMACKI

This signal to configure the device as a master or a slave device.

When CSEL signal is grounded, the IDD is a master device.

− When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 240 k

resistor at each device.

The host system asserts this signal as a response that the host system receive data or to indicate that data is valid.

C141-E192-01EN 5-5

Interface

[signal]

DMARQ

+5 VDC

GND

[I/O] [Description]

O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing).

I

-

The direction of data transfer is controlled by the DIOR and

DIOW signals. This signal hand shakes with the DMACK-signal.

In other words, the device negates the DMARQ signal after the host system asserts the DMACK signal. When there is other data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCS16-, CS0- and

CS1- signals are not asserted. The DMA data transfer is a 16-bit data transfer.

+5 VDC power supplying to the device.

Grounded signal at each signal wire.

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host and the device.

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The

IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the

Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder

Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the

INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.)

×

(Number of head) + (Head No.))

×

(Number of sector/track)] + (Sector No.)

1

5-6 C141-E192-01EN

5.2 Logical Interface

5.2.1 I/O registers

Communication between the host system and the device is done through inputoutput (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to

DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

CS0– CS1– DA2 DA1

Table 5.2 I/O registers

DA0

I/O registers

Read operation Write operation

Host I/O address

Command block registers

L H L

L

L

L

L

H

H

H

H

L

L

L

H

L

L

L

L

H

L

H

H

Control block registers

H L H

H L H

H

X

H

H

H

H

L

H

L

L

H

H

X

L

H

L

L

L

H

Data

Device/Head

H Status

X (Invalid)

Alternate Status

Data

H Error Register Features

L Sector Count Sector Count

H Sector Number Sector Number

L Cylinder Low Cylinder Low

H Cylinder High Cylinder High

Device/Head

Command

(Invalid)

Device Control

X’3F6’

X’3F7’

X’1F0’

X’1F1’

X’1F2’

X’1F3’

X’1F4’

X’1F5’

X’1F6’

X’1F7’

Notes:

1.

The Data register for read or write operation can be accessed by 16 bit data bus (DATA0 to DATA15).

2.

The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus (DATA0 to DATA7).

3.

When reading the Drive Address register, bit 7 is high-impedance state.

4.

H indicates signal level High and L indicates signal level Low.

There are two methods for specifying the LBA mode. One method is to specify the LBA mode with 28-bit address information, and the other is to specify it with 48-bit address information (command of EXT system). If the LBA mode is specified with 28-bit address information, the

C141-E192-01EN 5-7

Interface

Device/Head, Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively.

If the LBA mode is specified with 48-bit address information, the Cylinder

High, Cylinder Low, Sector Number registers are set twice. In the first time, the registers indicate LBA bits 47 to 40, bits 39 to 32, and bits 31 to

24, respectively. In the second time, the registers indicate LBA bits 23 to

16, bits 15 to 8, and bits 7 to 0, respectively.

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode.

(2) Error register (X’1F1’)

The Error register indicates the status of the command executed by the device.

The contents of this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset , or the

EXECUTIVE DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7

ICRC

Bit 6

UNC

Bit 5

X

Bit 4

IDNF

Bit 3

X

Bit 2 Bit 1 Bit 0

ABRT TK0NF AMNF

X: Unused

- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error occurred during Ultra DMA transfer.

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad sector, uncorrectable error and SB not found.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready,

Write Fault) or the command code was invalid.

5-8 C141-E192-01EN

5.2 Logical Interface

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not

Found error occurred.

[Diagnostic code]

X’01’: No Error Detected.

X’02’: HDC Diagnostic Error

X’03’: Data Buffer Diagnostic Error.

X’04’: Memory Diagnostic Error.

X’05’: Reading the system area is abnormal.

X’06’: Calibration is abnormal.

X’80’: Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X’01’ to

X’06’).

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X’1F1’)

The Features register provides specific feature to a command. For instance, it is used with SET FEATURES command to enable or disable caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this register is X’00’, the sector count is 256. With the EXT system command, the sector count is 65536 when value of this register is X'00' in the first setting and X'00' in the second setting.

When this register indicates X’00’ at the completion of the command execution, this indicates that the command is completed successfully. If the command is not completed successfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the error.

The contents of this register has other definition for the following commands;

INITIALIZE DEVICE PARAMETERS, SET FEATURES, IDLE, STANDBY and SET MULTIPLE MODE.

C141-E192-01EN 5-9

Interface

(5) Sector Number register (X’1F3’)

The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

Under the LBA mode of the EXT system command, LBA bits 31 to 24 are set in the first setting, and LBA bits 7 to 0 are set in the second setting.

(6) Cylinder Low register (X’1F4’)

The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

Under the LBA mode of the EXT system command, LBA bits 39 to 32 are set in the first setting, and LBA bits 15 to 8 are set in the second setting.

(7) Cylinder High register (X’1F5’)

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the

Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

Under the LBA mode of the EXT system command, LBA bits 47 to 40 are set in the first setting, and LBA bits 23 to 16 are set in the second setting.

5-10 C141-E192-01EN

5.2 Logical Interface

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.).

Bit 7

X

Bit 6

L

Bit 5

X

Bit 4

DEV

Bit 3

HS3

Bit 2

HS2

Bit 1

HS1

Bit 0

HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3: HS3 CHS mode head address 3 (2

3

). bit 27 for LBA mode. Unused under the LBA mode of the EXT command.

- Bit 2: HS2 CHS mode head address 2 (2

2

). bit 26 for LBA mode. Unused under the LBA mode of the EXT command.

- Bit 1: HS1 CHS mode head address 1 (2

1

). bit 25 for LBA mode. Unused under the LBA mode of the EXT command.

- Bit 0: HS0 CHS mode head address 0 (2

0

). bit 24 for LBA mode. Unused under the LBA mode of the EXT command.

(9) Status register (X’1F7’)

The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the

BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt

Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

C141-E192-01EN 5-11

Interface

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed.

However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. the BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

(c) Within 5

µ s following transfer of 512 bytes data during execution of the READ SECTOR(S), WRITE SECTOR(S), or WRITE

BUFFER command.

Within 5

µ s following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ

LONG or WRITE LONG command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected (not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault

(write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

- Bit 2: Always 0.

5-12 C141-E192-01EN

5.2 Logical Interface

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written.

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7 Bit 6

BSY DRDY

Bit 5

DF

Bit 4

DSC

Bit 3

DRQ

Bit 2

0

Bit 1

0

Bit 0

ERR

C141-E192-01EN 5-13

Interface

(2) Device Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

Bit 7

HOB

Bit 6

X

Bit 5

X

Bit 4

X

Bit 3

X

Bit 2

SRST

Bit 1 nIEN

Bit 0

0

- Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command.

If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector count are displayed in the task register.

If HOB = 0, LBA bits 23 to 0 and the lower-order 8 bits of the sector count are displayed in the task register.

- Bit 2: Software Reset (SRST) is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption

(INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the highimpedance state.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the

Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.

5-14 C141-E192-01EN

Table 5.3 Command code and parameters (1 of 3)

5.3 Host Commands

Command code (Bit) Parameters used

Command name

7 6 5 4 3 2 1 0 FR SC SN CY DH

READ SECTOR(S)

READ MULTIPLE

READ DMA

READ VERIFY SECTOR(S)

WRITE MULTIPLE

WRITE DMA

WRITE VERIFY

0 0 1 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 0 N Y Y Y Y

1 1 0 0 1 0 0 R N Y Y Y Y

0 1 0 0 0 0 0 R N Y Y Y Y

1 1 0 0 0 1 0 1 N Y Y Y Y

1 1 0 0 1 0 1 R N Y Y Y Y

0 0 1 1 1 1 0 0 N Y Y Y Y

WRITE SECTOR(S)

RECALIBRATE

SEEK

0 0 1 1 0 0 0 R N Y Y Y Y

0 0 0 1 X X X X N N N N D

0 1 1 1 X X X X N N Y Y Y

INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y

IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D

IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D

SET FEATURES

SET MULTIPLE MODE

SET MAX

READ NATIVE MAX ADDRESS

1 1 1 0 1 1 1 1 Y N* N N D

1 1 0 0 0 1 1 0 N Y N N D

1 1 1 1 1 0 0 1 N Y Y Y Y

1 1 1 1 1 0 0 0 N N N N D

EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D*

READ LONG 0 0 1 0 0 0 1 R N Y Y Y Y

WRITE LONG 0 0 1 1 0 0 1 R N Y Y Y Y

READ BUFFER

WRITE BUFFER

IDLE

1

1

1

1

1

1

0

1

1

1

0

1

0

0

1

0

0

1

0

0

1

0

1

0

0

0

1

1

0

0

1

1

N

N

N

N

N

Y

N

N

N

N

N

N

D

D

D

C141-E192-01EN 5-15

Interface

Table 5.3 Command code and parameters (2 of 3)

Command code (Bit) Parameters used

Command name

7 6 5 4 3 2 1 0 FR SC SN CY DH

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

SLEEP

1

1

1

1

1

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

0

1

0

0

1

1

0

0

0

1

0

0

0

0

1

1

1

0

N

N

N

N

N

Y

N

N

N

N

N

N

N

N

N

N

D

D

D

D

CHECK POWER MODE

SMART

1

1

1

0

1

0

0

1

1

1

0

1

1

0

0

0

1

0

0

0

0

0

1

0

N

Y

N

Y

N

Y

N

Y

D

D

SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

0

0

1

0

1

N

N

N

N

N

N

N

N

N

N

N

N

D

D

D

SECURITY SET PASSWORD

SECURITY UNLOCK

FLUSH CACHE

DEVICE CONFIGURATION

1 1 1 1 0 0 0 1 N N N N D

1 1 1 1 0 0 1 0 N N N N D

1 1 1 0 0 1 1 1 N N N N D

1 0 1 1 0 0 0 1 N N N N D

SET MAX ADDRESS

SET MAX SET PASSWORD

SET MAX LOCK

SET MAX UNLOCK

SET MAX FREEZE LOCK

READ NATIVE MAX ADDRESS

IDENTIFY COMPONENT

DEVICE CONFIGURATION

RESTORE

DEVICE CONFIGURATION

FREEZE LOCK

1 1 1 1 1 0 0 1 N Y Y Y Y

1 1 1 1 1 0 0 1 Y N N N Y

1 1 1 1 1 0 0 1 Y N N N Y

1 1 1 1 1 0 0 1 Y N N N Y

1 1 1 1 1 0 0 1 Y N N N Y

1 1 1 1 1 0 0 0 N N N N D

1 1 0 1 0 0 0 0 N N N Y D

1 0 1 1 0 0 0 1 Y N N N D

1 0 1 1 0 0 0 1 Y N N N D

5-16 C141-E192-01EN

5.3 Host Commands

Table 5.3 Command code and parameters (3 of 3)

Command name

Command code (Bit) Parameters used

7 6 5 4 3 2 1 0 FR SC SN CY DH

1 0 1 1 0 0 0 1 Y N N N D DEVICE CONFIGURATION

IDENTIFY

DEVICE CONFIGURATION SET

READ NATIVE MAX ADDRESS

EXT *O

SET MAX ADDRESS EXT *O

FLUSH CACHE EXT

WRITE DMA EXT

READ DMA EXT

WRITE MULTIPLE EXT

READ MULTIPLE EXT

WRITE SECTOR (S) EXT

READ SECTOR (S) EXT

DOWNLOAD MICRO CODE

*O

*O

*O

*O

*O

*O

*O

1 0 1 1 0 0 0 1 Y N N N D

1 1 1 1 1 0 0 0 N N N N D

1 1 1 1 1 0 0 1 N Y Y Y Y

1 1 1 0 0 1 1 1 N N N N D

0 0 1 1 0 1 0 1 N Y Y Y D

0 0 1 0 0 1 0 1 N Y Y Y D

0 0 1 1 1 0 0 1 N Y Y Y D

0 0 1 0 1 0 0 1 N Y Y Y D

0 0 1 1 0 1 0 0 N Y Y Y D

0 0 1 0 0 1 0 0 N Y Y Y D

1 0 0 1 0 0 1 0 Y Y Y N D

Notes:

FR: Features Register

CY: Cylinder Registers

SC: Sector Count Register

DH: Drive/Head Register

SN: Sector Number Register

R: Retry at error

1 = Without retry

0 = With retry

Y: Necessary to set parameters

Y*: Necessary to set parameters under the LBA mode.

N: Not necessary to set parameters (The parameter is ignored if it is set.)

N*: May set parameters

C141-E192-01EN 5-17

Interface

D: The device parameter is valid, and the head parameter is ignored.

*O: Option (customizing)

D*: The command is addressed to the master device, but both the master device and the slave device execute it.

X: Do not care

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.

Example: READ SECTOR(S)

At command issuance (I/O registers setting contents)

Bit 7 6 5 4 3 2 1 0

1F7

H

(CM) 0 0 1 0 0 0 0 0

1F6

H

(DH) x L x DV Head No. / LBA [MSB]

1F5

H

(CH) Start cylinder address [MSB] / LBA

1F4

H

(CL) Start cylinder address [LSB] / LBA

1F3

H

(SN) Start sector No. / LBA [LSB]

1F2

H

(SC) Transfer sector count

1F1

H

(FR) xx

At command completion (I/O registers contents to be read)

Bit 7 6 5 4 3 2 1 0

1F7

H

(ST) Status information

1F6

H

(DH) x L x DV Head No. / LBA [MSB]

1F5

H

(CH) End cylinder address [MSB] / LBA

1F4

H

(CL) End cylinder address [LSB] / LBA

1F3

H

(SN) End sector No. / LBA [LSB]

1F2

H

(SC) X’00’

1F1

H

(ER) Error information

5-18 C141-E192-01EN

5.3 Host Commands

CM: Command register FR: Features register

DH: Device/Head register ST: Status register

CH: Cylinder High register ER: Error register

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sector Number register DV: Device address. bit

SC: Sector Count register x, xx: Do not care (no necessary to set)

Note:

1.

When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit).

2.

At error occurrence, the SC register indicates the remaining sector count of data transfer.

3.

In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and

Sector Number registers. Number of sectors can be specified from 1 to 256 sectors. To specify 256 sectors reading, ‘00’ is specified. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs an implied seek. After the head reaches to the specified track, the device reads the target sector.

If an error occurs, retry reads are attempted to read the target sector before reporting an error, irrespective of the R bit setting.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

If an unrecoverable error occurs in a sector, the read operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

C141-E192-01EN 5-19

Interface

1F7

H

(CM)

1F6

H

(DH)

1F5

H

1F4

H

1F3

H

1F2

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

(CL)

(SN)

(SC)

(FR)

0 x

0

L

1 0 0 0 0 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

R

(R: Retry)

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X’C4’)

The READ MULTIPLE Command performs the same as the READ SECTOR(S)

Command except that when the device is ready to transfer data for a block of sectors, and enters the interrupt pending state only before the data transfer for the first sector of the block sectors. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.

The number of sectors per block is defined by a successful SET MULTIPLE

MODE Command. The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command.

If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a

5-20 C141-E192-01EN

5.3 Host Commands

final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”).

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.

Figure 5.2 shows an example of the execution of the READ MULTIPLE command.

Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block)

READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

Figure 5.2 Execution example of READ MULTIPLE command

1F7

H

(CM)

1F6

H

(DH)

1F5

H

1F4

H

1F3

H

1F2

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

(CL)

(SN)

(SC)

(FR)

1 x

1

L

0 0 0 1 0 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

0

C141-E192-01EN 5-21

Interface

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00

(*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.

(3) READ DMA (X’C8’ or X’C9’)

This command operates similarly to the READ SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES command.

Multiword DMA transfer mode 0 to 2

Ultra DMA transfer mode 0 to 5

5-22 C141-E192-01EN

5.3 Host Commands

1F7

H

(CM)

1F6

H

(DH)

1F5

H

1F4

H

1F3

H

1F2

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

(CL)

(SN)

(SC)

(FR)

1 x

1

L

0 0 1 0 0 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

R

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH) x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X’40’ or X’41’)

This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.

If an unrecoverable error occurs, the verify operation is terminated at the sector where the error occurred. The command block registers contain the cylinder, the head, and the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred. The Sector Count register indicates the number of sectors that have not been verified.

C141-E192-01EN 5-23

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0 1 0 0 0 0 0 R x L x DV Start head No. / LBA [MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the

Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified from 1 to 256 sectors. A sector count of 0 requests 256 sectors. Data transfer begins at the sector specified in the Sector Number register. For the DRQ,

INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs an implied seek. After the head reaches to the specified track, the device writes the target sector.

If an error occurs when writing to the target sector, retries are attempted irrespectively of the R bit setting.

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

5-24 C141-E192-01EN

5.3 Host Commands

If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

0 x

0

L

1 x

1

DV

0 0

Start head No. / LBA

[MSB]

0

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

R

1F7

H

At command completion (I/O registers contents to be read)

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

C141-E192-01EN 5-25

Interface

(6) WRITE MULTIPLE (X’C5’)

This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command. The DRQ bit of the Status register is required to set only at the start of the data block, not on each sector.

The number of sectors per block is defined by a successful SET MULTIPLE

MODE command. The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command.

If the number of requested sectors is not divided evenly (having the same number of sectors [block count]), as many full blocks as possible are transferred, then a final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”).

If the WRITE MULTIPLE command is issued before the SET MULTIPLE

MODE command is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE MULTIPLE command with an ABORTED

COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred.

Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block. If an error occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block.

The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual request.

5-26 C141-E192-01EN

5.3 Host Commands

1F7

H

(CM)

1F6

H

(DH)

1F5

H

1F4

H

1F3

H

1F2

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

(CL)

(SN)

(SC)

(FR)

1 x

1

L

0 0 0 1 0 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00

Error information

(7) WRITE DMA (X’CA’ or X’CB’)

This command operates similarly to the WRITE SECTOR(S) command except for following events.

The data transfer starts at the timing of DMARQ signal assertion.

The device controls the assertion or negation timing of the DMARQ signal.

The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device.

The device posts a status as the result of command execution only once at completion of the data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the WRITE SECTOR(S) command.

C141-E192-01EN 5-27

Interface

A host system can select the following transfer mode using the SET FEATURES command.

Multiword DMA transfer mode 0 to 2

Ultra DMA transfer mode 0 to 5

1F7

H

(CM)

1F6

H

(DH)

1F5

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

(FR)

1 x

1

L

0 0 1 0 1 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

R

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X’3C’)

This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted.

After all sectors are verified, the last interruption (INTRQ for command termination) is generated.

5-28 C141-E192-01EN

5.3 Host Commands

1F7

H

(CM)

1F6

H

(DH)

1F5

1F1

H

H

At command issuance (I/O registers setting contents)

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

(FR)

0 x

0

L

1 1 1 1 0 x DV Start head No. / LBA

[MSB]

Start cylinder No. [MSB] / LBA

Start cylinder No. [LSB] / LBA

Start sector No. / LBA [LSB]

Transfer sector count xx

0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x DV End head No. / LBA [MSB]

End cylinder No. [MSB] / LBA

End cylinder No. [LSB] / LBA

End sector No. / LBA [LSB]

00 (*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X’10’ to X’1F’)

This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the

BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

C141-E192-01EN 5-29

Interface

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0 x xx xx xx xx xx

0 x

0 x

1

DV x xx x x x

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

Note:

Also executable in LBA mode.

(10) SEEK (X’70’ to X’7F’)

This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt.

In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.

5-30 C141-E192-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0 1 1 1 x x x x x L x DV Head No. / LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB] xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x xx

Error information

DV

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB]

Head No. / LBA [MSB]

(11) INITIALIZE DEVICE PARAMETERS (X’91’)

The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of

Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt.

When the SC register is specified to X’00’, an ABORTED COMMAND error is posted. Other than X’00’ is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting.

The device ignores the L bit specification and operates with only CHS mode specification.

C141-E192-01EN 5-31

Interface

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x xx

0 x

0 x

1

DV xx xx

Number of sectors/track xx

0 0

Max. head No.

0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x DV

Number of sectors/track

Error information

Max. head No.

(12) IDENTIFY DEVICE (X’EC’)

The host system issues the IDENTIFY DEVICE command to read parameter information from the device. Upon receipt of this command, the drive sets the

BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and generates an interrupt. After that, the host system reads the information out of the sector buffer. Table 5.4 shows the values of the parameter words and the meaning in the buffer.

At command issuance (I/O registers setting contents)

1 1 1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1 x

1 x

1 0 1 x DV xx

0

5-32 C141-E192-01EN

5.3 Host Commands

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

(13) IDENTIFY DEVICE DMA (X’EE’)

When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x xx xx xx xx xx

1 x

1 x

0

DV

1 xx

1 1 0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

C141-E192-01EN 5-33

Interface

23-26

27-46

47

48

49

50

51

52

53

54

55

56

57-58

59

Word

0

1

2

3

4-5

6

7-9

10-19

20

21

22

60-61

62

63

64

65

Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 2)

Value

X’045A’

X’3FFF’

X’xxxx’

X’10’

X’0000’

X’3F’

X’0000’

Set by a device

X’0003’

X’xxxx’

X’0004’

Set by a device

X’8010’

X’0000’

X’2B00’

X’400x’

X’0200’

X’0200’

X’0007’

(Variable)

(Variable)

(Variable)

(Variable)

*8

*2

X’0000’

X’xx07’

X’0003’

X’0078’

General Configuration *1

Description

Number of Logical cylinders *2

Detailed Configuration *3

Number of Logical Heads *2

Undefined

Number of Logical sectors per Logical track *2

Undefined

Serial number (ASCII code, 20 characters, right)

Undefined

Buffer Size (1 LSB: 512 Byte) ex. Buffer Size=2MByte: X’1000’

Number of ECC bytes transferred at READ LONG or WRITE

LONG command

Firmware revision (ASCII code, 8 characters, left)

Model name (ASCII code, 40 characters, left)

Maximum number of sectors per interrupt on READ/WRITE

MULTIPLE command

Reserved

Capabilities *4

Capabilities *5

PIO data transfer mode *6

Reserved

Enable/disable setting of words 54-58 and 64-70, 88 *7

Number of current Cylinders

Number of current Head

Number of current sectors per track

Total number of current sectors

Transfer sector count currently set by READ/WRITE

MULTIPLE command *8

Total number of user addressable sectors (LBA mode only) *2

Reserved

Multiword DMA transfer mode *9

Advance PIO transfer mode support status *10

Minimum multiword DMA transfer cycle time per word :

120 [ns]

5-34 C141-E192-01EN

5.3 Host Commands

Word

66

67

68

83

84

85

86

87

88

69-79

80

81

82

89

90

91

92

93

94

95-99

Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 2)

100-103

104-127

128

129-159

160-254

255

Value

X’0078’

X’00F0’

X’0078’

X’0000’

X’007C’

X’0019’

X’346B’

X’7x28’

X’40xx’

*15

*16

*17

X’xx3F’

Set by a device

X’0000’

(Variable)

(Variable)

*20

(Variable)

X’0000’

X’xx’

X’00’

X’0xxx’

X’xxxx’

X’0000’

X’xxA5’

Description

Manufacturer’s recommended DMA transfer cycle time : 120

[ns]

Minimum PIO transfer cycle time without IORDY flow control

: 240 [ns]

Minimum PIO transfer cycle time with IORDY flow control :

120 [ns]

Reserved

Major version number *11

Minor version number

Support of command sets *12

Support of command sets *13

Support of command sets/function *14

Valid of command sets/function *15

Valid of command sets/function *16

Default of command sets/function *17

Ultra DMA transfer mode *18

Security Erase Unit execution time (1 LSB: 2 min.) *19

Enhanced Security Erase Unit execution time

(1 LSB: 2 min.)

Advance power management level

Master password revision

Hardware configuration *20

Acoustic Management level *21

Reserved

Total number of sectors accessible by users in the 48-bit LBA mode *22

Reserved

Security status *23

Undefined

Reserved

Check sum (The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255, in byte units.)

*1 Word 0: General configuration

Bit 15: ATA device = 0, ATAPI device = 1

C141-E192-01EN 5-35

Interface

5-36

Bit 14-8: Undefined

Bit 7: Removable disk drive = 1

Bit 6: Fixed drive = 1

Bit 5-3: Undefined

Bit 2: IDENTIFY DEVICE Valid = 0

Bit 1-0: Reserved

*2 Word 1, 3, 6, 60-61

Word 01

Word 03

Word 06

Word 60-61

MHT2080AT MHT2060AT MHT2040AT MHT2030AT MHT2020AT

X’3FFF’

X’10’

X’3FFF’

X’10’

X’3FFF’

X’10’

X’3FFF’

X’10’

X’3FFF’

X’10’

X’3F’ X’3F’ X’3F’ X’3F’ X’3F’

X’950F8B0’ X’6FC7C80’ X’4A85300’ X’37E3E40’ X’2542980’

*3 Status of the Word 2 Identify information is shown as follows:

37C8h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete.

738Ch

8C73h

C837h

The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete.

The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete.

The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete.

Others Reserved

*4 Word 49: Capabilities

Bit 15-14: Reserved

Bit 13: Standby timer value. ATA spec is '1.'

Bit 12:

Bit 11:

Reserved

1 = Supported

Bit 10: 0 = Disable inhibition

Bit 7-0: Undefined

Bit 8: 1 = LBA Supported

Bit 9: 1 = DMA Supported

C141-E192-01EN

5.3 Host Commands

*5 Word 50: Device capability

Bit 15: 0

Bit 14: 1

Bit 13 to 1 Reserved

Bit 0 Standby timer value '1' = Standby timer value of the device is the smallest value.

*6 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X’02’=PIO mode 2

Bit 7-0: Undefined

*7 Word 53: Enable/disable setting of word 54-58 and 64-70

Bit 15-3: Reserved

Bit 2: 1 = Enable the word 88

Bit 1:

Bit 0:

1 = Enable the word 64-70

1 = Enable the word 54-58

*8 Word 59: Transfer sector count currently set by READ/WRITE

MULTIPLE command

Bit 15-9: Reserved

Bit 8: 1 = Enable the multiple sector transfer

Bit 7-0: Transfer sector count currently set by READ/WRITE

MULTIPLE command without interrupt supports 2, 4, 8 and 16 sectors.

*9 Word 63: Multiword DMA transfer mode

Bit 15-11: Reserved

Bit 10:

Bit 9:

'1' = multiword DMA mode 2 is selected.

'1' = multiword DMA mode 1 is selected.

Bit 8: '1' = multiword DMA mode 0 is selected.

Bit 7-3: Reserved

Bit 2:

Bit 1:

1 = Multiword DMA mode 2, 1, and 0 supported (Bit 1 = 0 = '1')

1 = Multiword DMA mode 1, and 0 supported (Bit 0 = '1')

Bit 0: 1 = Mode 0

*10 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved

C141-E192-01EN 5-37

Interface

Bit 7:

Bit 6:

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

Bit 15:

Bit 14:

Bit 13:

Bit 12:

Bit 11:

Bit 10:

Bit 9:

Bit 8:

Bit 7-0: Advance PIO transfer mode

Bit 1: 1 = Mode 4

Bit 0:

*11 WORD 80

1 = Mode 3

Bit 15-7: Reserved

Bit 6: 1 = ATA/ATAPI-6 supported

Bit 5:

Bit 4:

1 = ATA/ATAPI-5 supported

1 = ATA/ATAPI-4 supported

Bit 3:

Bit 2:

1 = ATA-3 supported

1 = ATA-2 supported

Bit 1-0: Undefined

*12 WORD 82

Undefined

'1' = Supports the NOP command.

'1' = Supports the READ BUFFER command.

'1' = Supports the WRITE BUFFER command.

Undefined

'1' = Supports the Host Protected Area feature set.

'1' = Supports the DEVICE RESET command.

'1' = Supports the SERVICE interrupt.

'1' = Supports the release interrupt.

'1' = Supports the read cache function.

'1' = Supports the write cache function.

'1' = Supports the PACKET command feature set.

'1' = Supports the power management feature set.

'1' = Supports the Removable Media feature set.

'1' = Supports the Security Mode feature set.

'1' = Supports the SMART feature set.

5-38 C141-E192-01EN

5.3 Host Commands

*13 WORD 83

Bits 15-14: Undefined

Bit 13:

Bit 12:

'1' = FLUSH CACHE EXT command supported.

'1' = FLUSH CACHE command supported.

Bit 11:

Bit 10:*

Bit 9:

Bit 8:

'1' = Device Configuration Overlay feature set supported.

'1' = 48 bit LBA feature set.

'1' = Automatic Acoustic Management feature set.

'1' = Supports the SET MAX Security extending command.

Bit 7:

Bit 6:

Reserved

'1' = When the power is turned on, spin is started by the SET

FEATURES sub-command.

'1' = Supports the Power-Up In Standby set.

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

'1' = Supports the Removable Media Status Notification feature set.

'1' = Supports the Advanced Power Management feature set.

'1' = Supports the CFA (Compact Flash Association) feature set.

'1' = Supports the READ/WRITE DMA QUEUED command.

'1' = Supports the DOWNLOAD MICROCODE command.

*: Option (customizing)

*14 WORD 84

Bit 15:

Bit 14:

= 0

= 1

Bit 13-2: Reserved

Bit 1: '1' = Supports the SMART SELF-TEST.

Bit 0:

*15 WORD 85

'1' = Supports the SMART Error Logging.

Bit 15:

Bit 14:

Bit 13:

Undefined.

'1' = Supports the NOP command.

'1' = Supports the READ BUFFER command.

Bit 12:

Bit 11:

'1' = Supports the WRITE BUFFER command.

Undefined.

C141-E192-01EN 5-39

Interface

Bit 10:

Bit 9:

Bit 8:

Bit 7:

Bit 6:

'1' = Supports the Host Protected Area function.

'1' = Supports the DEVICE RESET command.

'1' = Enables the SERVICE interrupt. From the SET FEATURES command

'1' = Enables the release interrupt. From the SET FEATURES command

'1' = Enables the read cache function. From the SET FEATURES command

Bit 5:

Bit 4:

Bit 3:

Bit 2:

'1' = Enables the write cache function.

'1' = Enables the P PACKET command set.

'1' = Supports the Power Management function.

'1' = Supports the Removable Media function.

Bit 1:

Bit 0:

'1' = From the SECURITY SET PASSWORD command

'1' = From the SMART ENABLE OPERATION command

*16 WORD 86

Bits 15: Reserved

Bit 13-10: Same definition as WORD 83.

Bit 9: '1' = Enables the Automatic Acoustic Management function.

From the SET FEATURES command

Bit 8: '1' = From the SET MAX SET PASSWORD command

Bits 7-6: Same definition as WORD 83.

Bit 5: '1' = Enables the Power-Up In Standby function.

Bit 4:

Bit 3:

'1' = Enables the Removable Media Status Notification function.

'1' = Enables the Advanced Power Management function.

Bits 2-0: Same definition as WORD 83.

*17 WORD 87

Bits 15: = '0'

Bits 14: = '1'

Bits 13-2: Reserved

Bit 1-0: Same definition as WORD 84.

5-40 C141-E192-01EN

5.3 Host Commands

*18 WORD 88

Bit 15-8: Currently used Ultra DMA transfer mode

Bit 13: '1' = Mode 5 is selected.

Bit 12: '1' = Mode 4 is selected.

Bit 11: '1' = Mode 3 is selected.

Bit 10: '1' = Mode 2 is selected.

Bit 9: '1' = Mode 1 is selected.

Bit 8: '1' = Mode 0 is selected.

Bit 7-0: Supportable Ultra DMA transfer mode

Bit 5: '1' = Supports the Mode 5

Bit 4: '1' = Supports the Mode 4

Bit 3: '1' = Supports the Mode 3

Bit 2: '1' = Supports the Mode 2

Bit 1: '1' = Supports the Mode 1

Bit 0: '1' = Supports the Mode 0

*19 WORD 89

MHT2080AT = X'30': 96 minutes

MHT2060AT = X'24': 72 minutes

MHT2040AT = X'18': 48 minutes

MHT2030AT = X'12': 36 minutes

MHT2020AT = X'0C': 24 minutes

*20 WORD 93

Bits 15: = 0

Bit 14: = '1'

Bit 13: '1' = CBLID- is a higher level than VIH (80-conductor cable).

'0' = CBLID- is a lower level than VIL (40-conductor cable).

Bits 12-8: In the case of Device 1 (slave drive), a valid value is set.

Bit 12: Reserved

Bit 11: '1' = Device asserts PDIAG-.

Bit 10, 9: Method for deciding the device No. of Device 1.

C141-E192-01EN 5-41

Interface

5-42

'00' = Reserved

'01' = Using a jumper.

'10' = Using the CSEL signal.

'11' = Other method.

Bit 8: = '1' (In the case of device 1)

Bits 7-0: In the case of Device 0 (master drive), a valid value is set.

Bit 7:

Bit 6:

Reserved

'1' = Device 1 is selected, Device 0 responds.

Bit 5:

Bit 4:

Bit 3:

'1' = Device 0, assertion of DASP- was detected.

'1' = Device 0, assertion of PDIAG- was detected.

'1' = Device 0, an error was not detected in the selfdiagnosis.

Bit 2, 1: Method for deciding the device No. of Device 0.

'00' = Reserved

'01' = Using a jumper.

'10' = Using the CSEL signal.

Bit 0:

'11' = Other method.

'1'= (In the case of device 0)

*21 WORD 94

Bit 15-8: X'FE' Recommended acoustic management value.

Bit 7-0: X'XX' Current set value.

FE-C0: Performance mode

BF-80: Acoustic mode

00: Acoustic management is unused it.

(It is same as "FE-CO")

*22 WORD 100-103

When "48 bit LBA" of the option (customize) is supported, same number of

LBA as WORD 60-61 is displayed.

*23 WORD 128

Bit 15-9: Reserved

Bit 8: Security level. 0: High, 1: Maximum

Bit 7-6: Reserved

C141-E192-01EN

5.3 Host Commands

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

Bit 0:

'1' = Enhanced security erase supported

'1' = Security counter expired

'1' = Security frozen

'1' = Security locked

'1' = Security enabled

'1' = Security supported

(14) SET FEATURES (X’EF’)

The host system issues the SET FEATURES command to set parameters in the

Features register for the purpose of changing the device features to be executed.

Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register. Then, the device clears the

BSY bit, and generates an interrupt.

If the value in the Features register is not supported or it is invalid, the device posts an ABORTED COMMAND error.

Table 5.5 lists the available values and operational modes that may be set in the

Features register.

C141-E192-01EN 5-43

Interface

Table 5.5 Features register values and settable modes

Features

Register

Drive operation mode

X’02’

X’03’

X’05’

X’42’

X’55’

X’66’

X’82’

X’85’

X’AA’

X’BB’

X’C2’

X’CC’

Enables the write cache function.

Set the data transfer mode. *1

Enables the advanced power management function. *2

Enables the Acoustic management function. *3

Disables read cache function.

Disables the reverting to power-on default settings after software reset. (*1)

Disables the write cache function.

Set the advanced power management mode to the default mode.

Enables the read cache function.

Specifies the transfer of 4-byte ECC for READ LONG and WRITE LONG commands.

(*1)

Disables the Acoustic management function.

Enables the reverting to power-on default settings after software reset. (*1)

*1 Although there is a response to the command, nothing is done.

At power-on or after hardware reset, the default mode is set as follows.

Write cashe function : Enabled

Transfer mode : PIO Mode-4, Multiworld DMA Mode-2

Advanced power

management function : Enabled (Mode-1)

Acoustic

management function : State keeping

Read cashe function : Enabled

5-44 C141-E192-01EN

5.3 Host Commands

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 1 x xx x xx xx xx or *1~3

[See Table 5.5]

1 0 1 x DV xx

1 1 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

*1) Data Transfer Mode

The host sets X’03’ to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected.

Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value.

The IDD supports following values in the Sector Count register value. If other value than below is specified, an ABORTED COMMAND error is posted.

PIO default transfer mode

PIO flow control transfer mode X

00000 000 (X’00’)

00001 000 (X’08’: Mode 0)

00001 001 (X’09’: Mode 1)

00001 010 (X’0A’: Mode 2)

00001 011 (X’0B’: Mode 3)

00001 100 (X’0C’: Mode 4)

C141-E192-01EN 5-45

Interface

Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0)

Ultra DMA transfer mode X

00100 001 (X’21’: Mode 1)

00100 010 (X’22’: Mode 2)

01000 000 (X’40’: Mode 0)

01000 001 (X’41’: Mode 1)

01000 010 (X’42’: Mode 2)

01000 011 (X’43’: Mode 3)

01000 100 (X’44’: Mode 4)

01000 101 (X’45’: Mode 5)

*2) Advanced Power Management (APM)

The host writes the Sector Count register with the desired power management level and executes this command with the Features register X’05’, and then

Advanced Power Management is enabled.

The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any commands for a specific time. The sequence in which the power management level shifts is from Active Idle to Low

Power Idle to Standby. The Mode-2 level requires the longest shifting time, depending on the APM level settings. The settings of the APM level revert to their default values when power-on or a hardware or software reset occurs for the drive

.

APM Level

Mode 0 Active Idle

Mode 1 Low Power Idle

Mode 2 Standby

Reserve (State Keep)

Sector Count Register

C0h-FEh

80h-BFh

01h-7Fh

00h, FFh

Active Idle: The spindle motor rotates, and the head is loaded on the media.

Low Power Idle: The spindle motor rotates, and the head is unloaded.

Standby: The spindle motor stops, and the head is unloaded.

5-46 C141-E192-01EN

5.3 Host Commands

*3) Automatic Acoustic Management (AAM)

The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h, and then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets.

AAM Level

Performance mode (Fast Seek)

Acoustic mode (Slow Seek)

Abort

Non Operate

Sector Count Register

C0h-FEh

80h-BFh

01h-7Fh

00h, FFh

High-speed seek to which gives priority to the performance operates as for

"Performance mode", and low-speed seek by which the seek sound is suppressed operates as for "Acoustic mode".

Setting the seek mode by this command is applied to the seek operation in all command processing.

(15) SET MULTIPLE MODE (X’C6’)

This command enables the device to perform the READ MULTIPLE and

WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.

The number of sectors per block is written into the Sector Count register. The

IDD supports 2, 4, 8, 16 and 32 (sectors) as the block counts.

Upon receipt of this command, the device sets the BSY bit of the Status register and checks the contents of the Sector Count register. If the contents of the Sector

Count register is valid and is a supported block count, the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands. Execution of these commands is then enabled. If the value of the Sector Count register is not a supported block count, an ABORTED COMMAND error is posted and the

READ MULTIPLE and WRITE MULTIPLE commands are disabled.

If the contents of the Sector Count register is 0, when the SET MULTIPLE

MODE command is issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.

When the SET MULTIPLE MODE command operation is completed, the device clears the BSY bit and generates an interrupt.

C141-E192-01EN 5-47

Interface

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x xx

1 x

0 x xx xx

Sector count/block xx

0

DV

0 xx

1 1 0

After power-on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode.

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x

Sector count/block

Error information

DV xx

(16) SET MAX (F9)

SET MAX Features Register Values

Value

00h

01h

02h

03h

04h

05h - FFh

Command

Obsolete

SET MAX SET PASSWORD

SET MAX LOCK

SET MAX UNLOCK

SET MAX FREEZE LOCK

Reserved

5-48 C141-E192-01EN

5.3 Host Commands

SET MAX ADDRESS

A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command.

This command allows the maximum address accessible by the user to be set in

LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.

Then, it clears BSY and generates an interrupt.

The new address information set by this command is reflected in Words 1, 54, 57,

58, 60 and 61 of IDENTIFY DEVICE information. If an attempt is made to perform a read or write operation for an address beyond the new address space, an

ID Not Found error will result.

When SC register bit 0, VV (Value Volatile), is 1, the value set by this command is held even after power on and the occurrence of a hard reset. When the VV bit is

0, the value set by this command becomes invalid when the power is turned on or a hard reset occurs, and the maximum address returns to the value most lately set when VV bit = 1. (The value by VV bit = 0 is held in case that this command with VV bit = 1 has not been issued or had set the default value, and hard reset occurs.)

After power on and the occurrence of a hard reset, the host can issue this command only once when VV bit = 1. If this command with VV bit = 1 is issued twice or more, any command following the first time will result in an Aborted

Command error.

When the SET MAX ADDRESS EXT command is executed, all SET MAX

ADRESS commands are aborted. The address value returns to the origin when the

SET MAX ADDRESS EXT command is executed using the address value returned by the READ NATIVE MAX ADDRESS command.

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1 x

1

L

1 x

1

DV

1 0 0

Max head/LBA [MSB]

1F5

H

(CH) Max. cylinder [MSB]/Max. LBA

1F4

H

(CL) Max. cylinder [LSB]/Max. LBA

1F3

H

(SN) Max. sector/Max. LBA [LSB]

1F2

H

(SC) xx

1F1

H

(FR) xx

1

VV

C141-E192-01EN 5-49

Interface

At command completion (I/O registers contents to be read)

1F7

H

(ST) Status information

1F6

H

(DH) x x x DV Max head/LBA [MSB]

1F5

H

(CH) Max. cylinder [MSB]/Max. LBA

1F4

H

(CL) Max. cylinder [LSB]/Max. LBA

1F3

H

(SN) Max. sector/Max. LBA [LSB]

1F2

H

(SC) xx

1F1

H

(ER) Error information

SET MAX SET PASSWORD (FR = 01h)

This command requests a transfer of 1 sector of data from the host, and defines the contents of SET MAX password. The password is retained by the device until the next power cycle.

The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed.

At command issuance (I/O registers setting contents)

0 0 1F7

H

(CM)

1F6

H

(DH)

1 x

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN) xx xx xx

1F2

H

(SC) xx

1F1

H

(FR) 01

1 x

1 1 1 x DV xx

1

5-50 C141-E192-01EN

5.3 Host Commands

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

Status information xx xx xx xx xx

1F1

H

(ER) Error information

Words

0

1 to 16

17 to 255

Password information

Reserved

Contents

Password (32 bytes)

Reserved

SET MAX LOCK (FR = 02h)

The SET MAX LOCK command sets the device into SET_MAX_LOCK state.

After this command is completed, any other SET MAX commands except SET

MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected. And the device returns command aborted.

The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command.

The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed.

C141-E192-01EN 5-51

Interface

1F7

H

At command issuance (I/O registers setting contents)

(CM) 1

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL) x xx xx

1F3

H

(SN) xx

1F2

H

(SC) xx

1F1

H

(FR) 02

1 x

1 x

1

DV

1 xx

0 0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

Status information xx xx xx xx xx

1F1

H

(ER) Error information

SET MAX UNLOCK (FR = 03h)

This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.

The password supplied in the sector of data transferred shall be compared with the stored password.

If the password compare fails, the device returns command aborted and decrements the Unlock counter, and remains in the Set Max Lock state. On the acceptance of the SET MAX LOCK command, the Unlock counter is set to a value of five. When this counter reaches zero, then SET MAX UNLOCK command returns command aborted until a power cycle.

If the password compare matches, then the device makes a transition to the Set

Max Unlocked state and all SET MAX commands will be accepted.

The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed.

5-52 C141-E192-01EN

5.3 Host Commands

1F7

H

At command issuance (I/O registers setting contents)

(CM) 1

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL) x xx xx

1F3

H

(SN) xx

1F2

H

(SC) xx

1F1

H

(FR) 03

1 x

1 x

1

DV

1 xx

0 0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

Status information xx xx xx xx xx

1F1

H

(ER) Error information

SET MAX FREEZE LOCK (FR=04h)

The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.

After the device made a transition to the Set Max Freeze Lock state, the following

SET MAX commands are rejected, then the device returns command aborted:

SET MAX ADDRESS

SET MAX SET PASSWORD

SET MAX LOCK

SET MAX UNLOCK

If the Device is in the SET_MAX_UNLOCK state with the SET MAX FREEZE

LOCK command, then the device returns command aborted.

The READ NATIVE MAX ADDRESS command is not executed just before this command. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed.

C141-E192-01EN 5-53

Interface

1F7

H

At command issuance (I/O registers setting contents)

(CM) 1

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL) x xx xx

1F3

H

(SN) xx

1F2

H

(SC) xx

1F1

H

(FR) 04

1 x

1 x

1

DV

1 xx

0 0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

Status information xx xx xx xx xx

1F1

H

(ER) Error information

(17) READ NATIVE MAX ADDRESS (F8)

This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.

At command issuance (I/O registers setting contents)

0 0 1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1 x

1

L

1 1 1 x DV xx

0

5-54 C141-E192-01EN

5.3 Host Commands

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x x x DV Max head/LBA [MSB]

Max. cylinder [MSB]/Max. LBA

Max. cylinder [LSB]/Max. LBA

Max. sector/Max. LBA [LSB] xx

Error information

(18) EXECUTE DEVICE DIAGNOSTIC (X’90’)

This command performs an internal diagnostic test (self-diagnosis) of the device.

This command usually sets the DRV bit of the Drive/Head register is to 0

(however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis.

If device 1 is present:

Both devices shall execute self-diagnosis.

The device 0 waits for up to 6 seconds until device 1 asserts the PDIAGsignal.

If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X’80’ to its own diagnostic status.

The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.)

A diagnostic status of the device 0 is read by the host system. When a diagnostic failure of the device 1 is detected, the host system can read a status of the device 1 by setting the DV bit (selecting the device 1).

When device 1 is not present:

The device 0 posts only the results of its own self-diagnosis.

The device 0 clears the BSY bit of the Status register, and generates an interrupt.

Table 5.6 lists the diagnostic code written in the Error register which is 8-bit code.

If the device 1 fails the self-diagnosis, the device 0 “ORs” X’80’ with its own status and sets that code to the Error register.

C141-E192-01EN 5-55

Interface

Code

X’01’

X’02’

X’03’

X’04’

X’05’

X’06’

X’8x’

Table 5.6 Diagnostic code

Result of diagnostic

No error detected.

HDC diagnostic error

Data buffer diagnostic error

Memory diagnostic error

Reading the system area is abnormal

Calibration abnormal

Failure of device 1 attention: The device responds to this command with the result of power-on diagnostic test.

1F7

H

1F6

H

At command issuance (I/O registers setting contents)

(CM)

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x xx xx xx xx xx

0 x

0 1 0 0 0 x DV Head No. /LBA

[

MSB]

0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx

01

H

01

H x x DV Head No. /LBA

[

MSB]

Diagnostic code

5-56 C141-E192-01EN

5.3 Host Commands

(19) READ LONG (X’22’ or X’23’)

This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE

LONG command. The READ LONG command supports only single sector operation.

Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command.

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

(R: Retry)

At command issuance (I/O registers setting contents)

0 x

0

L

1 0 0 0 1 R x DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB]

01 xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x

Error information

DV

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB] xx

Head No. /LBA [MSB]

C141-E192-01EN 5-57

Interface

(20) WRITE LONG (X’32’ or X’33’)

This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE

LONG command supports only single sector operation.

The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command.

This command is operated under the following conditions:

READ LONG issued

WRITE LONG (Same address) issues sequence

(After READ LONG is issued, WRITE LONG can be issued consecutively.)

If above condition is not satisfied, the WRITE LONG Data becomes the

Uncorrectable error for subsequence READ command.

At command issuance (I/O registers setting contents)

1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

0 x

R x DV Head No. /LBA [MSB]

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB]

01 xx

0

L

1 1 0 0 1

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x L x

Error information

DV

Cylinder No. [MSB] / LBA

Cylinder No. [LSB] / LBA

Sector No. / LBA [LSB] xx

Head No. /LBA [MSB]

5-58 C141-E192-01EN

5.3 Host Commands

(21) READ BUFFER (X’E4’)

The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.

At command issuance (I/O registers setting contents)

1 0 1F7

H

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx xx

1 x

1 x

1 1 0 x DV xx

0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

C141-E192-01EN 5-59

Interface

(22) WRITE BUFFER (X’E8’)

The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of

Status register and clears the BSY bit when the device is ready to receive the data.

After that, 512 bytes of data is transferred from the host and the device writes the data to the buffer, then generates an interrupt.

1F7

H

At command issuance (I/O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x xx xx xx xx xx

1 x

1 x

1

DV

1 xx

0 0 0

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

5-60 C141-E192-01EN

5.3 Host Commands

(23) IDLE (X’97’ or X’E3’)

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.

By using this command, the APS (Automatic Power Standby) timer function is enabled and the timer immediately starts the countdown. When the timer reaches the specified value, the device enters standby mode. The APS timer is set to prohibition if the Sector Count register's value was "00h" when device has received this command.

The APS timer allows the device to change to the standby mode automatically after specified period. When the device enters the idle mode, the timer starts countdown. If any command is not issued while the timer is counting down, the device automatically enters the standby mode. If any command is issued while the timer is counting down, the timer is initialized and the command is executed. The timer restarts countdown after completion of the command execution.

The period of timer count is set depending on the value of the Sector Count register as shown below.

Sector Count register value Point of timer

0

1 to 240

[X’00’]

[X’01’ to X’F0’]

241 to 251 [X’F1’ to X’FB’]

Timeout disabled

(Value

×

5) seconds

((Value-240)

×

30) min

21 minutes 252 [X’FC’]

253 [X’FD’] 8 hrs

254 to 255 [X’FE’ to X’FF’] 21 minutes 15 seconds

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’97’ or X’E3’

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) x xx xx xx

Period of timer xx x x DV xx

C141-E192-01EN 5-61

Interface

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

(24) IDLE IMMEDIATE (X’95’ or X’E1’)

Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the APS timer function.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’95’ or X’E1’

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) x xx xx xx xx xx x x DV xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

5-62 C141-E192-01EN

5.3 Host Commands

(25) STANDBY (X’96’ or X’E2’)

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. If the device has already spun down, the spin-down sequence is not implemented.

By using this command, the APS (Automatic Power Standby) timer function is enabled and the timer starts the countdown when the device returns to idle mode.

If the device has not received any command during specified period, then the device enters standby mode automatically.

Under the standby mode, the spindle motor is stopped. Thus, when the command involving a seek such as READ SECTOR(s) command is received, the device processes the command after driving the spindle motor.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’96’ or X’E2’

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) x xx xx xx

Period of timer xx x x DV xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

C141-E192-01EN 5-63

Interface

(26) STANDBY IMMEDIATE (X’94’ or X’E0’)

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the APS timer function.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’94’ or X’E0’

1F6

H

(DH) x x x DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

5-64 C141-E192-01EN

5.3 Host Commands

(27) SLEEP (X’99’ or X’E6’)

This command is the only way to make the device enter the sleep mode.

Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode.

In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All I/O register outputs are in high-impedance state.

The only way to release the device from sleep mode is to execute a software or hardware reset.

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’99’ or X’E6’

1F6

H

(DH) x x x DV xx xx 1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) xx xx xx xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

C141-E192-01EN 5-65

Interface

(28) CHECK POWER MODE (X’98’ or X’E5’)

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by the contents of the Sector Count register.

The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.

Power save mode

• During moving to standby mode

• Standby mode

• Idle mode

• Active mode

Sector Count register

X’00’

X’FF’

X’FF’

At command issuance (I/O registers setting contents)

1F7

H

(CM) X’98’ or X’E5’

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR) x xx xx xx xx xx x x DV xx

At command completion (I/O registers contents to be read)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x xx xx xx x x

X’00’ or X’FF’

Error information

DV xx

5-66 C141-E192-01EN

5.3 Host Commands

(29) SMART (X’B0)

This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued.

Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register). If the key values are incorrect, the Aborted Command error is issued.

If the failure prediction function is disabled, the device returns the Aborted

Command error to subcommands other than those of the SMART Enable

Operations (with the FR register set to D8h).

If the failure prediction function is enabled, the device collects and updates data on specific items. The values of items whose data is collected and updated by the device in order to predict device failures are hereinafter referred to as attribute values.

C141-E192-01EN 5-67

Interface

Table 5.7 Features Register values (subcommands) and functions (1 of 3)

Features Resister

X’D0’

X’D1’

X’D2’

X’D3’

X’D4’

Function

SMART Read Attribute Values:

A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.

* For information about the format of the attribute value information, see

Table 5.8.

SMART Read Attribute Thresholds:

This subcommand is used to transfer 512-byte insurance failure threshold value data to the host.

* For information about the format of the insurance failure threshold value data, see Table 5.9.

SMART Enable/Disable Attribute AutoSave:

Enables (by setting the SC register to a value other than 00h) or disables (by setting the SC register to 00h) a function that automatically saves device attribute values (“automatic attribute save function”). This setting is held regardless of whether the device is turned on or off. If the automatic attribute save function is enabled and more than 15 minutes has elapsed since the last time that attributes were saved, then the attributes are saved.

However, if the automatic attribute save function is disabled, the attributes are not saved. Upon receiving this subcommand, a device asserts BSY, enables or disables the automatic attribute save function, and clears BSY.

SMART Save Attribute Values:

When the device receives this subcommand, it asserts the BSY bit, saves device attribute value data, then clears the BSY bit.

SMART Executive Off-line Immediate:

A device which receives this command asserts the BSY bit, then starts collecting the off-line data specified in the SN register, or stops.

In the off-line mode, after BSY is cleared, off-line data are collected. In the captive mode, it collects off-line data with the BSY assertion as is, then clears the BSY when collection of data is completed.

SN Off-line data collection mode

00h: Off-line diagnosis (off-line mode)

01h: Simple self-test (off-line mode)

02h: Comprehensive self-test (off-line mode)

03h: Conveyance self-test (off-line mode)

04h: Selective self-test (off-line mode)

7Fh: Self-test stop

81h: Simple self-test (captive mode)

82h: Comprehensive self-test (captive mode)

83h: Conveyance self-test (captive mode)

84h: Selective self-test (captive mode)

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5.3 Host Commands

Table 5.7 Features Register values (subcommands) and functions (2 of 3)

Features Resister

X’D5’

Function

SMART Read Log Sector:

A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.

X’D6’

SN:

00h:

01h:

02h:

SC:

01h:

01h:

33h:

Log sector

SMART log directory

SMART summary error log

SMART comprehensive error log

06h:

09h:

01h:

01h:

SMART self-test log

SMART selective self-test log

80h-9Fh: 01h-10h: Host vendor log

* See Table 5.11 concerning the SMART error log data format.

See Table 5.12 concerning the SMART self-test log data format.

See Table 5.13 concerning the SMART selective self-test log data format.

SMART Write Log Sector:

A device which receives this sub-command asserts the BSY bit and when it has prepared to receive data from the host computer, it sets DRQ and clears the BSY bit. Next, it receives data from the host computer and writes the specified log sector in the SN register.

X’D8’

X’D9’

SN:

09h:

SC:

01h:

Log sector

SMART selective self-test log

80h-9Fh: 01h-10h Host vendor log

* The host can write any desired data in the host vendor log.

SMART Enable Operations:

This subcommand enables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, enables the failure prediction feature, then clears the BSY bit.

SMART Disable Operations:

This subcommand disables the failure prediction feature. The setting is maintained even when the device is turned off and then on.

When the device receives this subcommand, it asserts the BSY bit, disables the failure prediction feature, then clears the BSY bit.

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Interface

Table 5.7 Features Register values (subcommands) and functions (3 of 3)

Features Resister

X’DA’

X’DB’

Function

SMART Return Status:

When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers.

If there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded into the CL and CH registers. After the settings for the CL and CH registers have been determined, the device clears the BSY bit

SMART Enable/Disable Auto Off-line:

This sets automatic off-line data collection in the enabled (when the SC register specification

00h) or disabled (when the SC register specification

= 00) state. This setting is preserved whether the drive’s power is switched on or off.

If 24 hours have passed since the power was switched on, or since the last time that off-line data were collected, off-line data collection is performed without relation to any command from the host computer.

The host must regularly issue the SMART Read Attribute Values subcommand

(FR register = D0h), SMART Save Attribute Values subcommand (FR register =

D3h), or SMART Return Status subcommand (FR register = DAh) to save the device attribute value data on a medium.

Alternative, the device must issue the SMART Enable-Disable Attribute

AutoSave subcommand (FR register = D2h) to use a feature which regularly save the device attribute value data to a medium.

The host can predict failures in the device by periodically issuing the SMART Return

Status subcommand (FR register = DAh) to reference the CL and CH registers.

If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of its life . In this case, the host recommends that the user quickly backs up the data.

1F7

H

At command issuance (I-O registers setting contents)

(CM)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(FR)

1 x

0 x

Key (C2h)

Key (4Fh) xx xx

Subcommand

1 1 0 x DV xx

0 0 0

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5.3 Host Commands

At command completion (I-O registers setting contents)

1F7

H

(ST)

1F6

H

(DH)

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

Status information x x x DV xx

Key-failure prediction status (C2h/2Ch)

Key-failure prediction status (4Fh/F4h) xx xx

Error information

The attribute value information is 512-byte data; the format of this data is shown the following Table 5.8. The host can access this data using the SMART Read

Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown the following Table 5.9. The host can access this data using the SMART Read

Attribute Thresholds subcommand (FR register = D1h).

C141-E192-01EN 5-71

Interface

Table 5.8 Format of device attribute value data

Byte

00

01

02

03

04

05

Data format version number

Attribute 1 Attribute ID

Status flag

Item

Current attribute value

06

07 to 0C

0D

0E to 169 Attribute 2 to attribute 30

Attribute value for worst case so far

Raw attribute value

Reserved

(The format of each attribute value is the same as that of bytes 02 to 0D.)

16A

16B

Off-line data collection status

Self-test execution status

16C, 16D Off-line data collection execution time [sec.]

16E

16F

Reserved

Off-line data collection capability

170, 171 Trouble prediction capability flag

172 Error logging capability

173 (Self-test error detection point)

174

175

Simple self-test (Quick Test) execution time [min.]

Comprehensive self-test (Comprehensive Test) execution time [min.]

176 Conveyance self-test execution time [min.]

177 to 181 Reserved

182 to 1FE Vendor unique

1FF Check sum

Table 5.9 Format of insurance failure threshold value data

Byte

00

01

Data format version number

02

03

Threshold 1

04 to 0D

0E to 169 Threshold 2 to

Threshold 30

16A to 17B Reserved

17C to 1FE Vendor unique

1FF Check sum

Attribute ID

Item

Insurance failure threshold

Reserved

(The format of each threshold value is the same as that of bytes 02 to 0D.)

5-72 C141-E192-01EN

5.3 Host Commands

Data format version number

The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated.

Attribute ID

The attribute ID is defined as follows:

9

10

12

192

193

194

195

196

197

198

199

200

203

Attribute ID

0

1

2

3

4

5

7

8

Attribute name

(Indicates unused attribute data.)

Read Error Rate

Throughput Performance

Spin Up Time

Start/Stop Count

Reallocated Sector Count

Seek Error Rate

Seek Time Performance

Power-On Hours Count

Spin Retry Count

Drive Power Cycle Count

Emergency Retract Cycle Count

Load/Unload Cycle Count

HDA Temperature

ECC On the Flag Count

Reallocated Event Count

Current Pending Sector Count

Off-Line Scan Uncorrectable Sector Count

Ultra ATA CRC Error Count

Write Error Rate

Run Out

C141-E192-01EN 5-73

Interface

Status Flag

Bit

0

1

2

3

4

5

6 to 15

Meaning

If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value.

If this bit is 1 (0), it indicates the attribute only updated by an online test (off-line test).

If this bit 1, it indicates the attribute that represents performance.

If this bit 1, it indicates the attribute that represents an error rate.

If this bit 1, it indicates the attribute that represents the number of occurrences.

If this bit 1, it indicates the attribute that can be collected/saved even if the drive fault prediction function is disabled.

Reserve bit

Current attribute value

It indicates the normalized value of the original attribute value. The value deviates in a range of 01h to 64h (range of 01h to C8h for the ultra ATA CRC error rate). It indicates that the closer the value is to 01h, the higher the possibility of a failure. The host compares the attribute value with the threshold value. If the attribute value is larger than the threshold value, the drive is determined to be normal.

Attribute value for the worst case so far

This is the worst attribute value among the attribute values collected to date.

This value indicates the state nearest to a failure so far.

Raw attribute value

Raw attributes data is retained.

Off-line data collection status

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5.3 Host Commands

Status Byte

Reserved

Meaning

00h or 80h Off-line data acquisition is not executed.

02h or 82h Off-line data acquisition has ended without an error.

04h or 84h Off-line data acquisition is interrupted by a command from the host.

05h or 85h Off-line data acquisition has ended before completion because of a command from the host.

06h or 86h Off-line data acquisition has ended before completion because of an error that makes acquisition impossible. (Not used)

40 to 7Fh Vendor unique (Not used)

C0h to FFh

01h or 81h

03h or 83h

07h or 3Fh

87h to BFh

Bit

0 to 3:

4 to 7:

= 0h:

= 1h:

= 2h:

Self-test execution status

Meaning

Remainder of the self-test is indicated as a percentage in a range of "0h to 9h" (corresponding to 0 to 90 %).

Self-test execution status

Self-test has ended successfully, or self-test has not been executed.

Self-test is suspended by the host.

Self-test is interrupted by a soft/hard reset from the host.

= 3h: Self-test cannot be executed.

= 4h:

= 5h:

= 6h:

= 7h:

Self-test has ended with an abnormality because of unknown contents.

Self-test has ended with "Write/Read Test" error.

Self-test has ended with "Servo Check," error.

= 8h:

= 9h:

= Ah:

Self-test has ended with "SMART Drive Error Log Check,"

"Random Read Test," or "Read Scan Test" error.

Self-test has ended with "Pre-SMART Check," or "Post-SMART

Check" error.

Reserved

Reserved

= Bh: Reserved

= Ch to Eh: Reserved

= Fh: Self-test is in progress.

C141-E192-01EN 5-75

Interface

5-76

5

6

7

3

4

1

2

Off-line data collection capability

Indicates the method of off-line data collection carried out by the drive. If the off-line data collection capability is 0, it indicates that off-line data collection is not supported.

Bit

0

Meaning

If this bit is 1, it indicates that the SMART EXECUTE OFF-

LINE IMMEDATE sub-command (FR register = D4h) is supported.

Vendor unique

If this bit is 1, it indicates that acquisition of off-line data under execution is aborted when a new command is received.

If this bit is 1, it indicates that the SMART Off-line Read

Scanning Technology is supported.

If this bit is 1, it indicates that the SMART Self-test function is supported.

If this bit is 1, it indicates that the SMART Conveyance Selftest is supported.

If this bit is 1, it indicates that the SMART Selective Selftest is supported.

Reserved bits

Failure prediction capability flag

Bit

0

1

2 to 15

Meaning

If this bit is 1, it indicates that the attribute value is saved on media before the drive enters the power save mode.

If this bit is 1, it indicates that the attribute value is saved automatically after the pre-set operation of the drive.

Reserved bits

Error logging capability

Bit

0

1 to 7

Meaning

If this bit is 1, it indicates that the drive error logging function is supported.

Reserved bits

Check sum

Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.

C141-E192-01EN

5.3 Host Commands

Insurance failure threshold

The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure.

Byte

00

01

02

03

04

05-0B

0C

0D-11

12

13-FF

100

101

102

13F

140

1FF

Table 5.10 Log Directory Data Format

Item

SMART Logging Version

Number of sectors of Address "01h"

Reserved

Number of sectors of Address "02h"

Reserved

Number of sectors of Address "06h"

Reserved

Number of sectors of Address "09h"

Reserved

Address 80h

Number of sector

Reserved

Address 81h

"102" and "13F" are both the same format as "100-101"

Address 9Fh

Reserved

SMART error logging

If the device detects an unrecoverable error during execution of a command received from the host, the device registers the error information in the SMART

Summary Error Log (see Table 5.11) and the SMART Comprehensive Error Log

(see Table 5.11.1), and saves the information on media.

The host issues the SMART Read Log Sector sub-command (FR register = D5h,

SN register = 01h, SC register = 01h) and can read the SMART Summary Error

Log.

The host issues the SMART Read Log Sector sub-command (FR register = D5h,

SN register = 02h, SC register = 33h) and can read the SMART Comprehensive

Error Log.

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Interface

Table 5.11 Data format of SMART Summary Error Log

Byte

00

01

02 to 31

32

33

34

35

36

37

38

39

3A to 3D

Version of this function

Item

Pointer for the latest "Error Log Data Structure"

Error log data structure

Reserved

Command data structure

Device Control register value

Features register value

Sector Count register value

42

43

44

45

3E

3F

40

41

Error data structure

Sector Number register value

Cylinder Low register value

Cylinder High register value

Drive/Head register value

Command register value

Elapsed time after the power-on sequence (unit: ms)

Reserved

Error register value

Sector Count register value

Sector Number register value

Cylinder Low register value

Cylinder High register value

Drive/Head register value

Status register value

46 to 58

59

5A

5B

5C to 1C3 Error log data structure 2 to

Error log data structure 5

Vendor unique

State

Power-on time (unit: h)

Format of each error log data structure is same as those of bytes 02 to 5B.

1C4, 1C5 Number of unrecoverable errors that have occurred.

1C6 to 1FE Reserved

1FF Check sum

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5.3 Host Commands

Command data structure

Indicates the command received when an error occurs.

Error data structure

Indicates the status register when an error occurs.

Total number of drive errors

Indicates total number of errors registered in the error log.

Checksum

Two's complementary for the lowest-order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes beginning from the top of the structure.

Status

Bits 0 to 3: Indicates the drive status when received error commands according to the following table.

Bits 4 to 7: Vendor unique

Status

0

1

2

3

4

5 to F

Meaning

Unclear status

Sleep status

Standby status

Active status (BSY bit = 0)

Off-line data collection being executed

Reserved

Byte

00h

01h

02h...5Bh

5Ch...B5h

B6h...10Fh

110h...169h

16Ah...1C3h

1C4h...1C5h

1C6h...1FEh

1FFh

Table 5.11.1 Data format of SMART Comprehensive Error Log

First sector

SMART Error Logging 01h

Index Pointer Latest Error Data Structure.

1 st

Error Log Data Structure

2 nd

Error Log Data Structure

3 rd

Error Log Data Structure

4 th

Error Log Data Structure

5 th

Error Log Data Structure

Total Error Count

Reserved

Checksum

Next sector

Reserved

Reserved

Data Structure 5n + 1

Data Structure 5n + 2

Data Structure 5n + 3

Data Structure 5n + 4

Data Structure 5n + 5

Reserved

Reserved

Checksum

C141-E192-01EN 5-79

Interface

SMART Self-Test

The host computer can issue the SMART Execute Off-line Immediate subcommand (FR Register = D4h) and cause the device to execute a self-test. When the self-test is completed, the device saves the SMART self-test log to the disk medium.

The host computer can issue the SMART Read Log Sector sub-command (FR

Register = D5h, SN Register = 06h, SC register = 01h) and can read the SMART self-test log.

Table 5.12 SMART self-test log data format

Byte

00, 01

02

03

Item

Self-test log data structure

Self-test log 1 Self-test number (SN Register Value)

Self-test execution status

04, 05

06

07 to 0A

0B to 19

1A to 1F9 Self-test log 2 to 21

Life time. Total power-on time [hours]

Self-test error No.

Error LBA

Vendor unique

(Each log data format is the same as that in byte 02 to 19.)

1FA, 1FB Vendor unique

1FC Self-test index

1FD, 1FE Reserved

1FF Check sum

Self-test number

Indicates the type of self-test executed.

Self-test execution status

Same as byte 16Bh of the attribute value.

Self-test index

If this is "00h", it indicates the status where the self-test has never been executed.

Checksum

Two's complementary for the lowest-order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes from the top.

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5.3 Host Commands

Table 5.13 Selective self-test log data structure

Offset

00h, 01h

02h...09h

0Ah...11h

12h...19h

1Ah...21h

22h...29h

2Ah...31h

32h...39h

Description

Data Structure Revision Number

Test Span 1

Test Span 2

Test Span 3

Starting LBA

Ending LBA

Starting LBA

Ending LBA

Starting LBA

Ending LBA

Starting LBA

3Ah...41h

42h...49h

4Ah...51h

Test Span 4

Test Span 5

52h...151h

Reserved

152h...1EBh

Vender Unique

1Ech...1F3h

Current LBA under test

Ending LBA

Starting LBA

Ending LBA

1F4h...1F5h

Current Span under test

1F6h...1F7h

Feature Flags

1F8h Offline Execution Flag

1F9h

1FAh, 1FBh

Vender Unique Selective Offline Scan Number

Reserved

1FCh, 1FDh

Selective Self-test pending time [min]

1FEh, 1FFh

Checksum

Test Span

Selective self-test log provides for the definition of up to five test spans. If the starting and ending LBA values for a test span are both zero, a test span is not defined and not tested.

Current LBA under test

As the self-test progress, the device shall modify this value to contain the

LBA currently being tested.

Current Span under test

As the self-test progress, the device shall modify this value to contain the test span number currently being tested.

Feature Flags

Initial

01h, 00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h...00h

00h

00h

00h, 00h

00h, 00h

00h, FFh

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Interface

Bit

0

1

2

3

4

5...15

Table 5.14 Selective self-test feature flags

Vendor specific (unused)

Description

When set to one, perform off-line scan after selective test

Vendor specific (unused)

When set to one, off-line scan after selective test is pending.

When set to one, off-line scan after selective test is active.

Reserved

Bit [l] shall be written by the host and returned unmodified by the device. Bit

[3:4] shall be written as zeros by the host and the device shall modify them as the test progress.

Selective Self-test pending time [min]

The selective self-test pending time is the time in minutes from power-on to the resumption of the off-line testing if the pending bit is set.

(30) SECURITY DISABLE PASSWORD (F6h)

This command invalidates the user password already set and releases the lock function.

The host transfers the 512-byte data shown in Table 5.15 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET

PASSWORD command and reset the user password.

If the user password or master password transferred from the host does not match, the Aborted Command error is returned.

Issuing this command while in LOCKED MODE or FROZEN MODE returns the

Aborted Command error.

(The section about the SECURITY FREEZE LOCK command describes

LOCKED MODE and FROZEN MODE.)

5-82 C141-E192-01EN

C141-E192-01EN

5.3 Host Commands

Table 5.15 Contents of security password

Word

0

Contents

Control word

Bit 0: Identifier

0 = Compares the user passwords.

1 = Compares the master passwords.

1 to 16

Bits 1 to 15: Reserved

Password (32 bytes)

17 to 255 Reserved

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents))

1 1 1 1 0 1 x xx xx xx xx xx x x DV xx

1 0

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

At command completion (I-O register contents)

Status information x xx xx xx xx x x

Error information

DV xx

5-83

Interface

(31) SECURITY ERASE PREPARE (F3h)

The SECURITY ERASE UNIT command feature is enabled by issuing the

SECURITY ERASE PREPARE command and then the SECURITY ERASE

UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command.

Issuing this command during FROZEN MODE returns the Aborted Command error.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 x xx xx xx xx xx

1 x

1 x

1

DV

0 xx

0 1 1

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

(32) SECURITY ERASE UNIT (F4h)

This command erases all user data. This command also invalidates the user password and releases the lock function.

The host transfers the 512-byte data shown in Table 5.15 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set. The device erases user data, invalidates the user password, and releases the lock function if the passwords are the same.

5-84 C141-E192-01EN

5.3 Host Commands

Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET

PASSWORD command and reset the user password.

If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.

Issuing this command while in FROZEN MODE returns the Aborted Command error.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 x xx xx xx xx xx

1 x

1 x

1

DV

0 xx

1 0 0

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

(33) SECURITY FREEZE LOCK (F5h)

This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE.

SECURITY SET PASSWORD

SECURITY UNLOCK

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

C141-E192-01EN 5-85

Interface

5-86

SECURITY ERASE UNIT

FROZEN MODE is canceled when the power is turned off, or when hardware is reseted. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged.

Issuing this command during LOCKED MODE returns the Aborted Command error.

The following medium access commands return the Aborted Command error when the device is in LOCKED MODE:

READ DMA (EXT)

READ LONG

READ MULTIPLE (EXT)

READ SECTORS

READ VERIFY SECTORS

WRITE DMA (EXT)

WRITE LONG

WRITE MULTIPLE (EXT)

WRITE SECTORS (EXT)

WRITE VERIFY

SECURITY DISABLE PASSWORD

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SET MAX ADDRESS (EXT)

FLUSH CACHE (EXT)

DCO RESTORE

DCO SET

SET MAX ADDRESS (EXT)

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

At command issuance (I-O register contents)

1 x xx xx

1 x

1 x

1

DV

0 xx

1 0 1

C141-E192-01EN

5.3 Host Commands

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR) xx xx xx

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx xx xx x x xx

Error information

DV xx

(34) SECURITY SET PASSWORD (F1h)

This command enables a user password or master password to be set.

The host transfers the 512-byte data shown in Table 5.16 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.

(Table 5.17)

Issuing this command in LOCKED MODE or FROZEN MODE returns the

Aborted Command error.

Table 5.16 Contents of SECURITY SET PASSWORD data

Word

0

Contents

Control word

Bit 0 Identifier

0 = Sets a user password.

1 = Sets a master password.

Bits 1 to 7 Reserved

Bit 8 Security level

0 = High

1 = Maximum

Bits 9 to 15 Reserved

Password (32 bytes) 1 to 16

17 Master password version number

18 to 255 Reserved

C141-E192-01EN 5-87

Interface

Table 5.17 Relationship between combination of Identifier and Security level, and operation of the lock function

Identifier

User

Master

User

Master

Level

High

Description

The specified password is saved as a new user password.

The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password or the master password already set.

High The specified password is saved as a new master password.

The lock function is not enabled.

Maximum The specified password is saved as a new user password.

The lock function is enabled after the device is turned off and then on. LOCKED MODE can be canceled using the user password only. The master password already set cannot cancel LOCKED MODE.

Maximum The specified password is saved as a new master password.

The lock function is not enabled.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 1 1 1 0 0 x xx xx xx xx xx x x DV xx

0 1

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx xx xx xx x x

Error information

DV xx

5-88 C141-E192-01EN

5.3 Host Commands

(35) SECURITY UNLOCK

This command cancels LOCKED MODE.

The host transfers the 512-byte data shown in Table 5.15 to the device. Operation of the device varies as follows depending on whether the host specifies the master password.

When the master password is selected

When the security level is LOCKED MODE is high, the password is compared with the master password already set. If the passwords are the same, LOCKED MODE is canceled. Otherwise, the Aborted Command error is returned. If the security level in LOCKED MODE is set to the highest level, the Aborted Command error is always returned.

When the user password is selected

The password is compared with the user password already set. If the passwords are the same, LOCKED MODE is canceled. Otherwise, the

Aborted Command error is returned.

If the password comparison fails, the device decrements the UNLOCK counter.

The UNLOCK counter initially has a value of five. When the value of the

UNLOCK counter reaches zero, this command or the SECURITY ERASE UNIT command causes the Aborted Command error until the device is turned off and then on, or until a hardware reset is executed. Issuing this command with

LOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCK counter.

Issuing this command in FROZEN MODE returns the Aborted Command error.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 x xx xx xx xx xx

1 x

1 x

1

DV

0 xx

0 1 0

C141-E192-01EN 5-89

Interface

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

(36) FLUSH CACHE (E7)

This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred. The device performs every error recovery so that the data are read correctly.

When executing this command, the reading of the data may take several seconds if much data are to be read.

In case a non-recoverable error has occurred while the data is being read, the error generation address is put into the command block register before ending the command. This error sector is deleted from the write cache data, and the remaining cache data is written into the medium by the execution of the next

Flush Cache command.

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 1 1 0 0 1 x xx xx xx xx xx x x DV xx

1 1

5-90 C141-E192-01EN

5.3 Host Commands

At command completion (I-O register contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

(37) DEVICE CONFIGURATION (X'B1')

Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these

Features register values. If this command sets with the reserved value of Features register, an aborted error is posted.

FR values

C0h

C1h

C2h

C3h

00h-BFh, C4h-FFh

Command

DEVICE CONFIGURATION RESTORE

DEVICE CONFIGURATION FREEZE

DEVICE CONFIGURATION IDENTIFY

DEVICE CONFIGURATION SET

Reserved

1F7 h

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

At command issuance (I-O register contents)

1 0 1 1 0 0 x xx xx xx x x xx

C0h/C1h/C2h/C3h

DV xx

0 1

C141-E192-01EN 5-91

Interface

At command completion (I-O register contents)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

Status information x xx x x xx xx xx

Error information

DV xx

• DEVICE CONFIGURATION RESTORE (FR=C0h)

The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a

DEVICE CONFIGURATION IDENTIFY command. After execution of this command, the settings are kept for the device power down or reset.

If a Host Protected Area has been set by a SET MAX ADDRESS (EXT) command, or if DEVICE CONFIGURATION FREEZE LOCK is set, an aborted error is posted.

DEVICE CONFIGURATION FREEZE LOCK (FR=C1h)

The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE

CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION

IDENTIFY, and DEVICE CONFIGURATION RESTORE commands are aborted by the device. The DEVICE CONFIGURATION FREEZE LOCK condition is cleared by a power-down, not cleared by a hardware or software reset.

If the device has executed a previous DEVICE CONFIGURATION FREEZE

LOCK command since power-up, an aborted error is posted.

5-92 C141-E192-01EN

5.3 Host Commands

DEVICE CONFIGURATION IDENTIFY (FR=C2h)

The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5.18. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE command will reflect the reduced set of capabilities, while the DEVICE

CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities.

If the device has executed a previous DEVICE CONFIGURATION FREEZE

LOCK command since power-up, an aborted error is posted.

DEVICE CONFIGURATION SET (FR=C3h)

The DEVICE CONFIGURATION SET command allows to reduce the set of optional commands, modes, or feature sets supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command. The format of the overlay transmitted by the device is described in Table 5.18. As a result to the limitation of the function by the DEVICE CONFIGURATION SET command, is reflected in IDENTIFY information. When the bits in these words are cleared, the device no longer supports the indicated command, mode, or feature set. If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION

IDENTIFY command, no action is taken for that bit. After execution of this command, the settings are kept for the device power down or reset.

If the restriction of Multiword DMA modes or Ultra DMA modes is executed, a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued.

When the Automatic Acoustic Management function is assumed to be a unsupport, Automatic Acoustic Management is prohibited beforehand by

SET FEATURES command (FR=C2h).

If a DEVICE CONFIGURATION SET command has already modified the original settings as reported by a DEVICE CONFIGURATION IDENTIFY command, if DEVICE CONFIGURATION FREEZE LOCK is set, if any of the bit modification restrictions described are violated, or if a Host Protected

Area has been established by the execution of a SET MAX ADDRESS (EXT) command, an aborted error is posted.

C141-E192-01EN 5-93

Interface

Word

0

1

2

3-6

7

8-254

255

Table 5.18 DEVICE CONFIGURATION IDENTIFY data structure

Value

X'0001' Data structure revision

Content

X'0007' Multiword DMA modes supported

Reflected in IDENTIFY information "WORD63".

Bit 15-3: Reserved

Bit 2: 1 = Multiword DMA mode 2 and below are supported

Bit 1: 1 = Multiword DMA mode 1 and below are supported

Bit 0: 1 = Multiword DMA mode 0 is supported

X'003F' Ultra DMA modes supported

Reflected in IDENTIFY information "WORD88".

Bit 15-6: Reserved

Bit 5: 1 = Ultra DMA mode 5 and below are supported

Bit 4: 1 = Ultra DMA mode 4 and below are supported

Bit 3: 1 = Ultra DMA mode 3 and below are supported

Bit 2: 1 = Ultra DMA mode 2 and below are supported

Bit 1: 1 = Ultra DMA mode 1 and below are supported

Bit 0: 1 = Ultra DMA mode 0 is supported

-

X'00CF'

(X'01CF') *

Maximum LBA address Reflected in IDENTIFY information

"WORD60-61". (WORD100-103) *

Command set/feature set supported

Reflected in IDENTIFY information "WORD82-87".

Bit 15-9: Reserved

Bit 8: 1 = 48-bit Addressing feature set supported

Bit 7: 1 = Host Protected Area feature set supported

Bit 6: 1 = Automatic acoustic management supported

Bit 5: 1 = READ/WRITE DMA QUEUED commands supported

Bit 4: 1 = Power-up in Standby feature set supported

Bit 3: 1 = Security feature set supported

Bit 2: 1 = SMART error log supported

Bit 1: 1 = SMART self-test supported

Bit 0: 1 = SMART feature set supported

X'0000' Reserved

X'xxA5' Integrity word. Bits 15:8 contains the data structure checksum that is the two's complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7:0 of word 255.

*: When "48 bit LBA" of the option (customize) is supported, same number of

LBA as WORD60-61 is displayed.

5-94 C141-E192-01EN

5.3 Host Commands

(38) READ NATIVE MAX ADDRESS EXT (27H): Option (customizing)

Description

This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1.

Error reporting conditions

This command is issued with LBA = 0. (ST = 51h, ER= 04h: Aborted command)

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0

1 xx xx xx xx xx xx xx xx xx xx

0

L

0

1

1

DV

0 xx

1 1

C: Current

P: Previous

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L 1

Status information

Native max address LBA (47-40)

Native max address LBA (23-16)

Native max address LBA (39-32)

Native max address LBA (15-8)

Native max address LBA (31-24)

Native max address LBA (7-0) xx xx

Error information

DV xx

0: HOB=0

1: HOB=1

1

C141-E192-01EN 5-95

Interface

(39) SET MAX ADDRESS EXT (37H): Option (customizing)

Description

This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode.

The address information specified with this command is set in words 1, 54,

57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response. If read or write processing is executed for an address that is outside of the new address space, an ID Not Found error occurs.

If the SC register bit is 0 and the value volatile (VV) bit is 1 when this command is executed, the specified values are maintained after a power-on reset. If the VV bit is 0 when the command is executed, the specified values are invalidated during the power-on sequence. If the VV bit is 1, the highest address value is defined as the last value specified. (If the VV bit is not set to

1, the highest address is the default value.)

After a power-on reset is performed, a host can issue the SET MAX

ADDRESS (EXT) command only once if the VV bit is 1. If the SET MAX

ADDRESS (EXT) command is issued twice or more, an ID Not Found error occurs.

When the SET MAX ADDRESS EXT command is executed, all SET MAX

ADDRESS commands are aborted. The address value returns to the origin when the SET MAX ADDRESS EXT command is executed using the address value returned by the READ NATIVE MAX ADDRESS command.

Error reporting conditions

This command is issued twice or more in an operation sequence. (ST =

51h, ER = 10h, ID Not Found)

The READ NATIVE MAX ADDRESS EXT command (27h) is not issued immediately before this command (ST = 51h, ER = 04h, Aborted) is issued.

This command is issued while LBA = 0 (ST = 51h, ER = 04h, Aborted)

The SET MAX ADDRESS command has already been issued.

5-96 C141-E192-01EN

5.3 Host Commands

At command issuance (I/O registers setting contents)

1F7 h

(CM)

1F6 h

(DH)

0

1

0

L

1

1

1

DV

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

SET MAX LBA (47-40)

SET MAX LBA (23-16)

SET MAX LBA (39-32)

SET MAX LBA (15-8)

1F3 h

(SN) P

1F3 h

(SN) C

SET MAX LBA (31-24)

SET MAX LBA (7-0)

1F2 h

(SC) P xx

1F2 h

(SC) C xx

1F1 h

(FR) P xx

1F1 h

(FR) C xx

0 xx

1 1

C: Current

P: Previous

1

VV

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L 1

Status information

SET MAX LBA (47-40)

SET MAX LBA (23-16)

SET MAX LBA (39-32)

SET MAX LBA (15-8)

SET MAX LBA (31-24)

SET MAX LBA (7-0) xx xx

Error information

DV xx

0: HOB=0

1: HOB=1

(40) FLUSH CACHE EXT (EAH): Option (customizing)

Description

This command executes the same operation as the Flush Cache command

(E7h) but only LBA = 1 can be specified.

Error reporting conditions

This command is issued with LBA = 0. (ST = 51h, ER= 10h: Aborted)

C141-E192-01EN 5-97

Interface

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

1

1 xx xx xx xx xx xx xx xx xx xx

1

L

1

1

0

DV

1 xx

0 1

C: Current

P: Previous

0

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 xx xx xx xx xx xx xx xx

L 1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

5-98 C141-E192-01EN

5.3 Host Commands

(41) WRITE DMA EXT (35H): Option (customizing)

Description

This command is the extended command of the WRITE DMA command.

The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the

WRITE DMA command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0 0

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

1

1

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

1

DV

0 xx

1 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

C141-E192-01EN 5-99

Interface

(42) READ DMA EXT (25H): Option (customizing)

Description

This command is the extended command of the READ DMA command. The

LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the

READ DMA command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0

1

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

0

L

1

1

0

DV

0 xx

1 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

5-100 C141-E192-01EN

5.3 Host Commands

(43) WRITE MULTIPLE EXT (39H): Option (customizing)

Description

This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the WRITE MULTIPLE command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0 0

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

1

1

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

1

DV

1 xx

0 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

C141-E192-01EN 5-101

Interface

(44) READ MULTIPLE EXT (29H): Option (customizing)

Description

This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ MULTIPLE command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0 0

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

1

1

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

1

DV

1 xx

0 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

5-102 C141-E192-01EN

5.3 Host Commands

(45) WRITE SECTOR (S) EXT (34H): Option (customizing)

Description

This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the WRITE SECTOR (S) command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0

1

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

0

L

1

1

1

DV

1 xx

0 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

C141-E192-01EN 5-103

Interface

(46) READ SECTOR (S) EXT (24H): Option (customizing)

Description

This command is the extended command of the READ SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ SECTOR (S) command.

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH) P

1F5 h

(CH) C

1F4 h

(CL) P

1F4 h

(CL) C

1F3 h

(SN) P

1F3 h

(SN) C

1F2 h

(SC) P

1F2 h

(SC) C

1F1 h

(FR) P

1F1 h

(FR) C

0

1

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0)

Sector count (15-8)

Sector count (7-0) xx xx

0

L

1

1

0

DV

0 xx

1 0

C: Current

P: Previous

1

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH) 1

1F5 h

(CH) 0

1F4 h

(CL) 1

1F4 h

(CL) 0

1F3 h

(SN) 1

1F3 h

(SN) 0

1F2 h

(SC) 1

1F2 h

(SC) 0

1F1 h

(ER)

1 L

LBA (47-40)

LBA (23-16)

LBA (39-32)

LBA (15-8)

LBA (31-24)

LBA (7-0) xx xx

1

Status information

Error information

DV xx

0: HOB=0

1: HOB=1

5-104 C141-E192-01EN

5.3 Host Commands

(47) DOWNLOAD MICRO CODE (92H)

1F7 h

At command issuance (I/O registers setting contents)

(CM)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(FR)

1

1

0

X

0

1

1

DV

00

00

0

0

Sector count (15-8)

Sector count (7-0)

Subcommand code

0

0

1

0

0

0

At command completion (I/O registers contents to be read)

1F7 h

(ST)

1F6 h

(DH)

1F5 h

(CH)

1F4 h

(CL)

1F3 h

(SN)

1F2 h

(SC)

1F1 h

(ER)

1 X 1

Status information

DV

00

00

XX

XX

0

Error information

0 0 0

This command rewrites the microcode of the device (firmware).

When this command is accepted, the device does beginning the data transfer of the microcode or the microcode rewriting according to Subcommand code

(Rewriting is also possible simultaneously with the data transfer). Refer to Table

5-19.

In the data transfer of Subcommand code:01h, transfer by which data is divided into multiple times is possible. Refer to Table 5-20.

After the designation of rewriting by Subcommand code:07h, reactivates in the device for the update of the rewriting microcode of the microcode.

C141-E192-01EN 5-105

Interface

Table 5.19 Operation of DOWNLOAD MICRO CODE

Host Command Movement of device

Subcommand code

(FR Reg)

01h

07h

Excluding 01h and 07h

Sector count

(SN, SC Reg)

0000h xxxxh

0000h xxxxh

Data transfer

Non

It is.

Non

It is.

Microcode rewriting execution

Rewriting execution reservation

Rewriting execution reservation

Execution. **

Execution. **

Abort

**: In the following cases, Subcommand code=07h returns Abort as an error though becomes Microcode rewriting execution specification.

1) Abnormality of the transmitted Microcode data is detected.

2) The data transfer is not done (The number of transfer: 0).

3) "DOWNLOAD MICROCODE" The command is not continuously issued.

Table 5.20 Example of rewriting procedure of data 384 KBytes (30000h Bytes) of microcode

Transfer example 1:

1) CMD = 92h SN, SC = 0100h FR = 0lh

2) CMD = 92h SN, SC = 0100h FR = 0lh

3) CMD = 92h SN, SC = 0100h FR = 0lh

4) CMD = 92h SN, SC = 0000h FR = 07h

Transfer of 127 KB from the first

Transfer from 128 to 255 KB

Transfer from 256 to 383 KB

Firmware rewriting execution

Transfer example 2:

1)

2)

CMD = 92h SN, SC = 0300h FR = 0lh

CMD = 92h SN, SC = 0000h FR = 07h

Transfer of 384 KB

Firmware rewriting execution

Transfer example 3:

1) CMD = 92h SN, SC = 0300h FR = 07h Transfer of 384 KB and Firmware rewriting execution

Transfer example 4:

1) CMD = 92h SN, SC = 0100h FR = 0lh

2) CMD = 92h SN, SC = 0100h FR = 0lh

3) CMD = 92h SN, SC = 0100h FR = 07h

Transfer of 127 KB from the first

Transfer from 128 to 255 KB

Transfer from 256 to 383 KB and Firmware rewriting execution

When the data of the transfer microcode did the rewriting specification with the illegality and the data transfer not done or the DOWNLOAD MICROCODE command is not continuously issued, reports on the Aborted Command error.

5-106 C141-E192-01EN

5.3 Host Commands

5.3.3 Error posting

Table 5.21 lists the defined errors that are valid for each command.

Table 5.21 Command code and parameters (1 of 2)

Command name

READ SECTOR(S)

WRITE SECTOR(S)

READ MULTIPLE

WRITE MULTIPLE

READ DMA

WRITE DMA

WRITE VERIFY

READ VERIFY SECTOR(S)

RECALIBRATE

SEEK

INITIALIZE DEVICE PARAMETERS

IDENTIFY DEVICE

IDENTIFY DEVICE DMA

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS

READ NATIVE MAX ADDRESS

EXECUTE DEVICE DIAGNOSTIC

READ LONG

WRITE LONG

READ BUFFER

WRITE BUFFER

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

V:

*1:

*2:

Valid on this command

See the command descriptions.

Valid only for Ultra DMA command.

Error register (X’1F1’)

ICRC UNC INDF ABRT TK0NF

Status register (X’1F7’)

DRDY DWF ERR

V V

V

V

V

V

V

V

V

V

V

V

V *2

V *2

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V V

V

V

V

V

V

V

V

V

V

V

V

*1 *1

V

*1

V

V

V

V

V

V

V

*1

V

V

V

V

V

V

V

V

*1

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

C141-E192-01EN 5-107

Interface

Table 5.21 Command code and parameters (2 of 2)

Command name

SLEEP

CHECK POWER MODE

SMART

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

FLUSH CACHE

DEVICE CONFIGURATION

READ NATIVE MAX ADDRESS

EXT *O

SET MAX ADDRESS EXT *O

FLUSH CACHE EXT

WRITE DMA EXT

READ DMA EXT

WRITE MULTIPLE EXT

READ MULTIPLE EXT

WRITE SECTOR (S) EXT

READ SECTOR (S) EXT

DOWNLOAD MICROCODE

Invalid command

*O

*O

*O

*O

*O

*O

*O

Error register (X’1F1’)

ICRC UNC INDF ABRT TK0NF

Status register (X’1F7’)

DRDY DWF ERR

V

V

V

V

V

V

V

V

V

V

V

V

V

V *2

V *2 V

V

V

V

V:

*1:

*2:

Valid on this command

See the command descriptions.

Valid only for Ultra DMA command.

*O: Option (customizing)

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

5-108 C141-E192-01EN

5.4 Command Protocol

5.4 Command Protocol

The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0.

Commands can be executed only when the DRDY bit of the Status register is 1.

However, the following commands can be executed even if DRDY bit is 0.

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

5.4.1 PIO Data transferring commands from device to host

The execution of the following commands involves data transfer from the device to the host.

IDENTIFY DEVICE.

READ SECTOR(S) (EXT)

READ LONG

READ BUFFER

SMART READ DATA

SMART READ LOG SECTOR

The execution of these commands includes the transfer one or more sectors of data from the device to the host. In the READ LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head registers.

b) The host writes a command code to the Command register.

c) The device sets the BSY bit of the Status register and prepares for data transfer.

d) When one sector of data is available for transfer to the host, the device sets

DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.

e) After detecting the INTRQ signal assertion, the host reads the Status register.

The host reads one sector of data via the Data register. In response to the

Status register being read, the device negates the INTRQ signal.

f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are repeated.

Even if an error is encountered, the device prepares for data transfer by setting the

DRQ bit. Whether or not to transfer the data is determined for each host. In other

C141-E192-01EN 5-109

Interface

words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting.

Figure 5.3 shows an example of READ SECTOR(S) command protocol, and

Figure 5.4 shows an example protocol for command abort.

5-110

Figure 5.3 Read Sector(s) command protocol

IMPORTANT

For transfer of a sector of data, the host needs to read Status register

(X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the

C141-E192-01EN

5.4 Command Protocol

device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.

When the host new command even if the device requests the data transfer (setting in DRQ bit), the correct device operation is not guaranteed.

Figure 5.4 Protocol for command abort

5.4.2 PIO Data transferring commands from host to device

The execution of the following commands involves Data transfer from the host to the drive.

WRITE SECTOR(S) (EXT)

WRITE LONG

WRITE BUFFER

WRITE VERIFY

SMART WRITE LOG SECTOR

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

SECURITY SET PASSWORD

SECURITY UNCLOK

C141-E192-01EN 5-111

Interface

The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline.

a) The host writes any required parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head registers.

b) The host writes a command code in the Command register. The drive sets the

BSY bit of the Status register.

c) When the device is ready to receive the data of the first sector, the device sets

DRQ bit and clears BSY bit.

d) The host writes one sector of data through the Data register.

e) The device clears the DRQ bit and sets the BSY bit.

f) When the drive completes transferring the data of the sector, the device clears

BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit.

g) After detecting the INTRQ signal assertion, the host reads the Status register.

h) The device resets INTRQ (the interrupt signal).

i) If transfer of another sector is requested, steps d) and after are repeated.

Figure 5.5 shows an example of WRITE SECTOR(S) command protocol.

5-112 C141-E192-01EN

5.4 Command Protocol

40 ms

Figure 5.5 WRITE SECTOR(S) command protocol

IMPORTANT

For transfer of a sector of data, the host needs to read Status register

(X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred. If the timing to read the Status register does not meet above condition, normal data transfer operation is not assured guaranteed.

When the host issues the command even if the drive requests the data transfer (DRQ bit is set), or when the host executes resetting, the device correct operation is not guaranteed.

5.4.3 Commands without data transfer

Execution of the following commands does not involve data transfer between the host and the device.

• RECABLIBRATE

C141-E192-01EN 5-113

Interface

SEEK

READY VERIFY SECTOR(S)

EXECUTE DEVICE DIAGNOSTIC

INITIALIZE DEVICE PARAMETERS

SET FEATURES

SET MULTIPLE MODE

SET MAX ADDRESS (EXT)

READ NATIVE MAX ADDRESS (EXT)

IDLE

IDLE IMMEDIATE

STANDBY

STANDBY IMMEDIATE

CHECK POWER MODE

SMART DISABLE OPERATION

SMART ENABLE/DISABLE AUTOSAVE

SMART ENABLE OPERATION

SMART EXECUTE OFFLINE IMMEDIATE

SMART RETURN STATUS

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

FLUSH CACHE (EXT)

Figure 5.6 shows the protocol for the command execution without data transfer.

5-114

Figure 5.6 Protocol for the command execution without data transfer

C141-E192-01EN

5.4 Command Protocol

5.4.4 Other commands

READ MULTIPLE (EXT)

SLEEP

WRITE MULTIPLE (EXT)

See the description of each command.

5.4.5 DMA data transfer commands

READ DMA (EXT)

WRITE DMA (EXT)

Starting the DMA transfer command is the same as the READ SECTOR(S) or

WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.

Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed.

The following outlines the protocol:

C141-E192-01EN 5-115

Interface

The interrupt processing for the DMA transfer differs the following point.

• The interrupt processing for the DMA transfer differs the following point.

a) The host writes any parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head register.

b) The host initializes the DMA channel c) The host writes a command code in the Command register.

d) The device sets the BSY bit of the Status register.

e) The device asserts the DMARQ signal after completing the preparation of data transfer. The device asserts either the BSY bit or DRQ bit during DMA data transfer.

f) When the command execution is completed, the device clears both BSY and

DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register.

g) The host resets the DMA channel.

Figure 5.7 shows the correct DMA data transfer protocol.

5-116 C141-E192-01EN

5.4 Command Protocol

f g d d e

Figure 5.7 Normal DMA data transfer

f

C141-E192-01EN 5-117

Interface

5.5 Ultra DMA Feature Set

5.5.1 Overview

Ultra DMA is a data transfer protocol used with the READ DMA and WRITE

DMA commands. When this protocol is enabled it shall be used instead of the

Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command

Block Register access).

Several signal lines are redefined to provide new functions during an Ultra DMA burst. These lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of the control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.

With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0) is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of DD (15:0) and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an

Ultra DMA data out burst.

During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of

STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data.

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time.

All timing requirements for a selected Ultra DMA Mode shall be satisfied.

Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA

Mode 0.

An Ultra DMA capable device shall retain its previously selected Ultra DMA

Mode after executing a Software reset sequence. An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non-

Ultra DMA Modes after executing a Power on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The

5-118 C141-E192-01EN

5.5 Ultra DMA Feature Set

device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

5.5.2 Phases of operation

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6 defines the specific timing requirements). In the following rules DMARDY- is used in cases that could apply to either

DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules.

a) An Ultra DMA burst is defined as the period from an assertion of DMACKby the host to the subsequent negation of DMACK-.

b) A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst.

5.5.3 Ultra DMA data in commands

5.5.3.1 Initiating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert STOP.

4) The host shall negate HDMARDY-.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4) and (5) shall have occurred at least t

ACK

before the host asserts

DMACK-. The host shall keep DMACK- asserted until the end of an Ultra

DMA burst.

7) The host shall release DD (15:0) within t

AZ

after asserting DMACK-.

C141-E192-01EN 5-119

Interface

8) The device may assert DSTROBE t

ZIORDY

after the host has asserted DMACK-.

Once the device has driven DSTROBE the device shall not release

DSTROBE until after the host has negated DMACK- at the end of an Ultra

DMA burst.

9) The host shall negate STOP and assert HDMARDY- within t

ENV

after asserting DMACK-. After negating STOP and asserting HDMARDY-, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

10) The device shall drive DD (15:0) no sooner than t

ZAD

after the host has asserted DMACK-, negated STOP, and asserted HDMARDY-.

11) The device shall drive the first word of the data transfer onto DD (15:0).

This step may occur when the device first drives DD (15:0) in step (10).

12) To transfer the first word of data the device shall negate DSTROBE within t

FS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than t

DVS

DD (15:0).

after driving the first word of data onto

5.5.3.2 The data in transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.3 and 5.6.3.2 for specific timing requirements):

1) The device shall drive a data word onto DD (15:0).

2) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The device shall generate a

DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA

Mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t

CYC

for the selected Ultra DMA mode.

3) The device shall not change the state of DD (15:0) until at least t

DVH

after generating a DSTROBE edge to latch the data.

4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.

5.5.3.3 Pausing an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.4 and 5.6.3.2 for specific timing requirements).

a) Device pausing an Ultra DMA data in burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by not generating

DSTROBE edges.

5-120 C141-E192-01EN

5.5 Ultra DMA Feature Set

NOTE - The host shall not immediately assert STOP to initiate Ultra

DMA burst termination when the device stops generating

STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t

RP

before asserting STOP.

3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.

b) Host pausing an Ultra DMA data in burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by negating HDMARDY-.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst

a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.5 and 5.6.3.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last DSTROBE edge. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating

DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated

DMARQ. The host shall not negate STOP again until after the Ultra

DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated

DMARQ. The host shall continue to negate HDMARDY- until the Ultra

DMA burst is terminated. Steps (4) and (5) may occur at the same time.

C141-E192-01EN 5-121

Interface

5-122

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5):

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (6), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted DSTROBE and negated DMARQ and the host has asserted

STOP and negated HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DSTROBE within t

IORDYZ

after the host negates

DMACK-.

13) The host shall not negate STOP no assert HDMARDY- until at least t

ACK after negating DMACK-.

14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

b) Host terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):

1) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall initiate Ultra DMA burst termination by negating

HDMARDY-. The host shall continue to negate HDMARDY- until the

Ultra DMA burst is terminated.

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than t

SR

C141-E192-01EN

C141-E192-01EN

5.5 Ultra DMA Feature Set

after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

5) The host shall assert STOP no sooner than t

RP

after negating

HDMARDY-. The host shall not negate STOP again until after the Ultra

DMA burst is terminated.

6) The device shall negate DMARQ within t

LI

after the host has asserted

STOP. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) The device shall release DD (15:0) no later than t

AZ

after negating

DMARQ.

9) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).

10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).

11) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted DSTROBE and negated DMARQ and the host has asserted

STOP and negated HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC calculation on DD (15:0).

12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

13) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

14) The device shall release DSTROBE within t

IORDYZ

after the host negates

DMACK-.

15) The host shall neither negate STOP nor assert HDMARDY- until at least t

ACK

after the host has negated DMACK-.

16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

5-123

Interface

5.5.4 Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements):

1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2) The device shall assert DMARQ to initiate an Ultra DMA burst.

3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert STOP.

4) The host shall assert HSTROBE.

5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep

CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6) Steps (3), (4), and (5) shall have occurred at least t

ACK

before the host asserts

DMACK-. The host shall keep DMACK- asserted until the end of an Ultra

DMA burst.

7) The device may negate DDMARDY- t

ZIORDY

after the host has asserted

DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8) The host shall negate STOP within t

ENV

after asserting DMACK-. The host shall not assert STOP until after the first negation of HSTROBE.

9) The device shall assert DDMARDY- within t

LI

after the host has negated

STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

LI

after the device has asserted DDMARDY-. The host shall negate

HSTROBE no sooner than t

DVS

after the driving the first word of data onto

DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):

1) The host shall drive a data word onto DD (15:0).

5-124 C141-E192-01EN

5.5 Ultra DMA Feature Set

2) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of DD (15:0). The host shall generate an

HSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA

Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t

CYC

for the selected Ultra DMA mode.

3) The host shall not change the state of DD (15:0) until at least t

DVH

after generating an HSTROBE edge to latch the data.

4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).

a) Host pausing an Ultra DMA data out burst

1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The host shall pause an Ultra DMA burst by not generating an

HSTROBE edge.

Note: The device shall not immediately negate DMARQ to initiate Ultra

DMA burst termination when the host stops generating

HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate

DDMARDY- and wait t

RP

before negating DMARQ.

3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.

b) Device pausing an Ultra DMA data out burst

1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall pause an Ultra DMA burst by negating DDMARDY-.

3) The host shall stop generating HSTROBE edges within t

RFS

of the device negating DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.

C141-E192-01EN 5-125

Interface

5.5.4.4 Terminating an Ultra DMA data out burst

a) Host terminating an Ultra DMA data out burst

The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):

1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.

2) The host shall assert STOP no sooner than t

SS

after it last generated an

HSTROBE edge. The host shall not negate STOP again until after the

Ultra DMA burst is terminated.

3) The device shall negate DMARQ within t

LI

after the host asserts STOP.

The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.

4) The device shall negate DDMARDY- with t

LI

after the host has negated

STOP. The device shall not assert DDMARDY- again until after the

Ultra DMA burst termination is complete.

5) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE.

HSTROBE shall remain asserted until the Ultra DMA burst is terminated.

6) The host shall place the result of its CRC calculation on DD (15:0) (see

5.5.5)

7) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted HSTROBE and STOP and the device has negated DMARQ and

DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

10) The device shall release DDMARDY- within t

IORDYZ

after the host has negated DMACK-.

11) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating DMACK-.

12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

5-126 C141-E192-01EN

5.5 Ultra DMA Feature Set

b) Device terminating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements):

1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

2) The device shall initiate Ultra DMA burst termination by negating

DDMARDY-.

3) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating DDMARDY-.

4) If the device negates DDMARDY- within t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater than t

SR

after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the host.

5) The device shall negate DMARQ no sooner than t

RP

after negating

DDMARDY-. The device shall not assert DMARQ again until after the

Ultra DMA burst is terminated.

6) The host shall assert STOP with t

LI

after the device has negated DMARQ.

The host shall not negate STOP again until after the Ultra DMA burst is terminated.

7) If HSTROBE is negated, the host shall assert HSTROBE with t

LI

after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE.

HSTROBE shall remain asserted until the Ultra DMA burst is terminated.

8) The host shall place the result of its CRC calculation on DD (15:0) (see

5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the host has asserted HSTROBE and STOP and the device has negated DMARQ and

DDMARDY-, and no sooner than t

DVS

after placing the result of its CRC calculation on DD (15:0).

10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-.

11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).

12) The device shall release DDMARDY- within t

IORDYZ

after the host has negated

DMACK-.

C141-E192-01EN 5-127

Interface

13) The host shall neither negate STOP nor HSTROBE until at least t

ACK

after negating DMACK-.

14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t

ACK

after negating DMACK.

5.5.5 Ultra DMA CRC rules

The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.

a) Both the host and the device shall have a 16-bit CRC calculation function.

b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.

c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.

d) For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.

e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD (15:0) with the negation of

DMACK-.

f) The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra

DMa burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.

g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by re-issuing the command.

h) A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.

5-128 C141-E192-01EN

5.5 Ultra DMA Feature Set

i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.

Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe.

The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.

5.5.6 Series termination required for Ultra DMA

Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes. The following table describes recommended values for series termination at the host and the device.

Table 5.22 Recommended series termination for Ultra DMA

Signal Host Termination Device Termination

DIOR-:HDMARDY-:HSTROBE

DIOW-:STOP

CS0-, CS1-

DA0, DA1, DA2

22 ohm

22 ohm

33 ohm

33 ohm

82 ohm

82 ohm

82 ohm

82 ohm

DMACK22 ohm 82 ohm

DD15 through DD0 33 ohm 22 ohm

DMARQ

INTRQ

82 ohm

82 ohm

22 ohm

22 ohm

IORDY:DDMARDY-:DSTROBE 82 ohm 22 ohm

RESET33 ohm 82 ohm

Note: Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA Mode. For signals also requiring a pull-up or pull-down resistor at the host see Figure 5.8.

Vcc

Figure 5.8 Ultra DMA termination with pull-up or pull-down

C141-E192-01EN 5-129

Interface

5.6 Timing

5.6.1 PIO data transfer

Figure 5.9 shows of the data transfer timing between the device and the host system.

t0

Addresses t1 t9

DIOR-/DIOWt2 t2i

Write data

DD0-DD15 t3 t4

Read data

DD0-DD15 t5 t6

IORDY t10 t11 t12

Symbol t2i t3 t4 t5 t6 t9 t0 t1 t2 t10 t11 t12

Timing parameter

Cycle time

Data register selection setup time for DIOR-/DIOW-

Pulse width of DIOR-/DIOW-

Recovery time of DIOR-/DIOW-

Data setup time for DIOW-

Data hold time for DIOW-

Time from DIOR- assertion to read data available

Data hold time for DIOR-

Data register selection hold time for DIOR-/DIOW-

Time from DIOR-/DIOW- assertion to IORDY "low" level

Time from validity of read data to IORDY "high" level

Pulse width of IORDY

Min.

Max.

Unit

120 —

25 —

70 —

25

20

10 —

— 50

5

10

— 35

0 — ns ns

— 1,250 ns ns ns ns ns ns ns ns ns ns

Figure 5.9 PIO data transfer timing

5-130 C141-E192-01EN

5.6 Timing

5.6.2 Multiword data transfer

Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system.

DMACKt

I

DIOR-/DIOWt

D

Symbol t0 tD tE tF tG tH tI t

Timing parameter

Cycle time

Pulse width of DIOR-/DIOW-

Data Access time for DIOR-

Data hold time for DIOR-

Data setup time for DIOR-/DIOW-

Data hold time for DIOW-

DMACK setup time for DIOR-/DIOW-

CS (1:0) Available time for DIOR-/DIOW-

Figure 5.10 Multiword DMA data transfer timing (mode 2)

Min.

Max.

Unit

120

70

5 —

20 —

50

10

0 —

25 — ns ns ns ns ns ns ns ns

C141-E192-01EN 5-131

Interface

5.6.3 Ultra DMA data transfer

Figures 5.11 through 5.20 define the timings associated with all phases of Ultra

DMA bursts.

Table 5.23 contains the values for the timings for each of the Ultra DMA Modes.

5.6.3.1 Initiating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host) t

UI

t

ACK

t

ACK

t

ZIORDY

t

ENV

t

ENV

t

FS

t

ZAD

t

FS

t

ZAD

t

ZFS

t

DZFS

t

VDS

DSTROBE

(device)

DD (15:0)

DA0,DA1,DA2,

CS0-,CS1t

ACK

t

AZ

t

DVH

Note:

The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted.

Figure 5.11 Initiating an Ultra DMA data in burst

5-132 C141-E192-01EN

5.6 Timing

5.6.3.2 Ultra DMA data burst timing requirements

Table 5.23 Ultra DMA data burst timing requirements (1 of 2)

t

CS t

CH t

CVS t t t t t

NAME MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

MODE 5

(in ns)

COMMENT t t t t

2CYCTYP t

CYC

2CYC

DS

DH

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

240 160 120 90 60 40

112

230

15

5

73

153

10

5

54

115

7

5

39

86

7

5

25

57

5

5

16.8

38

4

4.6

Typical sustained average two cycle time

Cycle time allowing for asymmetry and clock variations

(from STROBE edge to STROBE edge)

Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of

STROBE)

Data setup time at recipient (from data valid until STROBE edge)

(*2), (*5)

Data hold time at recipient (from

STROBE edge until data may become invalid) (*2), (*5) t

DVS

DVH

CVH

ZFS

DZFS

FS

70

6.2

15

5

70

6.2

0

70

230

48

6.2

10

5

48

6.2

0

48

200

31

6.2

7

5

31

6.2

0

31

170

20

6.2

7

5

20

6.2

0

20

130

6.7

6.2

5

5

6.7

6.2

0

6.7

120

4.8

4.8

5

5

10

10

35

25

Data valid setup time at sender

(from data valid until STROBE edge) (*3)

Data valid hold time at sender

(from STROBE edge until data may become invalid) (*3)

CRC word setup time at device

(*2)

CRC word hold time device (*2)

CRC word valid setup time at host (from CRC valid until

DMACK-negation) (*3)

CRC word valid hold time at sender (from DMACK-negation until CRC may become invalid)

(*3)

Time from STROBE output released-to-driving until the first transition of critical timing

Time from data output releasedto-driving until the first transition of critical timing

90 First STROBE time (for device to first negate DSTROBE from

STOP during a data in burst)

C141-E192-01EN 5-133

Interface

Table 5.23 Ultra DMA data burst timing requirements (2 of 2)

NAME MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

MODE 5

(in ns)

COMMENT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t

LI t

MLI

T

UI t

AZ

0

20

0

150 0

20

0

150 0

20

0

150 0

20

0

100 0

20

0

100 0

20

0

75 Limited interlock time (*1)

Interlock time with minimum (*1)

Unlimited interlock time (*1) t t t t t t t t t

ZAH

ZAD

ENV

RFS

RP

IORDYZ

ZIORDY

ACK

SS

20

0

20

160

0

20

50

10

70

75

20

20

0

20

125

0

20

50

10

70

70

20

20

0

20

100

0

20

50

10

70

60

20

20

0

20

100

0

20

50

10

55

60

20

20

0

20

100

0

20

50

10

55

60

20

20

0

20

85

0

20

50

10 Maximum time allowed for output drivers to release (from asserted or negated)

Minimum delay time required for output

Drivers to assert or negate (from released)

50 Envelope time (from DMACK- to

STOP and HDMARDY- during data in burst initiation and from

DMACK to STOP during data out burst initiation)

50 Ready-to-final-STROBE time (no

STROBE edges shall be sent this long after negation of DMARDY-)

Ready-to-pause time (that recipient shall wait to pause after negating DMARDY-)

20 Maximum time before releasing

IORDY

Minimum time before driving

IORDY (*4)

Setup and hold times for

DMACK- (before assertion or negation)

Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst)

*1: Except for some instances of t

MLI

that apply to host signals only, the parameters t

UI,

t

MLI

and t

LI

indicate sender-to-recipient or recipientto-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. t

UI

is an unlimited interlock that has no maximum time value. t

MLI

is a limited time-out that has a defined minimum. t

LI is a limited time-out that has a defined maximum.

*2: 80-conductor cabling shall be required in order to meet setup (t

DS

, t

CS

) and hold (t

DH

, t

CH

) times in modes greater than 2.

*3: Timing for t

DVS

, t

DVH

, t

CVS

and t

CVH

shall be met for lumped capacitive loads of 15 and 40 pf at the connector where all signals (Data and

STROBE) have the same capacitive load value. Due to reflections on the cable, the measurement of these timings is not valid in a normally functioning system.

*4: For all modes the parameter t

ZIORDY

may be greater than t

ENV

due to the fact that the host has a pull up on IORDY- giving it a known state when not actively driven.

*5: The parameters t

DS

, and t

DH

for mode 5 is defined for a recipient at the end of the cable only in a configuration with one device at the end of the cable.

Note: All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.

5-134 C141-E192-01EN

5.6 Timing

Table 5.24 Ultra DMA sender and recipient timing requirements

NAME

MODE 0

(in ns)

MODE 1

(in ns)

MODE 2

(in ns)

MODE 3

(in ns)

MODE 4

(in ns)

MODE 5

(in ns)

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

COMMENT t t t t

DSIC

DHIC

DVSIC

DVHIC

14.7

4.8

72.9

9

9.7

4.8

50.9

9

6.8

4.8

33.9

9

6.8

4.8

22.6

9

4.8

4.8

9.5

9

2.3

2.8

6

6

Recipient IC data setup time (from data valid until STROBE edge)

(*1)

Recipient IC data hold time (from

STROBE edge until data may become invalid) (*1)

Sender IC data valid setup time

(from data valid until STROBE edge) (*2)

Sender IC data valid hold time

(from STROBE edge until data may become invalid) (*2)

*1: The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input

STROBE with a slew rate of 0.4 V/ns rising and falling at t

DSIC

and t

DHIC timing (as measured through 1.5V).

*2: The parameters t

DVSIC

and t

DVHIC

shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources in a normally functioning system has not been included in these values.

Note:

All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.

C141-E192-01EN 5-135

Interface

5.6.3.3 Sustained Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

t

2CYC

t

CYC

t

CYC

t

2CYC

DSTROBE at device t

DVH

t

DVHIC

t

DVS

t

DVSIC

t

DVH

t

DVHIC

t

DVS

t

DVSIC

t

DVH

t

DVHIC

DD(15:0) at device

DSTROBE at host

DD(15:0) at host t

DH

t

DHIC

t

DS

t

DSIC

t

DH

t

DHIC

t

DS

t

DSIC

t

DH

t

DHIC

Note:

DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.

Figure 5.12 Sustained Ultra DMA data in burst

5-136 C141-E192-01EN

5.6 Timing

5.6.3.4 Host pausing an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device)

DMACK-

(host) t

RP

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

DD(15:0)

(device) t

RFS

Notes:

1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t

RP

after HDMARDY- is negated.

2) After negating HDMARDY-, the host may receive zero, one, two or three more data words from the device.

Figure 5.13 Host pausing an Ultra DMA data in burst

C141-E192-01EN 5-137

Interface

5.6.3.5 Device terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device) t

MLI

DMACK-

(host) t

LI

t

LI

t

ACK

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device) t

SS

t

LI

t

ACK

t

IORDYZ

t

ZAH

t

AZ

DD(15:0) t

CVS t

CVH

CRC t

ACK

DA0, DA1, DA2,

CS0-, CS1-

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

Figure 5.14 Device terminating an Ultra DMA data in burst

5-138 C141-E192-01EN

5.6 Timing

5.6.3.6 Host terminating an Ultra DMA data in burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device) t

LI

t

MLI

DMACK-

(host) t

AZ

t

ZAH

t

RP

t

ACK

STOP

(host) t

ACK

HDMARDY-

(host) t

MLI

t

RFS

t

LI

t

IORDYZ

DSTROBE

(device)

DD(15:0) t

CVS t

CVH

CRC t

ACK

DA0, DA1, DA2,

CS0, CS1

Note:

The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

Figure 5.15 Host terminating an Ultra DMA data in burst

C141-E192-01EN 5-139

Interface

5.6.3.7 Initiating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device) t

UI

t

ACK

t

ZIORDY

t

ENV

t

LI

t

UI

t

ACK

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2

CS0-, CS1t

ACK

t

DZFS

t

DVS

t

DVH

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted.

Figure 5.16 Initiating an Ultra DMA data out burst

5-140 C141-E192-01EN

5.6 Timing

5.6.3.8 Sustained Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

t

2CYC t

CYC t

CYC t

2CYC

HSTROBE at host t

DVH t

DVHIC t

DVS t

DVSIC t

DVH t

DVHIC t

DVS t

DVSIC t

DVH

t

DVHIC

DD(15:0)

at host

HSTROBE at device

DD(15:0) at device t

DH

t

DHIC

t

DS

t

DSIC

t

DH

t

DHIC

t

DS

t

DSIC

t

DH

t

DHIC

Note:

DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.

Figure 5.17 Sustained Ultra DMA data out burst

C141-E192-01EN 5-141

Interface

5.6.3.9 Device pausing an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

t

RP

DMARQ

(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device) t

RFS

HSTROBE

(host)

DD(15:0)

(host)

Notes:

1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t

RP

after DDMARDY- is negated.

2) After negating DDMARDY-, the device may receive zero, one two or three more data words from the host.

Figure 5.18 Device pausing an Ultra DMA data out burst

5-142 C141-E192-01EN

5.6 Timing

5.6.3.10 Host terminating an Ultra DMA data out burst

DMARQ

(device)

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

t

LI

t

MLI

DMACK-

(host) t

LI

t

SS

t

ACK

STOP

(host) t

LI

t

IORDYZ

DDMARDY-

(device) t

ACK

HSTROBE

(host) t

CVS

t

CVH

DD(15:0)

(host)

CRC t

ACK

DA0, DA1, DA2

CS0-, CS1-

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

Figure 5.19 Host terminating an Ultra DMA data out burst

C141-E192-01EN 5-143

Interface

5.6.3.11 Device terminating an Ultra DMA data out burst

5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

DMARQ

(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device) t

RP

t

LI

t

MLI

t

ACK

t

IORDYZ

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1t

RFS

t

LI

t

MLI

t

ACK

t

CVS

CRC t

CVH t

ACK

Note:

The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.

Figure 5.20 Device terminating an Ultra DMA data out burst

5-144 C141-E192-01EN

5.6 Timing

5.6.4 Power-on and reset

Figure 5.21 shows power-on and reset (hardware and software reset) timing.

(1) Only master device is present

Clear Reset *1

Power-on

RESET-

Software reset tM tN

BSY

DASPtP

*1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset.

(2) Master and slave devices are present (2-drives configuration)

Clear Reset tN

[Master device]

BSY

DASP-

[Slave device]

BSY

PDIAG-

DASPtP tQ tS tR

Symbol tM tN tP tQ tR tS

Timing parameter

Pulse width of RESET-

Time from RESET- negation to BSY set

Time from RESET- negation to DASP- or DIAG- negation

Self-diagnostics execution time

Time from RESET- negation to DASP- assertion (slave device)

Duration of DASP- assertion

Figure 5.21 Power-on Reset Timing

Min.

Max.

Unit

25 —

400

— 1

30

400 ns

µ s ms s ms

— 31 s

C141-E192-01EN 5-145

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Key Features

  • 80 GB 2.5" 4200 RPM Ultra-ATA/100
  • HDD
  • Storage drive buffer size: 8 MB
  • 99 g

Related manuals

Frequently Answers and Questions

What is the capacity of the Fujitsu MHT2020AT?
The Fujitsu MHT2020AT has a capacity of 20GB.
What is the rotational speed of the Fujitsu MHT2020AT?
The Fujitsu MHT2020AT has a rotational speed of 5400RPM.
What interface does the Fujitsu MHT2020AT use?
The Fujitsu MHT2020AT uses the ATA interface.
Is the Fujitsu MHT2020AT shock-resistant?
Yes, the Fujitsu MHT2020AT is shock-resistant.
What is the form factor of the Fujitsu MHT2020AT?
The Fujitsu MHT2020AT has a 2.5-inch form factor.

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