6.2.2.Timing of Host Interface(PIO). Toshiba XM-7002B

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6.2.2.Timing of Host Interface(PIO). Toshiba XM-7002B | Manualzz

6.2.2. Timing of Host Interface (PIO)

Figure 10 shows the Host Interface Timings.

Address valid*1 t2 t1

DIOR-/DIOW-

Write data valid*2 t0 t3

Read data valid*2 t5 t7

IOCS16-

IORDY tA tB tRD t9

t2i t8 t4 t6Z t6

*1:Device Address consists of signals CS0-, CS1-, and DA2-0

*2:Data consists of DD0-15 (16-bit) or DD0-7 (8-bit) t0 t1 t2 DIOR-/DIOW- pulse wide

t2i

DIOR-/DIOW- recovery time t3 DIOW- data setup t4 t5

PIO Mode 4 timing parameters min(ns) max(ns)

Min Time (ns) Max Time (ns)

Cycle time

Address valid to DIOR-/DIOW-setup

DIOW- data hold

DIOR- data setup

120

25

70

25

20

10

20

5 t6 t8

DIOR- data hold t6Z DIOR- data tristate t7 Addr valid to IOCS16- assertion

Addr valid to IOCS16- negation t9 DIOR-/DIOW- to address valid hold tRD Read Data Valid to IORDY active tA tB

IORDY setup time

IORDY pulse wide

10

0

30

30

30

35

1250

Figure 10 Host Interface Timin

15/27

XM-7002B Rev.1.0

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