16. CPU Problem Bypasses and Checks. Altium TriCore
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Chapter 16. CPU Problem Bypasses and
Checks
Infineon Technologies regularly publishes microcontroller errata sheets for reporting both functional problems and deviations from the electrical and timing specifications.
For some of these functional problems in the microcontroller itself, the TASKING VX-toolset for TriCore provides workarounds. In fact these are software workarounds for hardware problems.
Support to deal with CPU functional problem is provided in three areas:
• Whenever possible and relevant, compiler bypasses will modify the code in order to avoid the identified erroneous code sequences;
• The assembler gives warnings for suspicious or erroneous code sequences;
• Ready-built, 'protected' standard C libraries with bypasses for all identified TriCore CPU functional problems are included in the toolset.
This chapter lists a summary of functional problems which can be bypassed by the TASKING VX-toolset for TriCore. Please refer to the Infineon errata sheets for the CPU step you are using, to verify if you need to use one of these bypasses.
To set a CPU bypass or check
1.
From the Project menu, select Properties
The Properties dialog appears.
2.
In the left pane, expand C/C++ Build and select Processor.
In the right pane the Processor page appears.
3.
From the Processor Selection list, select a processor.
The CPU Problem Bypasses and Checks box shows the available workarounds/checks available for the selected processor.
4.
(Optional) Select Show all CPU problem bypasses and checks.
5.
Click Select All or select one or more individual options.
Overview of the CPU problem bypasses and checks
The following table contains an overview of the silicon bugs you can provide to the
and the assembler option --silicon-bug
. WA means a workaround by the compiler, assembler and/or linker, CK means a check by the assembler.
793
TASKING VX-toolset for TriCore User Guide
CPU Problem Description
Unreliable context load/store operation following an address register load instruction
Compiler
WA
Assembler
CK
CK
Linker CPU
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796,
TC1910, TC1912, TC1920
TC1765, TC1775 LOOP over arithmetical instruction causes a jump to an undefined address
WA
Incorrect forwarding from branch and link address register update
CALLI with target address in register A11 not functional
WA CK
CK
TC1765, TC1775
TC1765, TC1775
CK TC1765, TC1775
Incorrect return address in
A11 when performing nested calls
WA
WA Loop bug following the
DVSTEP type instruction
Wrong return address after any divide instruction
Circular addressing mode limitations
WA
WA
DSYNC causes corruption of up to two following instructions
WA
A load/store instruction to the last 16 bytes of a segment can lead to undefined behavior
CPU fetches program from unexpected address
WA
CK
CK
WA
CK
CK
CK
WA
WA
TC1765, TC1775
TC1765, TC1775
TC1765, TC1775
TC1765, TC1775
TC1765, TC1775
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796,
TC1910, TC1912, TC1920
TC1765, TC1775
A load instruction following a multicycle integer instruction can get lost
WA
Reduced context save area
Alignment Restrictions for
Accesses using PTE-Based
Translation
WA
LD.[A,DA] followed by a dependent LD.[DA,D,W] can produce unreliable results
WA
WA
CK
WA TC1910, TC1912, TC1920
TC1100, TC1115, TC1130,
TC11IB
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796,
TC1910, TC1912, TC1920
794
CPU Problem Bypasses and Checks
CPU Problem
Description
Error when unconditional loop targets unconditional jump
Potential PSW corruption by cancelled DVINIT instructions
Compiler Assembler Linker CPU
WA
WA
CK
CK
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
Potential incorrect operation of RSLCX instruction
WA CK
Error when conditional jump precedes loop instruction
Error when Conditional Loop targets Unconditional Loop
Error when Loop Counter modified prior to Loop instruction
Interleaved LOOP/LOOPU instructions may cause
GRWP Trap
Error during Load A[10], Call
/ Exception Sequence
Data corruption possible when Memory Load follows
Context Store
Interrupt may be taken following DISABLE instruction
WA
WA
WA
WA
WA
CK
CK
CK
WA
CK
CK
CK
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1765, TC1766,
TC1775, TC1792, TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
Potential Performance Loss when CSA Instruction follows
IP Jump
WA
Incorrect Forwarding in SAT,
Mixed Register Instruction
Sequence
WA
Error when Conditional Loop targets Single Issue Group
Loop
WA
Spurious parity errors can be generated
WA
CK
CK
CK
WA
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC11IB, TC1766, TC1792,
TC1796
TC1100, TC1115, TC1130,
TC1766
795
TASKING VX-toolset for TriCore User Guide
CPU Problem Description
Double-word Load instructions using Circular
Addressing mode can produce unreliable results
Compiler
WA
RMW accesses to DMU memory are not locked
MMU-PMU Address
Translation
PMU not addressable in split mode via the LFI, bug will trigger an LMB_ABORT
WA
Assembler
CK
CK
CK
CK
Linker CPU
TC1100, TC1115, TC1130,
TC1766, TC1792, TC1796,
TC1792, TC1796
TC11IB, TC1765, TC1775
TC11IB, TC1920
TC11IB, TC1920
TC1161, TC1162, TC1163, TC1164, TC1165, TC1166, TC1762, TC1764 have the same silicon bugs as the TC1766.
796
CPU Problem Bypasses and Checks
CPU_TC.013
Command line option
--silicon-bug=cpu-tc013
Description
To bypass this CPU functional problem, the C compiler generates a
NOP16
instruction if a 16-bit load/store address register instruction (instructions:
LD16.A
and
ST16.A
) is followed by a lower context load/store instruction (instructions:
LDLCX
and
STLCX
).
The assembler issues a warning if a 16-bit load/store address register instruction (instructions:
LD16.A
and
ST16.A
) is followed by a lower context load/store instruction (instructions:
LDLCX
and
STLCX
).
797
TASKING VX-toolset for TriCore User Guide
CPU_TC.018
Command line option
--silicon-bug=cpu-tc018
Description
To bypass this CPU functional problem, the C compiler generates an
ISYNC
instruction before each
LOOP
,
LOOP16
and
LOOPU
instruction.
The assembler issues a warning when the preceding instruction of a
LOOP
,
LOOP16
or
LOOPU
instruction is not an
ISYNC
instruction.
798
CPU Problem Bypasses and Checks
CPU_TC.021
Command line option
--silicon-bug=cpu-tc021
Description
To bypass this CPU functional problem, the C compiler generates a
NOP
instruction between a (target) label and the instruction following it This is done when the instruction directly uses an
An
register for either an effective address calculation or as the target of an indirect branch. Optionally an integer instruction may directly follow the label.
For example, a
NOP
will be inserted after the following labels:
A_label:
ji a4
B_label:
add d0, d1 ; integer instruction
ji a4
The assembler issues a warning for an instruction using an
An
register for either an effective address calculation or as the target of an indirect branch that is located directly after a (target) label, optionally with an integer instruction in between.
799
TASKING VX-toolset for TriCore User Guide
CPU_TC.023
Command line option
--silicon-bug=cpu-tc023
Description
There is no C compiler workaround required for this CPU functional problem, because the compiler does not generate CALLI instructions with a target address in register
A11
.
The assembler generates an error for instruction
CALLI A11
.
800
CPU Problem Bypasses and Checks
CPU_TC.024
Command line option
--silicon-bug=cpu-tc024
Description
To bypass this CPU functional problem, the C compiler generates a
NOP
instruction at the very top of any subroutine that starts with a
CALL
instruction or that starts with an integer instruction or
MAC
instruction directly followed by a
CALL
instruction.
The assembler issues a warning when the first instruction of a subroutine is a
CALL
instruction or an integer instruction or
MAC
instruction directly followed by a
CALL
instruction.
801
TASKING VX-toolset for TriCore User Guide
CPU_TC.030
Command line option
--silicon-bug=cpu-tc030
Description
To bypass this CPU functional problem, the C compiler generates an
ISYNC
instruction prior to the
LOOP instruction if the last instruction in the loop is a
DVSTEP
or a
DVSTEP.U
.
The assembler issues a warning for loops where the last instruction is a
DVSTEP
or a
DVSTEP.U
.
802
CPU Problem Bypasses and Checks
CPU_TC.031
Command line option
--silicon-bug=cpu-tc031
Description
To bypass this CPU functional problem, the C compiler generates an
ISYNC
instruction prior to the
LOOP instruction.
The assembler issues a warning if the
LOOP
instruction is not preceded by an
ISYNC
instruction.
803
TASKING VX-toolset for TriCore User Guide
CPU_TC.033
Command line option
--silicon-bug=cpu-tc033
Description
To bypass this CPU functional problem, the C compiler aligns circular qualified buffers to a quad-word boundary, and the compiler sizes all stack frames to an integral number of quad-words.
See
Section 1.3.1, Circular Buffers: __circ
for a description on how to declare a circular buffer.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to enable initialization of the stack pointers to a quad-word boundary.
The preprocessor define
__CPU_TC033__
is used in the tc*.lsl
linker script files to set the alignment of the user stack and the interrupt stack to a quad-word alignment.
804
CPU Problem Bypasses and Checks
CPU_TC.034
Command line option
--silicon-bug=cpu-tc034
Description
To bypass this CPU functional problem, the C compiler generates an
ISYNC
instruction after each
DSYNC instruction.
The assembler issues a warning if a
DSYNC
instruction is not followed by an
ISYNC
instruction.
805
TASKING VX-toolset for TriCore User Guide
CPU_TC.043
Command line option
--silicon-bug=cpu-tc043
Description
To bypass this CPU functional problem, the preprocessor define
__CPU_TC043__
is used in the tc*.lsl
linker script files. The linker will not use the last 16 bytes of a segment.
806
CPU Problem Bypasses and Checks
CPU_TC.048
Command line option
--silicon-bug=cpu-tc048
Description
To bypass this CPU functional problem, the C compiler generates a
NOP
instruction before a
JI
or
CALLI instruction when this instruction is not directly preceded by either a
NOP
instruction or an integer instruction or a
MAC
instruction. The compiler also generates a
NOP
instruction before a
RET
and
RET16
instruction if there is no or just one instruction before
RET
, starting from the function entry point.
The assembler issues a warning when a
JI
or
CALLI
instruction is not directly preceded by a
NOP instruction. The assembler also issues a warning when there is no or just one instruction (not a
NOP instruction) between label and
RET
or
RET16
.
807
TASKING VX-toolset for TriCore User Guide
CPU_TC.050
Command line option
--silicon-bug=cpu-tc050
Description
To bypass this CPU functional problem, the C compiler generates a
NOP
instruction between a multi-cycle integer instruction and a load instruction.
The assembler issues a warning if a multi-cycle integer instruction is directly followed by a load instruction.
808
CPU Problem Bypasses and Checks
CPU_TC.051
Command line option
--silicon-bug=cpu-tc051
Description
The C compiler has no workaround for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code.
To bypass this CPU functional problem, the preprocessor define
__CPU_TC051__
is used in the tc*.lsl
linker script files. The linker will use more than one section for context stores if the required CSA area exceeds the 4 kB. Each section will have a maximum size of 4 kB and will start on an 8 kB boundary.
809
TASKING VX-toolset for TriCore User Guide
CPU_TC.052
Command line option
--silicon-bug=cpu-tc052
Description
To bypass this CPU functional problem, the C compiler prevents load ( ld
) and store ( st
) instructions to be combined.
For example, silicon bug workaround CPU_TC052 prevents that two
LD.W
instructions are combined into one
LD.DW
instruction.
There is no assembler check for this silicon bug.
810
CPU Problem Bypasses and Checks
CPU_TC.060
Command line option
--silicon-bug=cpu-tc060
Description
To bypass this CPU functional problem, the C compiler generates a
NOP
instruction between an
LD.A
/
LD.DA
instruction and a following
LD.W
/
LD.D
instruction, even if an integer instruction occurs in between.
The assembler issues a warning when an
LD.A
/
LD.DA
instruction is directly followed by an
LD.W
/
LD.D
instruction, or when only an integer instruction is in between.
811
TASKING VX-toolset for TriCore User Guide
CPU_TC.065
Command line option
--silicon-bug=cpu-tc065
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction before a jump, when a label is directly followed by an unconditional jump.
The assembler issues a warning when a label is directly followed by an unconditional jump, only when debug information is turned off.
812
CPU Problem Bypasses and Checks
CPU_TC.068
Command line option
--silicon-bug=cpu-tc068
Description
To bypass this CPU functional problem, the C compiler inserts a
DISABLE
and two
NOP
instructions before each
DVINIT
instruction (and if necessary an
ENABLE
after
TGE DVINIT
).
The assembler issues a warning when a
DVINIT
instruction is not preceded by a
DISABLE
and two
NOP instructions.
813
TASKING VX-toolset for TriCore User Guide
CPU_TC.069
Command line option
--silicon-bug=cpu-tc069
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction after each
RSLCX instruction.
The assembler issues a warning when an
RSLCX
instruction is not followed by a
NOP
instruction.
814
CPU Problem Bypasses and Checks
CPU_TC.070
Command line option
--silicon-bug=cpu-tc070
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction before a loop instruction, when a conditional jump, based on the value in an address register, is directly followed by a loop instruction.
The compiler inserts two
NOP
instructions before a loop instruction, when a conditional jump, based on the value in a data register, is directly followed by a loop instruction.
The assembler issues a warning when a conditional jump, based on the value in an address register, is directly followed by a loop instruction.
The assembler issues a warning when a conditional jump, based on the value in a data register, is directly followed by a loop instruction or when only a single
NOP
instruction is in between.
815
TASKING VX-toolset for TriCore User Guide
CPU_TC.071
Command line option
--silicon-bug=cpu-tc071
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction before a loop instruction, when a label is directly followed by an unconditional loop instruction.
The assembler issues a warning when a label is directly followed by an unconditional loop instruction, only when debug information is turned off.
816
CPU Problem Bypasses and Checks
CPU_TC.072
Command line option
--silicon-bug=cpu-tc072
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction before a loop instruction, when an instruction that updates an address register is followed by a conditional loop instruction which uses this address register.
The assembler issus a warning when an instruction that updates an address register is followed by a conditional loop instruction which uses this address register.
817
TASKING VX-toolset for TriCore User Guide
CPU_TC.074
Command line option
--silicon-bug=cpu-tc074
Description
The C compiler has no workaround for this problem.
To bypass this CPU functional problem, the assembler encodes the
LOOPU
instruction in such a way that bits 12-15 get the value 1.
818
CPU Problem Bypasses and Checks
CPU_TC.081
Command line option
--silicon-bug=cpu-tc081
Description
The C compiler has no workaround for this problem.
The assembler issues a warning when an address register load instruction,
LD.A
or
LD.DA
, targeting the
A[10]
register, is immediately followed by an operation causing a context switch.
819
TASKING VX-toolset for TriCore User Guide
CPU_TC.082
Command line option
--silicon-bug=cpu-tc082
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction between a context store operation,
STUCX
or
STLCX
, and a memory load operation which reads from the last double-word address written by the context store.
The assembler issues a warning when a context store operation,
STUCX
or
STLCX
, is immediately followed by a memory load operation which reads from the last double-word address written by the context store.
820
CPU Problem Bypasses and Checks
CPU_TC.083
Command line option
--silicon-bug=cpu-tc083
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction after each
DISABLE instruction.
The assembler issues a warning when the
DISABLE
instruction is not followed by a
NOP
instruction.
821
TASKING VX-toolset for TriCore User Guide
CPU_TC.094
Command line option
--silicon-bug=cpu-tc094
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction between an IP jump and
CSA list instruction.
The assembler issues a warning when an IP jump is followed by a CSA list instruction.
822
CPU Problem Bypasses and Checks
CPU_TC.095
Command line option
--silicon-bug=cpu-tc095
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction between any
SAT.B/SAT.H
instruction and a following load-store instruction with a
DGPR
source operand ( addsc.a
, addsc.at
, mov.a
, mtcr
).
The assembler issues a warning when a
SAT.B/SAT.H
instruction is immediately followed by a load-store instruction with a
DGPR
source operand ( addsc.a
, addsc.at
, mov.a
, mtcr
).
823
TASKING VX-toolset for TriCore User Guide
CPU_TC.096
Command line option
--silicon-bug=cpu-tc096
Description
To bypass this CPU functional problem, the C compiler inserts two
NOP
instructions for a single group loop, between an IP instruction and a loop instruction targeting the IP instruction. One
NOP
is inserted between a LS and a loop instruction, when the single group loop exists of an optional IP instruction, a single LS instruction and a loop instruction targeting the first instruction.
The assembler issues a warning in the following situations: label:
loop Ax,label label:
<any instruction>
loop Ax,label label:
<any IP-instruction>
<any LS-instruction or NOP>
loop Ax,label
824
CPU Problem Bypasses and Checks
CPU_TC.103
Command line option
--silicon-bug=cpu-tc103
Description
To bypass this CPU functional problem, the C compiler directs certain program flow instructions, such as
RET, RFE, CALL and JI, running in spram (scratch pad ram) via a stub located in safe memory. In order to be able to tell the C compiler that certain code is predetermined for spram, the pragma spram
and option --spram are introduced.
To bypass this CPU functional problem, the preprocessor define
__CPU_TC103__
is used in the tc*.lsl
linker script files. The linker will collect the stubs as generated by the C compiler and locate them in safe non-spram memory. Furthermore it is tested if (the start of) the interrupt and trap table are located at safe addresses.
Safe non-SPRAM addresses are defined as any address except: bit [15:14] = 11b (TC1130, TC1115, TC1110 PMEM) bit [14:13] = 11b (TC1762, TC1764, TC1766 PMEM)
825
TASKING VX-toolset for TriCore User Guide
CPU_TC.104
Command line option
--silicon-bug=cpu-tc104
Description
To bypass this CPU functional problem, the C compiler inserts a
NOP
instruction before a double-word load instruction using circular addressing mode (
LD.D
instruction).
The assembler issues a warning when a double-word load instruction using circular addressing mode
(
LD.D
instruction) is not preceded by a
NOP
instruction.
826
CPU Problem Bypasses and Checks
DMU_TC.001
Command line option
--silicon-bug=dmu-tc001
Description
To bypass this CPU functional problem, the C compiler avoids generation of the
ST.T
,
SWAP
and
LDMST instructions. For direct
__bit
and bit-field operations, alternative instructions are used.
The assembler issues a warning for
SWAP
,
LDMST
and
ST.T
instructions.
827
TASKING VX-toolset for TriCore User Guide
PMI_TC.003
Command line option
--silicon-bug=pmi-tc003
Description
There is no C compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to set the
TLB-A and TLB-B mappings to a page size of 16 kB. The SZA and SZB in the MMU_CON are set to 16 kB.
828
CPU Problem Bypasses and Checks
PMU_TC.004
Command line option
--silicon-bug=pmu-tc004
Description
There is no C compiler bypass for this problem.
To bypass this CPU functional problem, the assembler adds a macro to the C startup code to disable the split mode on the LMB bus. The SPLT bit of the SFR register LFI_CON is set to zero.
829
TASKING VX-toolset for TriCore User Guide
830
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