Triple-Speed Ethernet MegaCore Function User Guide

Functional Description

2015.06.15

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The Triple-Speed Ethernet MegaCore function includes the following functions:

• 10/100/1000 Ethernet MAC

• 1000BASE-X/SGMII PCS With Optional Embedded PMA

• Altera IEEE 1588v2

10/100/1000 Ethernet MAC

The Altera 10/100/1000 Ethernet MAC function handles the flow of data between user applications and

Ethernet network through an internal or external Ethernet PHY. Altera offers the following MAC variations:

• Variations with internal FIFO buffers—supports only single port.

• Variations without internal FIFO buffers—supports up to 24 ports and the ports can operate at different speeds.

• Small MAC—provides basic functionalities of a MAC function using minimal resources.

Refer to

10/100/1000 Ethernet MAC Versus Small MAC

on page 1-3 for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.

The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames. For more information about these frame formats, refer to

Ethernet Frame Format

on

page 12-1.

4

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

4-2

MAC Architecture

MAC Architecture

Figure 4-1: 10/100/1000 Ethernet MAC With Internal FIFO Buffers

System Side

10/100/1000 Ethernet MAC with Internal FIFO Buffers

Receiver Control

MAC Receive

Interface

(Avalon-ST)

CRC Check Frame

Termination

MAC Transmit

Interface

(Avalon-ST)

Transmitter Control

CRC

Generation

Pause

Generation

Ethernet Side

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Magic Packet

Detection

Configuration and

Statistics

Control Interface

(Avalon-MM)

MDIO Master

The FIFO buffers, which you can configure to 8- or 32-bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon-ST receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full

and tx_section_full

registers.

Altera Corporation


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Figure 4-2: Multiport MAC Without Internal FIFO Buffers

System Side

(Avalon-ST)

Port 0

Multiport MAC (Without Internal FIFO Buffers) Ethernet Side

Receiver Control

Loopback

(MII/GMII/RGMII)

CRC Check

Transmit / Receive

Interfaces

Transmitter Control

CRC Generation

MAC Interfaces

4-3

To/From

External PHY

Transmit / Receive

Interfaces

Port n

Receiver Control

CRC Check

Transmitter Control

CRC Generation

Loopback

To/From

External PHY

MDIO Master

Avalon-MM Interface

In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon-ST Multi-Channel Shared Memory FIFO core in Qsys to store the transmit and receive data.

Related Information

MAC Configuration Register Space

on page 6-1

MAC Interfaces

The MAC function implements the following interfaces:


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MAC Transmit Datapath

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• Avalon-ST on the system side.

• Avalon-ST sink port on transmit with the following properties:

• Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.

• Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.

• Error reporting.

• Variable-length ready latency specified by the tx_almost_full

register.

• Avalon-ST source port on receive with the following properties:

• Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.

• Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.

• Packet support using SOP and EOP signals, and partial final packet signals.

• Error reporting.

• Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.

• Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the

Interface option on the Core Configuration page or the

ETH_SPEED

bit in the command_config register.

• Control interface—an Avalon-MM slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest

to stall the interconnect fabric for as many cycles as required.

• PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard

Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

• FIFO status interface—an Avalon-ST sink port that streams in the fill level of an external FIFO buffer.

Only MAC variations without internal buffers implement this interface.

• Packet classification interface—an Avalon-ST source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.


•

Transmit Thresholds

on page 4-16

•

Interface Signals

on page 7-1

•


on page 6-1

•

Avalon Interface Specifications

More information about the Avalon interfaces.

MAC Transmit Datapath

On the transmit path, the MAC function accepts frames from a user application and constructs Ethernet frames before forwarding them to the PHY. Depending on the MAC configuration, the MAC function could perform the following tasks: realigns the payload, modifies the source address, calculates and appends the CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC



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IP Payload Re-alignment

4-5

function also detects collision and attempts to retransmit frames when a collision occurs. The following conditions trigger transmission:

• In MAC variations with internal FIFO buffers:

• Cut-through mode—transmission starts when the level of the FIFO level hits the transmit sectionfull threshold.

• Store and forward mode—transmission starts when a full packet is received.

• In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the

Avalon-ST transmit interface.


Ethernet Frame Format

on page 12-1

IP Payload Re-alignment

If you turn the Align packet headers to 32-bit boundaries option, the MAC function removes the additional two bytes from the beginning of Ethernet frames.


IP Payload Alignment

on page 4-11

Address Insertion

By default, the MAC function retains the source address received from the user application. You can configure the MAC function to replace the source address with the primary MAC address or any of the supplementary addresses by setting the

TX_ADDR_INS

bit in the command_config

register to 1. The

TX_ADDR_SEL

bits in the command_config

register determines the address selection.


Command_Config Register (Dword Offset 0x02)

on page 6-7

Frame Payload Padding

The MAC function inserts padding bytes (

0x00

) when the payload length does not meet the minimum length required:

• 46 bytes for basic frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

CRC-32 Generation

To turn on CRC-32 generation, you must set the

OMIT_CRC

bit in the tx_cmd_stat

register to 0 and send the frame to the MAC function with the ff_tx_crc_fwd

signal deasserted.

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X

32

+X

26

+X

23

+X

22

+X

16

+X

12

+X

11

+X

10

+X

8

+X

7

+X

5

+X

4

+X

2

+X

1

+1

The 32-bit CRC value occupies the FCS field with

X

31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order:

X

31,

X

30,...,

X

1,

X

0.

Interpacket Gap Insertion

In full-duplex mode, the MAC function maintains the minimum number of IPG configured in the tx_ipg_length

register between transmissions. You can configure the minimum IPG to any value



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Collision Detection in Half-Duplex Mode

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between 64 and 216 bit times, where 64 bit times is the time it takes to transmit 64 bits of raw data on the medium.

In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs

signal is deasserted.


Collision occurs only in a half-duplex network. It occurs when two or more nodes transmit concurrently.

The PHY device asserts the m_rx_col

signal to indicate collision.

When the MAC function detects collision during transmission, it stops the transmission and sends a 32bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern to be identical to the CRC is very low, 0.532%.

If the MAC function detects collision while transmitting the preamble or SFD field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of 96-bit fragment.

If the MAC function detects collision while transmitting the first 64 bytes, including the preamble and

SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudorandom process, truncated binary exponential backoff.

Figure 4-3: Frame Retransmission

MAC Transmit

LFSR

Backoff

Period

Col

PHY Control

Retransmission Block

Rd_en

Buffer

Control

WAddr

64x8

Buffer

RAddr

Frame

Discard

Avalon-ST

Interface

MAC Transmit

Datapath

PHY Interface



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MAC Receive Datapath

4-7

The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of the delay slot times, before the Nth retransmission attempt, is chosen as a uniformly distributed random integer in the following range:

0

≤

r < 2 k k = min(n, N),

where n is the number of retransmissions and N = 10.

For example, after the first collision, the backoff period, in slot time, is 0 or 1. If a collision occurs during the first retransmission, the backoff period, in slot time, is 0, 1, 2, or 3.

The maximum backoff time, in 512 bit times slots, is limited by N set to 10 as specified in the IEEE

Standard 802.3.

If collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the

EXCESS_COL


register to 1, and discards the current frame from the transmit FIFO buffer.

In networks that violate standard requirements, collision may occur after the transmission of the first 64 bytes. If this happens, the MAC function stops transmitting the current frame, discards the rest of the frame from the transmit FIFO buffer, and resumes transmitting the next available frame. You can check the

LATE_COL

register ( command_config [12]

) to verify if the MAC has discarded any frame due to collision.

MAC Receive Datapath

The MAC function receives Ethernet frames from the network via a PHY and forwards the payload with relevant frame fields to the user application after performing checks, filtering invalid frames, and removing the preamble and SFD.

Preamble Processing

The MAC function uses the SFD (

0xD5

) to identify the last byte of the preamble. If an SFD is not found after the seventh byte, the MAC function rejects the frame and discards it.

The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.

The MAC function removes the preamble and SFD fields from valid frames.


In half-duplex mode, the MAC function checks for collisions during frame reception. When collision is detected during the reception of the first 64 bytes, the MAC function discards the frame if the

RX_ERR_DISC

bit is set to 1. Otherwise, the MAC function forwards the frame to the user application with error.

Address Checking

The MAC function can accept frames with the following address types:


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Unicast Address Checking

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• Unicast address—bit 0 of the destination address is 0.

• Multicast address—bit 0 of the destination address is 1.

• Broadcast address—all 48 bits of the destination address are 1.

The MAC function always accepts broadcast frames. If promiscuous mode is enabled (

PROMIS_EN


register = 1), the MAC function omits address filtering and accepts all frames.

Unicast Address Checking

When promiscuous mode is disabled, the MAC function only accepts unicast frames if the destination address matches any of the following addresses:

• The primary address, configured in the registers mac_0

and mac_1

• The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1

, smac_1_0/ smac_1_1

, smac_2_0/smac_2_1

and smac_3_0/smac_3_1

Otherwise, the MAC function discards the frame.

Multicast Address Resolution

You can use either a software program running on the host processor or a hardware multicast address resolution engine to resolve multicast addresses. Address resolution using a software program can affect the system performance, especially in gigabit mode.

The MAC function uses a 64-entry hash table in the register space, multicast hash table, to implement the hardware multicast address resolution engine as shown in figure below. The host processor must build the hash table according to the specified algorithm. A 6-bit code is generated from each multicast address by

XOR ing the address bits as shown in table below. This code represents the address of an entry in the hash table. Write one to the most significant bit in the table entry. All multicast addresses that hash to the address of this entry are valid and accepted.

You can choose to generate the 6-bit code from all 48 bits of the destination address by setting the

MHASH_SEL


register to 0, or from the lower 24 bits by setting the

MHASH_SEL

bit to 1. The latter option is provided if you want to omit the manufacturer's code, which typically resides in the upper 24 bits of the destination address, when generating the 6-bit code.

Figure 4-4: Hardware Multicast Address Resolution Engine

multicast_match dout

Look-Up Table

(64x1 DPRAM) din read_addr(5:0) write_port



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Table 4-1: Hash Code Generation—Full Destination Address

Frame Type Validation

Algorithm for generating the 6-bit code from the entire destination address.

Hash Code Bit

2

3

4

5

0

1 xor xor xor

Value

multicast MAC address bits 7:0


multicast MAC address bits 23:16 xor




Table 4-2: Hash Code Generation—Lower 24 Bits of Destination Address

Algorithm for generating the 6-bit code from the lower 24 bits of the destination address.

Hash Code Bit Value

2

3

0

1

4

5 xor xor xor xor xor xor







4-9

The MAC function checks each multicast address received against the hash table, which serves as a fast matching engine, and a match is returned within one clock cycle. If there is no match, the MAC function discards the frame.

All multicast frames are accepted if all entries in the hash table are one.

Frame Type Validation

The MAC function checks the length/type field to determine the frame type:


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Payload Pad Removal

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• Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.

• Length/type >= 0x600—the field represents the frame type.

• Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to check the frame and payload lengths, and asserts the following signals:

• for VLAN frames, rx_err_stat[16]

in MAC variations with internal FIFO buffers or pkt_class_data[1]

in MAC variations without internal FIFO buffers

• for stacked VLAN frames, rx_err_stat

[17] in MAC variations with internal FIFO buffers or pkt_class_data[0]

in MAC variations without internal FIFO buffers.

• Length/type = 0x8088—control frames. The next two bytes, the Opcode field, indicate the type of control frame.

• For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the

PAUSE_FWD


register is set to 1.

• For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the

CNTL_FRM_ENA



• For other field values, the MAC function forwards the receive frame to the user application.


Remote Device Congestion

on page 4-18

Payload Pad Removal

You can turn on padding removal by setting the

PAD_EN


register to 1. The

MAC function removes the padding, prior to forwarding the frames to the user application, when the payload length is less than the following values for the different frame types:

• 46 bytes for basic MAC frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

When padding removal is turned off, complete frames including the padding are forwarded to the

Avalon-ST receive interface.

CRC Checking

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X

32

+X

26

+X

23

+X

22

+X

16

+X

12

+X

11

+X

10

+X

8

+X

7

+X

5

+X

4

+X

2

+X

1

+1

The 32-bit CRC value occupies the FCS field with

X

31 in the least significant bit of the first byte. The CRC bits are thus received in the following order:

X

31,

X

30,...,

X

1,

X

0.

If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:

• rx_err[2]

in MAC variations with internal FIFO buffers.

• data_rx_error[1]

in MAC variations without internal FIFO buffers.

The MAC function discards frames with CRC-32 error if the

RX_ERR_DISC

bit in the command_config register is set to 1.



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Length Checking

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The MAC function forwards the CRC-32 field to the user application if the

CRC_FWD

and

PAD_EN


register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.

Length Checking

The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged frames.

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

• Basic frames—the value specified in the frm_length

register

• VLAN tagged frames—the value specified in the frm_length

register plus four

• Stacked VLAN tagged frames—the value specified in the frm_length

register plus eight

To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.

For frames of a valid length, the MAC function continues to check the payload length if the

NO_LGTH_CHECK


register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:

• The actual payload length matches the value in the length/type or client length/type field.

• Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.

• VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.

• Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding

1536.

If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:

• rx_err[1]

in MACs with internal FIFO buffers.

• data_rx_error[0]

in MACs without internal FIFO buffers.

Frame Writing

The MegaCore function removes the preamble and SFD fields from the frame. The CRC field and padding bytes may be removed depending on the configuration.

For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive

FIFO buffers.For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon-ST receive interface.

MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.

IP Payload Alignment

The network stack makes frequent use of the IP addresses stored in Ethernet frames. When you turn on the Align packet headers to 32-bit boundaries option, the MAC function aligns the IP payload on a 32-


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MAC Transmit and Receive Latencies

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bit boundary by adding two bytes to the beginning of Ethernet frames. The padding of Ethernet frames are determined by the registers tx_cmd_stat

and rx_cmd_stat

on transmit and receive, respectively.

Table 4-3: 32-Bit Interface Data Structure — Non-IP Aligned Ethernet Frame

31...24

Byte 0

Byte 4

23...16

Byte 1

Byte 5

Bits

15...8

Byte 2

Byte 6

Table 4-4: 32-Bit Interface Data Structure — IP Aligned Ethernet Frame

7...0

Byte 3

Byte 7

31...24

padded with zeros

Byte 2

23...16

Byte 3

Bits

15...8

Byte 0

Byte 4

7...0

Byte 1

Byte 5

MAC Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies:

• Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon-ST interface.

• Receive latency is the number of clock cycles the MAC function takes to present the first bit on the

Avalon-ST interface after the bit was received on the network-side interface (MII/GMII/RGMII).

Table 4-5: Transmit and Receive Nominal Latency

The transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies.

Latency (Clock Cycles) (1)

MAC Configuration

Transmit Receive

MAC with Internal FIFO Buffers

(2)

GMII in cut-through mode

MII in cut-through mode

RGMII in gigabit and cut-through mode

RGMII in 10/100 Mbps and cut-through mode

MAC without Internal FIFO Buffers

(3)

GMII

MII

RGMII in gigabit mode

RGMII in10/100 Mbps

32

41

33

42

11

22

12

23

110

218

113

221

37

77

40

80



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MAC Configuration

Notes to

Table 4-5

:

1. The clocks in all domains are running at the same frequency.

2. The data width is set to 32 bits.

3. The data width is set to 8 bits.

FIFO Buffer Thresholds

4-13

Latency (Clock Cycles) (1)

Transmit Receive


Base Configuration Registers (Dword Offset 0x00 – 0x17)

on page 6-3

FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and manage potential FIFO buffer overflow or underflow by configuring the following thresholds:

• Almost empty

• Almost full

• Section empty

• Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.


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Receive Thresholds


Figure 4-5: Receive FIFO Thresholds

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Network

The remaining unwritten entries in the FIFO buffer before it is full.

The remaining unread entries in the FIFO buffer before it is empty.

Almost full

Frame Buffer n

Frame Buffer n - 1

Almost empty

Frame Buffer k

Frame Buffer 2

Frame Buffer 1

Section Empty

Section full entries in the FIFO buffer for the user application to start reading from it.

An early indication that the FIFO buffer is getting full.

Switch Fabric

Table 4-6: Receive Thresholds

Threshold

Almost empty

Register Name

rx_almost_empty

Description

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_rx_a_empty signal. The MAC function stops reading from the FIFO buffer and subsequently stops transferring data to the user application to avoid buffer underflow.

When the MAC function detects an EOP, it transfers all data to the user application even if the number of unread entries is below this threshold.



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Threshold

Almost full

Register Name

rx_almost_full

Section empty rx_section_empty


4-15

Description

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the

MAC function asserts the ff_rx_a_full signal. If the user application is not ready to receive data ( ff_rx_rdy

= 0), the MAC function performs the following operations:

• Stops writing data to the FIFO buffer.

• Truncates received frames to avoid FIFO buffer overflow.

• Asserts the rx_err[0]

signal when the ff_ rx_eop

signal is asserted.

• Marks the truncated frame invalid by setting the rx_err[3]

signal to 1.

If the

RX_ERR_DISC

bit in the command_config register is set to 1 and the section-full ( rx_ section_full

) threshold is set to 0, the MAC function discards frames with error received on the Avalon-ST interface.

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer hits this threshold, the MAC function generates an XOFF pause frame to indicate

FIFO congestion to the remote Ethernet device. When the FIFO level goes below this threshold, the MAC function generates an

XON pause frame to indicate its readiness to receive new frames.

To avoid data loss, you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost-full threshold. The MAC function truncates receive frames when the buffer level hits the almost-full threshold.


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Threshold

Section full

Register Name

rx_section_full

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Description

The section-full threshold indicates that there are sufficient entries in the FIFO buffer for the user application to start reading from it. The

MAC function asserts the ff_rx_dsav

signal when the buffer level hits this threshold.

Set this threshold to 0 to enable store and forward on the receive datapath. In the store and forward mode, the ff_rx_dsav

signal remains deasserted. The MAC function asserts the ff_rx_dval

signal as soon as a complete frame is written to the FIFO buffer.


Figure 4-6: Transmit FIFO Thresholds

Switch Fabric

The remaining unwritten entries in the FIFO buffer before it is full.

The remaining unread entries in the FIFO buffer before it is empty.

Almost full

Frame Buffer n

Frame Buffer n - 1

Almost empty

Frame Buffer k

Frame Buffer 2

Frame Buffer 1

Section Empty

Section full entries in the FIFO buffer for the transmitter to start transmission.

An early indication that the FIFO buffer is getting full.

Network



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Table 4-7: Transmit Thresholds

Threshold

Almost empty

Register Name

tx_almost_empty

Almost full

Section empty

Section full tx_almost_full tx_section_empty tx_section_full

Transmit FIFO Buffer Underflow

4-17

Description

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_empty signal. The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII / MII/ RGMII error to avoid FIFO underflow.

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the

MAC function asserts the ff_tx_a_full signal. The MAC function deasserts the ff_ tx_rdy

signal to backpressure the Avalon-ST transmit interface.

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer reaches this threshold, the MAC function deasserts the ff_tx_septy

signal. This threshold can serve as a warning about potential FIFO buffer congestion.

This threshold indicates that there are sufficient entries in the FIFO buffer to start frame transmission.

Set this threshold to 0 to enable store and forward on the transmit path. When you enable the store and forward mode, the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer.

Transmit FIFO Buffer Underflow

If the transmit FIFO buffer hits the almost-empty threshold during transmission and the FIFO buffer does not contain the end-of-packet indication, the MAC function stops reading data from the FIFO buffer and initiates the following actions:

1. The MAC function asserts the RGMII/GMII/MII error signals ( tx_control

/ gm_tx_err

/ m_tx_err

) to indicate that the fragment transferred is not valid.

2. The MAC function deasserts the RGMII/GMII/MII transmit enable signals ( tx_control

/ gm_tx_en

/ m_tx_en

) to terminate the frame transmission.

3. After the underflow, the user application completes the frame transmission.

4. The transmitter control discards any new data in the FIFO buffer until the end of frame is reached.

5. The MAC function starts to transfer data on the RGMII/GMII/MII when the user application sends a new frame with an SOP.


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4-18

Congestion and Flow Control

Figure 4-7: Transmit FIFO Buffer Underflow

Figure illustrates the FIFO buffer underflow protection algorithm for gigabit Ethernet system.

Transmit FIFO ff_tx_data valid

[3] [4] valid ff_tx_sop ff_tx_eop ff_tx_rdy ff_tx_wren ff_tx_crc_fwd ff_tx_err ff_tx_septy ff_tx_uflow ff_tx_a_full ff_tx_a_empty

GMII Transmit gm_tx_en gm_tx_d gm_tx_err valid valid

[1] [2]

[5]

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Congestion and Flow Control

In full-duplex mode, the MAC function implements flow control to manage the following types of congestion:

• Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.

• Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.

• Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.



on page 6-1

Remote Device Congestion

When the MAC function receives an XOFF pause frame and the

PAUSE_IGNORE


register is set to 0, the MAC function completes the transfer of the current frame and stops transmission for the amount of time specified by the pause quanta in 512 bit times increments.

Transmission resumes when the timer expires or when the MAC function receives an XON frame.

You can configure the MAC function to ignore pause frames by setting the

PAUSE_IGNORE





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Receive FIFO Buffer and Local Device Congestion

4-19

Receive FIFO Buffer and Local Device Congestion

Pause frames generated are compliant to the IEEE Standard 802.3 annex 31A & B. The MAC function generates pause frames when the level of the receive FIFO buffer hits a level that can potentially cause an overflow, or at the request of the user application. The user application can trigger the generation of an

XOFF pause frame by setting the

XOFF_GEN


register to 1 or asserting the xoff_gen

signal.

For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold ( rx_section_empty

). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame.

The fill level of an external FIFO buffer is obtained via the Avalon-ST receive FIFO status interface.

When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant

register. The source address is set to the primary MAC address configured in the mac_0

and mac_1

registers, and the destination address is set to a fixed multicast address, 01-80-

C2-00-00-01 (0x010000c28001).

The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the

XOFF_GEN

bit and signal, and subsequently setting the

XON_GEN

bit to 1 or asserting the

XON_GEN

signal.

When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and

P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0

and mac_1

registers and the destination address is set to a fixed multicast address, 01-80-

C2-00-00-01 (0x010000c28001).

In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3]

, is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the

RX_ERR_DISC


register to 1.

Magic Packets

A magic packet can be a unicast, multicast, or broadcast packet which carries a defined sequence in the payload section. Magic packets are received and acted upon only under specific conditions, typically in power-down mode.

The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.

The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.

Sleep Mode

You can only put a node to sleep (set

SLEEP


register to 1 and deassert the magic_sleep_n

signal) if magic packet detection is enabled (set the

MAGIC_ENA

bit in the command_config register to 1).

Altera recommends that you do not put a node to sleep if you disable magic packet detection.

Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts

and etherStatsOctets

count the traffic statistics.


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4-20

Magic Packet Detection

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Magic Packet Detection

Magic packet detection wakes up a node that was put to sleep. The MAC function detects magic packets with any of the following destination addresses:

• Any multicast address

• A broadcast address

• The primary MAC address configured in the mac_0

and mac_1

registers

• Any of the supplementary MAC addresses configured in the following registers if they are enabled: smac_0_0

, smac_0_1

, smac_1_0

, smac_1_1

, smac_2_0

, smac_2_1

, smac_3_0

and smac_3_1

When the MAC function detects a magic packet, the

WAKEUP


register is set to 1, and the etherStatsPkts

and etherStatsOctets

statistics registers are incremented.

Magic packet detection is disabled when the

SLEEP


register is set to 0. Setting the

SLEEP

bit to 0 also resets the

WAKEUP

bit to 0 and resumes the transmit and receive operations.

MAC Local Loopback

You can enable local loopback on the MII/GMII/RGMII of the MAC function to exercise the transmit and receive paths. If you enable local loopback, use the same clock source for both the transmit and receive clocks. If you use different clock sources, ensure that the difference between the transmit and receive clocks is less than ±100 ppm.

To enable local loopback:

1. Initiate software reset by setting the

SW_RESET

bit in command_config

register to 1.

Software reset disables the transmit and receive operations, flushes the internal FIFOs, and clears the statistics counters. The

SW_RESET

bit is automatically cleared upon completion.

2. When software reset is complete, enable local loopback on the MAC's MII/GMII/RGMII by setting the

LOOP_ENA


register to 1.

3. Enable transmit and receive operations by setting the

TX_ENA

and

RX_ENA

bits in command_config register to 1.

4. Initiate frame transmission.

5. Compare the statistics counters aFramesTransmittedOK

and aFramesReceivedOK

to verify that the transmit and receive frame counts are equal.

6. Check the statistics counters ifInErrors and ifOutErrors

to determine the number of packets transmitted and received with errors.

7. To disable loopback, initiate a software reset and set the

LOOP_ENA


register to 0.

MAC Error Correction Code

The error correction code feature is implemented to the memory instances in the MegaCore function.

This feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.

Note: This feature is only applicable for Stratix V and Arria 10 devices.



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Table 4-8: Core Variation and ECC Protection Support

Core Variation

10/100/1000 Mb Ethernet MAC

10/100/1000 Mb Ethernet MAC with

1000BASE-X/SGMII PCS

1000BASE-X/SGMII PCS only

1000 Mb Small MAC

10/100 Mb Small MAC

ECC Protection Support

Protects the following options: transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)



Statistic counters (if enabled)

Multicast hashtable (if enabled)

SGMII bridge (if enabled)

Protects the SGMII bridge (if enabled)

Protects the transmit and receive FIFO buffer



MAC Reset

4-21

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the

MegaCore function.

• Single channel core configuration— eccstatus[1:0]

output ports.

• Multi-channel core configuration— eccstatus_<n>[1:0]

output ports, where eccstatus_0[1:0]

is for channel 0, eccstatus_1[1:0] for channel 1, and so on.

MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the

MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the

TX_ENA

and

RX_ENA


register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

• To trigger a hardware reset, assert the reset

signal.

• To trigger a software reset, set the

SW_RESET


register to 1. The

SW_RESET

bit is cleared automatically when the software reset ends.


Send Feedback


4-22

PHY Management (MDIO)

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Altera recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 4-8: Software Reset Sequence

START

(SW_RESET = 1)

Frame

Reception

Completed?

No

Yes

Receive Frames

Frame

Transmission

Completed?

No

Yes

Transmit Frames

MAC with internal FIFO?

Yes

Receive

FIFO empty?

No

No

Yes

Flush FIFO

Statistics

Counters

Enabled?

Yes

No

END

(SW_RESET = 0)

Note: If the

SW_RESET

bit is 1 when the line clocks are not available (for example, cable is disconnected), the statistics registers may not be cleared. The read_timeout

register is then set to 1 to indicate that the statistics registers were not cleared.

PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the

PHY device management registers, and supports up to 32 PHY devices.

To access each PHY device, write the PHY address to the MDIO register ( mdio_addr0

/

1

) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require



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MDIO Connection

4-23

writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon-MM interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

For more information about the MDIO registers, refer to


on page 6-

1.

MDIO Connection

Figure 4-9: MDIO Interface

addr mdc mdio addr mdc mdio

mdc mdio_in mdio_out mdio_oen

10/100/1000 Ethernet MAC

Avalon-MM Control

Interface

MDIO Frame Format

The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64 bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data.

Each bit is transferred on the rising edge of the MDIO clock, mdc

.


Send Feedback


4-24

Connecting MAC to External PHYs

Table 4-9: MDIO Frame Formats (Read/Write)

Field settings for MDIO transactions.

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Type PRE

Read 1 ... 1

Write 1 ... 1

ST

MSB LSB

01

01

OP

MSB LSB

10

01

Addr1

MSB LSB

xxxxx xxxxx

Command

Addr2

MSB LSB

xxxxx xxxxx

TA Data

MSB LSB

Z0 xxxxxxxxxxxxxxxx

10 xxxxxxxxxxxxxxxx

Idle

Table 4-10: MDIO Frame Field Descriptions

PRE

ST

OP

Addr1

Addr2

TA

Data

Idle

Name Description

Preamble. 32 bits of logical 1 sent prior to every transaction.

Start indication. Standard MDIO (Clause 22): 0b01.

Opcode. Defines the transaction type.

The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the mdio_addr0 register. For PHY device 1, the Addr1 field is set to the value configured in the mdio_addr1

register.

Register Address. Each PHY can have up to 32 registers.

Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2 nd turnaround phase.

bit of the

16-bit data written to or read from the PHY device.

Between frames, the MDIO data signal is tri-stated.

Z

Z

Connecting MAC to External PHYs

The MAC function implements a flexible network interface—MII for 10/100-Mbps interfaces, RGMII or

GMII for 1000-Mbps interfaces—that you can use in multiple applications. This section provides the guidelines for implementing the following network applications:

• Gigabit Ethernet operation

• Programmable 10/100 Ethernet operation

• Programmable 10/100/1000 Ethernet operation

Gigabit Ethernet

You can connect gigabit Ethernet PHYs to the MAC function via GMII or RGMII. On the receive path, connect the 125-MHz clock provided by the PHY device to the MAC clock, rx_clk

. On transmit, drive a

125-MHz clock to the PHY GMII or RGMII. Connect a 125-MHz clock source to the MAC transmit clock, tx_clk

.



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Programmable 10/100 Ethernet

4-25

A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.

Figure 4-10: Gigabit PHY to MAC via GMII

Altera FPGA

clk_in/xtali gtx_clk tx_en

Gigabit

PHY

Vcc m_tx_en m_tx_err eth_mode set_1000 set_10

10/100/1000

Ethernet

MAC

rx_clk rxd(7:0)

Programmable 10/100 Ethernet

Connect 10/100 Ethernet PHYs to the MAC function via MII. On the receive path, connect the 25-MHz

(100 Mbps) or 2.5-MHz (10 Mbps) clock provided by the PHY device to the MAC clock, rx_clk

. On the transmit path, connect the 25 MHz (100 Mbps) or a 2.5 MHz (10 Mbps) clock provided by the PHY to the

MAC clock, tx_clk

.


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4-26

Programmable 10/100/1000 Ethernet Operation

Figure 4-11: 10/100 PHY Interface

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2015.06.15

clk_in/xtali tx_clk txd(3:0) tx_en tx_err

10/100

PHY

rx_clk rxd(3:0) rx_err m_rx_col m_rx_crs

Altera FPGA

tx_clk m_tx_d(3:0) m_tx_en m_tx_err gm_tx_d(7:0) gm_tx_en gm_tx_err ena_10 eth_mode set_10 set_1000 gm_rx_d(7:0) gm_rx_dv gm_rx_err rx_clk m_rx_d(3:0) m_rx_en m_rx_err

10/100/1000

Ethernet

MAC


Typically, 10/100/1000 Ethernet PHY devices implement a shared interface that you connect to a 10/100-

Mbps MAC via MII/RGMII or to a gigabit MAC via GMII/RGMII.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the

MAC clock, rx_clk

. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz

(10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode

selects either MII or GMII. The MAC function asserts the eth_mode

signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode

signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.



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Figure 4-12: 10/100/1000 PHY Interface via MII/GMII


Altera FPGA

25MHz

Osc clk_in/xtali tx_clk gtx_clk txd(7:0)

25MHz

25/2.5 MHz x5

10/100/1000

PHY

Optional tie to 0

if not used rx_clk

125/25/2.5 MHz rxd(7:0) rx_err

Unused tx_clk m_tx_d(3:0) m_tx_en m_tx_err gm_tx_d(7:0) gm_tx_en gm_tx_err eth_mode set_1000 set_10 en_10

10/100/1000

Ethernet

MAC

m_rx_d(3:0) m_rx_err gm_rx_d(7:0) gm_rx_dv gm_rx_err

4-27

Figure 4-13: 10/100/1000 PHY Interface via RGMII

clk_in/xtali

10/100/1000

PHY

gtx_clk tx_en txd[3:0]

Optional tie to 0

if not used


Send Feedback

rx_clk rx_dv rxd[3:0]

Altera FPGA

ena_10 eth_mode tx_clk tx_control rgmii_out[3:0] set_1000 set_10

10/100/1000

Ethernet

MAC

rx_control rgmii_in[3:0]


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