Triple-Speed Ethernet MegaCore Function User Guide

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Triple-Speed Ethernet MegaCore Function User Guide | Manualzz

11-10 tse_mac_setMIImode()

Details

See also:

tse_mac_setMIImode()

tse_mac_setMIImode()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

See also:

Details

int tse_mac_setMIImode(np_tse_mac *pmac)

No

No

<

triple_speed_ethernet_iniche.h

>

The tse_mac_setMIImode()

function sets the MAC function operation mode to MII (10/100). The settings of the command_config

register are restored at the end of the function.

pmac

—A pointer to the MAC control interface base address.

SUCCESS tse_mac_setGMIImode()

tse_mac_SwReset()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

Details

int tse_mac_SwReset(np_tse_mac *pmac)

No

No

<

triple_speed_ethernet_iniche.h

>

The tse_mac_SwReset()

performs a software reset on the MAC function. A software reset occurs with some latency as specified by

ALTERA_TSE_SW_

RESET_TIME_OUT_CNT

. The settings of the command_config

register are restored at the end of the function.

pmac

—A pointer to the MAC control interface base address.

SUCCESS

UG-01008

2015.06.15

Constants

Table 11-3

lists all constants defined for the MAC registers manipulation and provides links to detailed

descriptions of the registers. It also list the constants that define the MAC operating mode and timeout values.

Altera Corporation

Software Programming Interface

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Table 11-3: Constants Mapping

Constants

Constant Value Description

ALTERA_TSE_DUPLEX_MODE_DEFAULT

ALTERA_TSE_MAC_SPEED_DEFAULT

ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE

ALTERA_CHECKLINK_TIMEOUT_THRESHOLD

ALTERA_AUTONEG_TIMEOUT_THRESHOLD

1

0

1

1000000

250000

0: Half-duplex

1: Full-duplex

0: 10 Mbps

1: 100 Mbps

2: 1000 Mbps

The number of SG-DMA descriptors required for the current operating mode.

The timeout value when the

MAC tries to establish a link with a PHY.

The auto-negotiation timeout value.

Command_Config Register (

Command_Config Register (Dword Offset 0x02)

on page 6-7)

ALTERA_TSEMAC_CMD_TX_ENA_OFST

0

Configures the

TX_ENA bit.

ALTERA_TSEMAC_CMD_TX_ENA_MSK

0x1

ALTERA_TSEMAC_CMD_RX_ENA_OFST

1

Configures the

RX_ENA

bit.

ALTERA_TSEMAC_CMD_RX_ENA_MSK

0x2

ALTERA_TSEMAC_CMD_XON_GEN_OFST

ALTERA_TSEMAC_CMD_XON_GEN_MSK

ALTERA_TSEMAC_CMD_ETH_SPEED_OFST

2

0x4

3

Configures the

Configures the

XON_GEN bit.

ETH_SPEED

bit.

ALTERA_TSEMAC_CMD_ETH_SPEED_MSK

ALTERA_TSEMAC_CMD_PROMIS_EN_OFST

ALTERA_TSEMAC_CMD_PROMIS_EN_MSK

ALTERA_TSEMAC_CMD_PAD_EN_OFST

0x8

4

0x10

5

Configures the

Configures the

PROMIS_EN

PAD_EN

bit.

bit.

ALTERA_TSEMAC_CMD_PAD_EN_MSK

ALTERA_TSEMAC_CMD_CRC_FWD_OFST

ALTERA_TSEMAC_CMD_CRC_FWD_MSK

ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST

0x20

6

0x40

7

Configures the

Configures the

CRC_FWD

bit.

PAUSE_FWD

bit.

ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK

ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST

ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK

0x80

8

Configures the bit.

PAUSE_IGNORE

ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST

ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK

0x100

9

0x200

Configures the bit.

TX_ADDR_INS

11-11

Software Programming Interface

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11-12

Constants

Constant

ALTERA_TSEMAC_CMD_HD_ENA_OFST

ALTERA_TSEMAC_CMD_HD_ENA_MSK

ALTERA_TSEMAC_CMD_EXCESS_COL_OFST

ALTERA_TSEMAC_CMD_EXCESS_COL_MSK

ALTERA_TSEMAC_CMD_LATE_COL_OFST

ALTERA_TSEMAC_CMD_LATE_COL_MSK

ALTERA_TSEMAC_CMD_SW_RESET_OFST

ALTERA_TSEMAC_CMD_SW_RESET_MSK

ALTERA_TSEMAC_CMD_MHASH_SEL_OFST

ALTERA_TSEMAC_CMD_MHASH_SEL_MSK

ALTERA_TSEMAC_CMD_LOOPBACK_OFST

ALTERA_TSEMAC_CMD_LOOPBACK_MSK

ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST

ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK

ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST

ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK

ALTERA_TSEMAC_CMD_SLEEP_OFST

ALTERA_TSEMAC_CMD_SLEEP_MSK

ALTERA_TSEMAC_CMD_WAKEUP_OFST

ALTERA_TSEMAC_CMD_WAKEUP_MSK

ALTERA_TSEMAC_CMD_XOFF_GEN_OFST

ALTERA_TSEMAC_CMD_XOFF_GEN_MSK

ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST

ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK

ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST

ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK

ALTERA_TSEMAC_CMD_ENA_10_OFST

ALTERA_TSEMAC_CMD_ENA_10_MSK

Value

10

0x8000

16

0x70000

19

0x80000

20

0x10000

0

21

0x400

11

0x800

12

0x1000

13

0x2000

14

0x4000

15

0x20000

0

22

0x40000

0

23

0x80000

0

24

0x10000

00

25

0x20000

00

Description

Configures the

HD_ENA

bit.

Configures the

EXCESS_COL

bit.

Configures the

LATE_COL

bit.

Configures the

SW_RESET

bit.

Configures the

MHASH_SEL

bit.

Configures the

LOOP_ENA

bit.

Configures the

TX_ADDR_SEL bits (bits 16 - 18).

Configures the

MAGIC_ENA bit.

Configures the

SLEEP

bit.

Configures the

WAKEUP

bit.

Configures the

XOFF_GEN

bit.

Configures the

CNTL_FRM_ENA bit.

Configures the

NO_LENGTH_

CHECK

bit.

Configures the

ENA_10

bit.

UG-01008

2015.06.15

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Constants

Constant Value Description

ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST

ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK

ALTERA_TSEMAC_CMD_CNT_RESET_OFST

26

0x40000

00

31

Configures the bit.

RX_ERR_DISC

ALTERA_TSEMAC_CMD_CNT_RESET_MSK

0x80000

000

Configures the

CNT_RESET

Tx_Cmd_Stat Register (

Transmit and Receive Command Registers (Dword Offset 0x3A –

0x3B)

on page 6-13)

bit.

ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST

ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK

17

0x20000

Configures the

OMIT_CRC bit.

ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST

ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK

ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST

18

0x40000

25

Configures the

TX_SHIFT16

Rx_Cmd_Stat Register (

Transmit and Receive Command Registers (Dword Offset 0x3A –

0x3B)

on page 6-13)

bit.

ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK

0x20000

00

Configures the

RX_SHIFT16

bit

11-13

Software Programming Interface

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