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11-10 tse_mac_setMIImode()
Details
See also:
tse_mac_setMIImode()
tse_mac_setMIImode()
Prototype:
Thread-safe:
Available from
ISR:
Include:
Description:
Parameter:
Return:
See also:
Details
int tse_mac_setMIImode(np_tse_mac *pmac)
No
No
<
triple_speed_ethernet_iniche.h
>
The tse_mac_setMIImode()
function sets the MAC function operation mode to MII (10/100). The settings of the command_config
register are restored at the end of the function.
pmac
—A pointer to the MAC control interface base address.
SUCCESS tse_mac_setGMIImode()
tse_mac_SwReset()
Prototype:
Thread-safe:
Available from
ISR:
Include:
Description:
Parameter:
Return:
Details
int tse_mac_SwReset(np_tse_mac *pmac)
No
No
<
triple_speed_ethernet_iniche.h
>
The tse_mac_SwReset()
performs a software reset on the MAC function. A software reset occurs with some latency as specified by
ALTERA_TSE_SW_
RESET_TIME_OUT_CNT
. The settings of the command_config
register are restored at the end of the function.
pmac
—A pointer to the MAC control interface base address.
SUCCESS
UG-01008
2015.06.15
Constants
lists all constants defined for the MAC registers manipulation and provides links to detailed
descriptions of the registers. It also list the constants that define the MAC operating mode and timeout values.
Altera Corporation
Software Programming Interface
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Table 11-3: Constants Mapping
Constants
Constant Value Description
ALTERA_TSE_DUPLEX_MODE_DEFAULT
ALTERA_TSE_MAC_SPEED_DEFAULT
ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE
ALTERA_CHECKLINK_TIMEOUT_THRESHOLD
ALTERA_AUTONEG_TIMEOUT_THRESHOLD
1
0
1
1000000
250000
0: Half-duplex
1: Full-duplex
0: 10 Mbps
1: 100 Mbps
2: 1000 Mbps
The number of SG-DMA descriptors required for the current operating mode.
The timeout value when the
MAC tries to establish a link with a PHY.
The auto-negotiation timeout value.
Command_Config Register (Dword Offset 0x02)
on page 6-7)
ALTERA_TSEMAC_CMD_TX_ENA_OFST
0
Configures the
TX_ENA bit.
ALTERA_TSEMAC_CMD_TX_ENA_MSK
0x1
ALTERA_TSEMAC_CMD_RX_ENA_OFST
1
Configures the
RX_ENA
bit.
ALTERA_TSEMAC_CMD_RX_ENA_MSK
0x2
ALTERA_TSEMAC_CMD_XON_GEN_OFST
ALTERA_TSEMAC_CMD_XON_GEN_MSK
ALTERA_TSEMAC_CMD_ETH_SPEED_OFST
2
0x4
3
Configures the
Configures the
XON_GEN bit.
ETH_SPEED
bit.
ALTERA_TSEMAC_CMD_ETH_SPEED_MSK
ALTERA_TSEMAC_CMD_PROMIS_EN_OFST
ALTERA_TSEMAC_CMD_PROMIS_EN_MSK
ALTERA_TSEMAC_CMD_PAD_EN_OFST
0x8
4
0x10
5
Configures the
Configures the
PROMIS_EN
PAD_EN
bit.
bit.
ALTERA_TSEMAC_CMD_PAD_EN_MSK
ALTERA_TSEMAC_CMD_CRC_FWD_OFST
ALTERA_TSEMAC_CMD_CRC_FWD_MSK
ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST
0x20
6
0x40
7
Configures the
Configures the
CRC_FWD
bit.
PAUSE_FWD
bit.
ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST
ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK
0x80
8
Configures the bit.
PAUSE_IGNORE
ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST
ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK
0x100
9
0x200
Configures the bit.
TX_ADDR_INS
11-11
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11-12
Constants
Constant
ALTERA_TSEMAC_CMD_HD_ENA_OFST
ALTERA_TSEMAC_CMD_HD_ENA_MSK
ALTERA_TSEMAC_CMD_EXCESS_COL_OFST
ALTERA_TSEMAC_CMD_EXCESS_COL_MSK
ALTERA_TSEMAC_CMD_LATE_COL_OFST
ALTERA_TSEMAC_CMD_LATE_COL_MSK
ALTERA_TSEMAC_CMD_SW_RESET_OFST
ALTERA_TSEMAC_CMD_SW_RESET_MSK
ALTERA_TSEMAC_CMD_MHASH_SEL_OFST
ALTERA_TSEMAC_CMD_MHASH_SEL_MSK
ALTERA_TSEMAC_CMD_LOOPBACK_OFST
ALTERA_TSEMAC_CMD_LOOPBACK_MSK
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST
ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK
ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST
ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK
ALTERA_TSEMAC_CMD_SLEEP_OFST
ALTERA_TSEMAC_CMD_SLEEP_MSK
ALTERA_TSEMAC_CMD_WAKEUP_OFST
ALTERA_TSEMAC_CMD_WAKEUP_MSK
ALTERA_TSEMAC_CMD_XOFF_GEN_OFST
ALTERA_TSEMAC_CMD_XOFF_GEN_MSK
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST
ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST
ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK
ALTERA_TSEMAC_CMD_ENA_10_OFST
ALTERA_TSEMAC_CMD_ENA_10_MSK
Value
10
0x8000
16
0x70000
19
0x80000
20
0x10000
0
21
0x400
11
0x800
12
0x1000
13
0x2000
14
0x4000
15
0x20000
0
22
0x40000
0
23
0x80000
0
24
0x10000
00
25
0x20000
00
Description
Configures the
HD_ENA
bit.
Configures the
EXCESS_COL
bit.
Configures the
LATE_COL
bit.
Configures the
SW_RESET
bit.
Configures the
MHASH_SEL
bit.
Configures the
LOOP_ENA
bit.
Configures the
TX_ADDR_SEL bits (bits 16 - 18).
Configures the
MAGIC_ENA bit.
Configures the
SLEEP
bit.
Configures the
WAKEUP
bit.
Configures the
XOFF_GEN
bit.
Configures the
CNTL_FRM_ENA bit.
Configures the
NO_LENGTH_
CHECK
bit.
Configures the
ENA_10
bit.
UG-01008
2015.06.15
Altera Corporation
Software Programming Interface
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UG-01008
2015.06.15
Constants
Constant Value Description
ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST
ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK
ALTERA_TSEMAC_CMD_CNT_RESET_OFST
26
0x40000
00
31
Configures the bit.
RX_ERR_DISC
ALTERA_TSEMAC_CMD_CNT_RESET_MSK
0x80000
000
Configures the
CNT_RESET
Transmit and Receive Command Registers (Dword Offset 0x3A –
bit.
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST
ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK
17
0x20000
Configures the
OMIT_CRC bit.
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST
ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST
18
0x40000
25
Configures the
TX_SHIFT16
Rx_Cmd_Stat Register (
Transmit and Receive Command Registers (Dword Offset 0x3A –
bit.
ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK
0x20000
00
Configures the
RX_SHIFT16
bit
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Table of contents
- 7 About This MegaCore Function
- 7 Device Family Support
- 8 Features
- 9 10/100/1000 Ethernet MAC Versus Small MAC
- 9 High-Level Block Diagrams
- 11 Example Applications
- 12 MegaCore Verification
- 13 Optical Platform
- 13 Copper Platform
- 13 Performance and Resource Utilization
- 18 Release Information
- 19 Design Walkthrough
- 19 Creating a New Quartus II Project
- 20 Generating a Design Example or Simulation Model
- 20 Simulate the System
- 20 Compiling the Triple-Speed Ethernet MegaCore Function Design
- 21 Programming an FPGA Device
- 21 Generated Files
- 22 Design Constraint File No Longer Generated
- 24 Parameter Settings
- 24 Core Configuration
- 25 Ethernet MAC Options
- 27 FIFO Options
- 28 Timestamp Options
- 28 PCS/Transceiver Options
- 31 10/100/1000 Ethernet MAC
- 32 MAC Architecture
- 33 MAC Interfaces
- 34 MAC Transmit Datapath
- 35 IP Payload Re-alignment
- 35 Address Insertion
- 35 Frame Payload Padding
- 35 CRC-32 Generation
- 35 Interpacket Gap Insertion
- 36 Collision Detection in Half-Duplex Mode
- 37 MAC Receive Datapath
- 37 Preamble Processing
- 37 Collision Detection in Half-Duplex Mode
- 37 Address Checking
- 38 Unicast Address Checking
- 38 Multicast Address Resolution
- 39 Frame Type Validation
- 40 Payload Pad Removal
- 40 CRC Checking
- 41 Length Checking
- 41 Frame Writing
- 41 IP Payload Alignment
- 42 MAC Transmit and Receive Latencies
- 43 FIFO Buffer Thresholds
- 44 Receive Thresholds
- 46 Transmit Thresholds
- 47 Transmit FIFO Buffer Underflow
- 48 Congestion and Flow Control
- 48 Remote Device Congestion
- 49 Receive FIFO Buffer and Local Device Congestion
- 49 Magic Packets
- 49 Sleep Mode
- 50 Magic Packet Detection
- 50 MAC Local Loopback
- 50 MAC Error Correction Code
- 51 MAC Reset
- 52 PHY Management (MDIO)
- 53 MDIO Connection
- 53 MDIO Frame Format
- 54 Connecting MAC to External PHYs
- 54 Gigabit Ethernet
- 55 Programmable 10/100 Ethernet
- 56 Programmable 10/100/1000 Ethernet Operation
- 58 1000BASE-X/SGMII PCS With Optional Embedded PMA
- 59 1000BASE-X/SGMII PCS Architecture
- 60 Transmit Operation
- 60 Frame Encapsulation
- 60 8b/10b Encoding
- 61 Receive Operation
- 61 Comma Detection
- 61 8b/10b Decoding
- 61 Frame De-encapsulation
- 61 Synchronization
- 61 Carrier Sense
- 62 Collision Detection
- 62 Transmit and Receive Latencies
- 62 SGMII Converter
- 62 Transmit
- 63 Receive
- 63 Auto-Negotiation
- 63 1000BASE-X Auto-Negotiation
- 64 SGMII Auto-Negotiation
- 66 Ten-bit Interface
- 67 PHY Loopback
- 68 PHY Power-Down
- 68 Power-Down in PCS Variations with Embedded PMA
- 69 1000BASE-X/SGMII PCS Reset
- 70 Altera IEEE 1588v2 Feature
- 70 IEEE 1588v2 Supported Configurations
- 71 IEEE 1588v2 Features
- 72 IEEE 1588v2 Architecture
- 72 IEEE 1588v2 Transmit Datapath
- 73 IEEE 1588v2 Receive Datapath
- 73 IEEE 1588v2 Frame Format
- 74 PTP Frame in IEEE 802.3
- 74 PTP Frame over UDP/IPv4
- 75 PTP Frame over UDP/IPv6
- 77 Software Requirements
- 78 Triple-Speed Ethernet with IEEE 1588v2 Design Example Components
- 79 Base Addresses
- 79 Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files
- 80 Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design
- 80 Triple-Speed Ethernet with IEEE 1588v2 Testbench
- 81 Triple-Speed Ethernet with IEEE 1588v2 Testbench Files
- 82 Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow
- 83 Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim Simulator
- 84 MAC Configuration Register Space
- 86 Base Configuration Registers (Dword Offset 0x00 – 0x17)
- 90 Command_Config Register (Dword Offset 0x02)
- 94 Statistics Counters (Dword Offset 0x18 – 0x38)
- 96 Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
- 98 Supplementary Address (Dword Offset 0xC0 – 0xC7)
- 99 IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
- 100 IEEE 1588v2 Feature PMA Delay
- 101 PCS Configuration Register Space
- 103 Control Register (Word Offset 0x00)
- 105 Status Register (Word Offset 0x01)
- 106 Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)
- 106 1000BASE-X
- 107 SGMII MAC Mode Auto Negotiation
- 108 SGMII PHY Mode Auto Negotiation
- 109 An_Expansion Register (Word Offset 0x06)
- 109 If_Mode Register (Word Offset 0x14)
- 110 Register Initialization
- 110 Triple-Speed Ethernet System with MII/GMII or RGMII
- 113 Triple-Speed Ethernet System with SGMII
- 114 Triple-Speed Ethernet System with 1000BASE-X Interface
- 116 Interface Signals
- 117 10/100/1000 Ethernet MAC Signals
- 117 Clock and Reset Signal
- 118 MAC Control Interface Signals
- 119 MAC Status Signals
- 119 MAC Receive Interface Signals
- 122 MAC Transmit Interface Signals
- 124 Pause and Magic Packet Signals
- 125 MII/GMII/RGMII Signals
- 126 PHY Management Signals
- 127 ECC Status Signals
- 128 10/100/1000 Multiport Ethernet MAC Signals
- 129 Multiport MAC Clock and Reset Signals
- 129 Multiport MAC Receive Interface Signals
- 130 Multiport MAC Transmit Interface Signals
- 130 Multiport MAC Packet Classification Signals
- 131 Multiport MAC FIFO Status Signals
- 133 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
- 133 TBI Interface Signals
- 134 Status LED Control Signals
- 135 SERDES Control Signals
- 135 Arria 10 Transceiver Native PHY Signals
- 136 ECC Status Signals
- 137 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
- 139 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
- 140 1.25 Gbps Serial Interface
- 140 Transceiver Native PHY Signal
- 140 SERDES Control Signals
- 142 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
- 143 IEEE 1588v2 RX Timestamp Signals
- 144 IEEE 1588v2 TX Timestamp Signals
- 146 IEEE 1588v2 TX Timestamp Request Signals
- 146 IEEE 1588v2 TX Insert Control Timestamp Signals
- 149 IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
- 150 IEEE 1588v2 PCS Phase Measurement Clock Signal
- 150 IEEE 1588v2 PHY Path Delay Interface Signals
- 151 1000BASE-X/SGMII PCS Signals
- 152 PCS Control Interface Signals
- 152 PCS Reset Signals
- 152 MII/GMII Clocks and Clock Enablers
- 153 GMII
- 153 MII
- 154 SGMII Status Signals
- 156 1000BASE-X/SGMII PCS and PMA Signals
- 157 Timing
- 157 Avalon-ST Receive Interface
- 159 Avalon-ST Transmit Interface
- 160 GMII Transmit
- 160 GMII Receive
- 160 RGMII Transmit
- 161 RGMII Receive
- 162 MII Transmit
- 162 MII Receive
- 162 IEEE 1588v2 Timestamp
- 167 Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA
- 168 MAC and PCS With GX Transceivers
- 170 MAC and PCS With LVDS Soft-CDR I/O
- 172 Sharing PLLs in Devices with LVDS Soft-CDR I/O
- 173 Sharing PLLs in Devices with GIGE PHY
- 173 Sharing Transceiver Quads
- 173 Migrating From Old to New User Interface For Existing Designs
- 173 Exposed Ports in the New User Interface
- 175 Creating Clock Constraints
- 177 Recommended Clock Frequency
- 179 Triple-Speed Ethernet Testbench Architecture
- 180 Testbench Components
- 180 Testbench Verification
- 181 Testbench Configuration
- 181 Test Flow
- 182 Simulation Model
- 182 Generate the Simulation Model
- 182 Simulate the IP Core
- 183 Simulation Model Files
- 184 Driver Architecture
- 185 Directory Structure
- 185 PHY Definition
- 187 Using Multiple SG-DMA Descriptors
- 187 Using Jumbo Frames
- 188 API Functions
- 188 alt_tse_mac_get_common_speed()
- 189 alt_tse_mac_set_common_speed()
- 189 alt_tse_phy_add_profile()
- 189 alt_tse_system_add_sys()
- 190 triple_speed_ethernet_init()
- 191 tse_mac_close()
- 192 tse_mac_raw_send()
- 192 tse_mac_setGMII mode()
- 193 tse_mac_setMIImode()
- 193 tse_mac_SwReset()
- 193 Constants
- 197 Basic Frame Format
- 198 VLAN and Stacked VLAN Frame Format
- 199 Pause Frame Format
- 200 Pause Frame Generation
- 201 Functionality Configuration Parameters
- 203 Test Configuration Parameters
- 206 ToD Clock Features
- 206 ToD Clock Device Family Support
- 206 ToD Clock Performance and Resource Utilization
- 207 ToD Clock Parameter Setting
- 208 ToD Clock Interface Signals
- 208 ToD Clock Avalon-MM Control Interface Signals
- 209 ToD Clock Avalon-ST Transmit Interface Signals
- 210 ToD Clock Configuration Register Space
- 211 Using ToD Clock SecondsH, SecondsL, and NanoSec Registers
- 211 Adjusting ToD Clock Drift
- 213 ToD Synchronizer Block
- 214 ToD Synchronizer Parameter Settings
- 215 ToD Synchronizer Signals
- 215 ToD Synchronizer Common Clock and Reset Signals
- 216 ToD Synchronizer Interface Signals
- 217 Packet Classifier Block
- 218 Packet Classifier Signals
- 218 Packet Classifier Common Clock and Reset Signals
- 218 Packet Classifier Avalon-ST Interface Signals
- 219 Packet Classifier Ingress Control Signals
- 220 Packet Classifier Control Insert Signals
- 221 Packet Classifier Timestamp Field Location Signals
- 223 Triple-Speed Ethernet IP Core Document Revision History
- 229 How to Contact Altera