J-Link RDI User Guide

J-Link RDI User Guide

Chapter 4

Configuration

41

This chapter describes how to confgure J-Link RDI.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

42 CHAPTER 4 Configuration

4.1

Overview

This chapter provides a short overview about the configuration abilities of J-Link RDI.

Normally, the default settings can be used.

4.1.1

Configuration file JLinkRDI.ini

All settings are stored in the file JLinkRDI.ini and default.jlinksettings. These files are located in the same directory as the JLinkRDI.dll.

4.1.2

Using different configurations

It can be desirable to use different configurations for different targets. If you intent to do this, you should create a new folder and copy the JLinkARM.dll and the

JLinkRDI.dll

into it. You can now have project A which uses the DLLs in the original folder and project B which uses the DLLs in the newly created directory. Both projects will use separate configuration files, stored in the same directory as the DLLs they are using.

If your debugger allows using a project-relative path (such as IAR's EWARM: Use for example $PROJ_DIR$\RDI\), it can make sense to create the directory for the DLLs and configuration file in a subdirectory of the project.

4.1.3

Using mutliple J-Links simulatenously

This procedure can also be used to operate 2 J-Links with different settings on the same host at the same time.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

43

4.2

Configuration dialog

The configuration dialog consists of several tabs making the configuration of J-Link

RDI an easy step.

4.2.1

General

4.2.1.1

Connection to J-Link

This setting allows to configure if J-Link is connected locally via USB or is connected on a remote system and should be accessed by a given network address.

4.2.1.2

About

Opens the "About" window.

4.2.1.3

License (J-Link RDI License managment)

1. The License button opens the J-Link RDI License management dialog. J-Link

RDI requires a valid license.

2. Click the Add license button and enter your license. Confirm your input by click-

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

44 ing the OK button.

CHAPTER 4

3. The J-Link RDI license is now added.

Configuration

4.2.2

Init

4.2.2.1

Macro file

A macro file can be specified to load custom settings to configure J-Link RDI with advanced commands for special chips or operations. For example a macro file can be used to initialize a target system in just about any way required.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

4.2.3

Comands in the macro file

Delay(x);

Reset(x);

Go();

Halt();

Command

SetJTAGSpeed(x);

Description

Sets the JTAG speed, x

= speed in kHz (0=Auto)

Waits a given time, x

= delay in milliseconds

Resets the target, x

= delay in milliseconds

Starts the ARM core

Halts the ARM core

Read8(Addr);

Read16(Addr);

Reads a 8/16/32 bit value,

Addr

= address to read (as hex value)

Read32(Addr);

Verify8(Addr, Data);

Verify16(Addr, Data);

Verifies a 8/16/32 bit value,

Addr

= address to verify (as hex value)

Data

= data to verify (as hex value)

Verify32(Addr, Data);

Write8(Addr, Data);

Write16(Addr, Data);

Writes a 8/16/32 bit value,

Addr

= address to write (as hex value)

Data

= data to write (as hex value)

Write32(Addr, Data);

WriteVerify8(Addr, Data);

Writes and verifies a 8/16/32 bit value,

WriteVerify16(Addr, Data);

WriteVerify32(Addr, Data);

Addr

Data

= address to write (as hex value)

= data to write (as hex value)

WriteRegister(Reg, Data);

WriteJTAG_IR(Cmd);

WriteJTAG_DR(nBits, Data);

Table 4.1: Macro file commands

Writes a register

Writes the JTAG instruction register

Writes the JTAG data register

4.2.4

Example of macro file

/*********************************************************************

*

* Macro file for J-LINK RDI

*

**********************************************************************

* File: LPC2294.setup

* Purpose: Setup for Philips LPC2294 chip

**********************************************************************

*/

SetJTAGSpeed(1000);

Reset(0);

Write32(0xE01FC040, 0x00000001); // Map User Flash into Vector area at (0-3f)

Write32(0xFFE00000, 0x20003CE3); // Setup CS0

Write32(0xE002C014, 0x0E6001E4); // Setup PINSEL2 Register

SetJTAGSpeed(2000);

45

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

46

4.2.5

JTAG

CHAPTER 4 Configuration

4.2.5.1

JTAG speed

This allows the selection of the JTAG speed. There are basically three types of speed settings (which are explained below):

• Fixed JTAG speed

• Automatic JTAG speed

• Adaptive clocking

Fixed JTAG speed

The target is clocked at a fixed clock speed. The maximum JTAG speed the target can handle depends on the target itself. In general ARM cores without JTAG synchronization logic (such as ARM7-TDMI) can handle JTAG speeds up to the CPU speed, ARM cores with JTAG synchronization logic (such as ARM7-TDMI-S, ARM946E-S,

ARM966EJ-S) can handle JTAG speeds up to 1/6 of the CPU speed. JTAG speeds of more than 10 MHz are not recommended.

Automatic JTAG speed

Selects automatically the maximum JTAG speed handled by the TAP controller.

Note:

On ARM cores without synchronization logic, this may not work reliably, since the CPU core may be clocked slower than the maximum JTAG speed.

Adaptive clocking

If the target provides the RTCK signal, select the adaptive clocking function to synchronize the clock to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface.

Note:

If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.

4.2.5.2

JTAG scan chain with multiple devices

The JTAG scan chain allows to specify the instruction register organization of the target system. This may be needed if there are more devices located on the target system than the ARM chip you want to access or if more than one target system is connected to one J-Link ARM at once.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

47

4.2.6

CPU

4.2.6.1

Reset strategy

This defines the behavior how J-Link RDI should handle resets called by software.

J-Link supports different reset strategies. This is necessary because there is no single way of resetting and halting an ARM core before it starts to execute instructions.

What is the problem if the core executes some instructions after RESET?

The instructions executed can cause various problems. Some cores can be completely

"confused", which means they can not be switched into debug mode (CPU can not be halted). In other cases, the CPU may already have initialized some hardware components, causing unexpected interrupts or worse, the hardware may have been initialized with illegal values. In some of these cases, such as illegal PLL settings, the CPU may be operated beyond specification, possibly locking the CPU.

Available reset strategies

The following reset strategies, described in detail below, are available:

• Hardware, halt after reset (normal)

• Hardware, halt after reset using WP

• Hardware, halt after reset using DBGRQ

• Hardware, halt with [email protected]

• Software, for Analog Devices ADuC7xxx MCUs

• No reset

Hardware, halt after reset (normal)

The hardware reset pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted. The number of instructions executed depends primarily on the JTAG speed: the higher the

JTAG speed, the faster the CPU can be halted.

Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release. If a pause has been specified, J-Link waits for the specified time before trying to halt the CPU. This can be useful if a bootloader

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

48 CHAPTER 4 Configuration which resides in flash or ROM needs to be started after reset.

Hardware, halt after reset using WP

The hardware RESET pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted.

The number of instructions executed depends primarily on the JTAG speed: the higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release.

Hardware, halt after reset using DBGRQ

The hardware RESET pin is used to reset the CPU. After reset release, J-Link continuously tries to halt the CPU. This typically halts the CPU shortly after reset release; the CPU can in most systems execute some instructions before it is halted.

The number of instructions executed depends primarily on the JTAG speed: the higher the JTAG speed, the faster the CPU can be halted. Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release.

Hardware, halt with [email protected]

The hardware reset pin is used to reset the CPU. Before doing so, the ICE breaker is programmed to halt program execution at address 0; effectively a breakpoint is set at address 0. If this strategy works, the CPU is actually halted before executing a single instruction.

This reset strategy does not work on all systems for two reasons:

• If nRESET and nTRST are coupled, either on the board or the CPU itself, reset clears the breakpoint, which means the CPU is not stopped after reset.

• Some MCUs contain a bootloader program (sometimes called kernel), which needs to be executed to enable JTAG access.

Software, for Analog Devices ADuC7xxx MCUs

The following sequence is executed:

• The CPU is halted

• A software reset sequence is downloaded to RAM

• A breakpoint at address 0 is set

• The software reset sequence is executed

This sequence performs a reset of CPU and peripherals and halts the CPU before executing instructions of the user program. It is recommended reset sequence for Analog Devices ADuC7xxx MCUs and works with these chips only.

No reset

No reset is performed.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

49

4.2.7

Log

A log file can be generated for J-Link ARM and J-Link RDI. This log files may be useful for debugging and evaluating. They may help you to solve a problem yourself but is also needed by the support to help you with it.

Default path of the J-Link ARM log file: c:\JLinkARM.log

Default path of the J-Link RDI log file: c:\JLinkRDI.log

Example of logfile content:

060:028 (0000) Logging started @ 2005-10-28 07:36

060:028 (0000) DLL Compiled: Oct 4 2005 09:14:54

060:031 (0026) ARM_SetMaxSpeed - Testing speed 3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0F

3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0F 3F0F0F0FAuto JTAG speed: 4000 kHz

060:059 (0000) ARM_SetEndian(ARM_ENDIAN_LITTLE)

060:060 (0000) ARM_SetEndian(ARM_ENDIAN_LITTLE)

060:060 (0000) ARM_ResetPullsRESET(ON)

060:060 (0116) ARM_Reset(): SpeedIsFixed == 0 -> JTAGSpeed = 30kHz >48> >2EF>

060:176 (0000) ARM_WriteIceReg(0x02,00000000)

060:177 (0016) ARM_WriteMem(FFFFFC20,0004) -- Data: 01 06 00 00 - Writing 0x4 bytes

@ 0xFFFFFC20 >1D7>

060:194 (0014) ARM_WriteMem(FFFFFC2C,0004) -- Data: 05 1C 19 00 - Writing 0x4 bytes

@ 0xFFFFFC2C >195>

060:208 (0015) ARM_WriteMem(FFFFFC30,0004) -- Data: 07 00 00 00 - Writing 0x4 bytes

@ 0xFFFFFC30 >195>

060:223 (0002) ARM_ReadMem (00000000,0004)JTAG speed: 4000 kHz -- Data: 0C 00 00 EA

060:225 (0001) ARM_WriteMem(00000000,0004) -- Data: 0D 00 00 EA - Writing 0x4 bytes

@ 0x00000000 >195>

060:226 (0001) ARM_ReadMem (00000000,0004) -- Data: 0C 00 00 EA

060:227 (0001) ARM_WriteMem(FFFFFF00,0004) -- Data: 01 00 00 00 - Writing 0x4 bytes

@ 0xFFFFFF00 >195>

060:228 (0001) ARM_ReadMem (FFFFF240,0004) -- Data: 40 05 09 27

060:229 (0001) ARM_ReadMem (FFFFF244,0004) -- Data: 00 00 00 00

060:230 (0001) ARM_ReadMem (FFFFFF6C,0004) -- Data: 10 01 00 00

060:232 (0000) ARM_WriteMem(FFFFF124,0004) -- Data: FF FF FF FF - Writing 0x4 bytes

@ 0xFFFFF124 >195>

060:232 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:233 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:234 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:236 (0000) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:237 (0000) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:238 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:239 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:240 (0001) ARM_ReadMem (FFFFF130,0004) -- Data: 00 00 00 00

060:241 (0001) ARM_WriteMem(FFFFFD44,0004) -- Data: 00 80 00 00 - Writing 0x4 bytes

@ 0xFFFFFD44 >195>

060:277 (0000) ARM_WriteMem(00000000,0178) -- Data: 0F 00 00 EA FE FF FF EA ...

060:277 (0000) ARM_WriteMem(000003C4,0020) -- Data: 01 00 00 00 02 00 00 00 ... -

Writing 0x178 bytes @ 0x00000000

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

50 CHAPTER 4 Configuration

060:277 (0000) ARM_WriteMem(000001CC,00F4) -- Data: 30 B5 15 48 01 68 82 68 ... -

Writing 0x20 bytes @ 0x000003C4

060:277 (0000) ARM_WriteMem(000002C0,0002) -- Data: 00 47

060:278 (0000) ARM_WriteMem(000002C4,0068) -- Data: F0 B5 00 27 24 4C 34 4D ... -

Writing 0xF6 bytes @ 0x000001CC

060:278 (0000) ARM_WriteMem(0000032C,0002) -- Data: 00 47

060:278 (0000) ARM_WriteMem(00000330,0074) -- Data: 30 B5 00 24 A0 00 08 49 ... -

Writing 0x6A bytes @ 0x000002C4

060:278 (0000) ARM_WriteMem(000003B0,0014) -- Data: 00 00 00 00 0A 00 00 00 ... -

Writing 0x74 bytes @ 0x00000330

060:278 (0000) ARM_WriteMem(000003A4,000C) -- Data: 14 00 00 00 E4 03 00 00 ... -

Writing 0x14 bytes @ 0x000003B0

060:278 (0000) ARM_WriteMem(00000178,0054) -- Data: 12 4A 13 48 70 B4 81 B0 ... -

Writing 0xC bytes @ 0x000003A4

060:278 (0000) ARM_SetEndian(ARM_ENDIAN_LITTLE)

060:278 (0000) ARM_SetEndian(ARM_ENDIAN_LITTLE)

060:278 (0000) ARM_ResetPullsRESET(OFF)

060:278 (0009) ARM_Reset(): - Writing 0x54 bytes @ 0x00000178 >3E68>

060:287 (0001) ARM_Halt(): **** Warning: Chip has already been halted.

...

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

51

4.3

Setting up flash download & unlimited flash breakpoints

4.3.1

Flash download

In order to allow direct download into internal flash memory of popular microcontrollers, J-Link RDI needs to know which device it is talking to. When starting a debug session and no device has been selected in a previous session, a device selection dialog pops up which allows the user to select the device he is using. If the device which is used does not provide internal flash memory or is not in the list, the core or

"Unspecified" should be selected.

4.3.2

Unlimited flash breakpoints

J-Link comes with a feature that allows the user to set an unlimited number of breakpoints in flash memory when debugging. This feature can be used free of charge for evaluation (no time limitation). For commercial use, a license is required. In order to make use of unlimited breakpoints in flash memory, the same as for download into flash memory is necessary: J-Link needs to know the device.

So, as soon as the device has been selected, both features can be used.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

52 CHAPTER 4 Configuration

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents