J-Link RDI User Guide

J-Link RDI User Guide

71

Chapter 9

Background information

This chapter provides background information about JTAG and ARM. The ARM7 and

ARM9 architecture is based on Reduced Instruction Set Computer (RISC) principles.

The instruction set and related decode mechanism are greatly simplified compared with microprogrammed Complex Instruction Set Computer (CISC).

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

72 CHAPTER 9 Background information

9.1

JTAG

JTAG is the acronym for Joint Test Action Group. In the scope of this document,

"the JTAG standard" means compliance with IEEE Standard 1149.1-2001.

9.1.1

Test access port (TAP)

JTAG defines a TAP (Test access port). The TAP is a general-purpose port that can provide access to many test support functions built into a component. It is composed as a minimum of the three input connections (TDI, TCK, TMS) and one output connection (TDO). An optional fourth input connection (nTRST) provides for asynchronous initialization of the test logic.

TCK

PIN

TDI

TMS

TDO

TRST

Type

Input

Input

Input

Output

Input

(optional

)

Explanation

The test clock input (TCK) provides the clock for the test logic.

Serial test instructions and data are received by the test logic at test data input (TDI).

The signal received at test mode select (TMS) is decoded by the TAP controller to control test operations.

Test data output (TDO) is the serial output for test instructions and data from the test logic.

The optional test reset (TRST) input provides for asynchronous initialization of the TAP controller.

9.1.2

Data registers

JTAG requires at least two data registers to be present: the bypass and the boundary-scan register. Other registers are allowed but are not obligatory.

Bypass data register

A single-bit register that passes information from TDI to TDO.

Boundary-scan data register

A test data register which allows the testing of board interconnections, access to input and output of components when testing their system logic and so on.

9.1.3

Instruction register

The instruction register holds the current instruction and its content is used by the

TAP controller to decide which test to perform or which data register to access. It consist of at least two shift-register cells.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

73

9.1.4

The TAP controller

The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry.

tms=1

Reset

Idle tms=0 tms=1 tms=0 tms=1 tm s=0

DR-Scan tms=0 tm s=1

Capture-DR tms=0

Shift-DR tms=1 tms=0

Exit1-DR tms=0 tms=1

Pause-DR tms=1 tms=0

Exit2-DR tms=1

Update-DR tms=1 tms=0

IR-Scan tm s=0 tm s=1 tms=1

Capture-IR tm s=0

Shift-IR tm s=1 tms=0 tms=0

Exit1-IR tm s=0 tm s=1

Pause-IR tm s=1 tms=0

Exit2-IR tms=1

Update-IR tms=1 tms=0

9.1.4.1

State descriptions

Reset

The test logic is disabled so that normal operation of the chip logic can continue unhindered. No matter in which state the TAP controller currently is, it can change into Reset state if TMS is high for at least 5 clock cycles. As long as TMS is high, the

TAP controller remains in Reset state.

Idle

Idle is a TAP controller state between scan (DR or IR) operations. Once entered, this state remains active as long as TMS is low.

DR-Scan

Temporary controller state. If TMS remains low, a scan sequence for the selected data registers is initiated.

IR-Scan

Temporary controller state. If TMS remains low, a scan sequence for the instruction register is initiated.

Capture-DR

Data may be loaded in parallel to the selected test data registers.

Shift-DR

The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

74 CHAPTER 9 Background information

Exit1-DR

Temporary controller state.

Pause-DR

The shifting of the test data register between TDI and TDO is temporarily halted.

Exit2-DR

Temporary controller state. Allows to either go back into Shift-DR state or go on to

Update-DR.

Update-DR

Data contained in the currently selected data register is loaded into a latched parallel output (for registers that have such a latch). The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.

Capture-IR

Instructions may be loaded in parallel into the instruction register.

Shift-IR

The instruction register shifts the values in the instruction register towards TDO with each clock.

Exit1-IR

Temporary controller state.

Pause-IR

Wait state that temporarily halts the instruction shifting.

Exit2-IR

Temporary controller state. Allows to either go back into Shift-IR state or go on to

Update-IR.

Update-IR

The values contained in the instruction register are loaded into a latched parallel output from the shift-register path. Once latched, this new instruction becomes the current one. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process.

9.2

The ARM core

The ARM7 family is a range of low-power 32-bit RISC microprocessor cores. Offering up to 130MIPs (Dhrystone2.1), the ARM7 family incorporates the 16-bit Thumb instruction set. The family consists of the ARM7TDMI, ARM7TDMI-S and ARM7EJ-S processor cores and the ARM720T cached processor macrocell.

The ARM9 family is built around the ARM9TDMI processor core and incorporates the

16-bit Thumb instruction set. The ARM9 Thumb family includes the ARM920T and

ARM922T cached processor macrocells.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

75

9.2.1

Processor modes

The ARM architecture supports seven processor modes.

Processor mode Description

User

System

Supervisor

Abort usr sys svc abt

Normal program execution mode

Runs privileged operating system tasks

A protected mode for the operating system

Implements virtual memory and/or memory protection

Undefined

Interrupt und irq

Supports software emulation of hardware coprocessors

Used for general-purpose interrupt handling

Fast interrupt fiq Supports a high-speed data transfer or channel process

Table 9.1: ARM processor modes

9.2.2

Registers of the CPU core

The CPU core has the following registers:

R8

R9

R10

R11

R12

R13

R14

PC

R4

R5

R6

R7

R0

R1

R2

R3

User/

System

Supervisor

R13_svc

R14_svc

Abor t

R13_abt

R14_abt

Undefined

R13_und

R14_und

Interrupt

R13_irq

R14_irq

Fast interrupt

R8_fiq

R9_fiq

R10_fiq

R11_fiq

R12_fiq

R13_fiq

R14_fiq

CPSR

SPSR_svc

Table 9.2: ARM CPU registers

SPSR_abt SPSR_und SPSR_irq SPSR_fiq

= indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode.

The ARM core has a total of 37 registers:

• 31 general-purpose registers, including a program counter. These registers are

32 bits wide.

• 6 status registers. These are also 32-bits wide, but only 12-bits are allocated or need to be implemented.

Registers are arranged in partially overlapping banks, with a different register bank for each processor mode. At any time, 15 general-purpose registers (R0 to R14), one or two status registers and the program counter are visible.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

76 CHAPTER 9 Background information

9.2.3

ARM /Thumb instruction set

An ARM core starts execution in ARM mode after reset or any type of exception. Most

(but not all) ARM cores come with a secondary instruction set, called the Thumb instruction set. The core is said to be in Thumb mode if it is using the thumb instruction set. The thumb instruction set consists of 16-bit instructions, where the ARM instruction set consists of 32-bit instructions. Thumb mode improves code density by approximately 35%, but reduces execution speed on systems with high memory bandwidth (because more instructions are required). On systems with low memory bandwidth, Thumb mode can actually be as fast or faster than ARM mode. Mixing

ARM and Thumb code (interworking) is possible.

J-Link ARM fully supports debugging of both modes without limitation.

9.3

EmbeddedICE

EmbeddedICE is a set of registers and comparators used to generate debug exceptions (such as breakpoints).

EmbeddedICE is programmed in a serial fashion using the ARM core controller. It consists of two real-time watchpoint units, together with a control and status register. You can program one or both watchpoint units to halt the execution of instructions by ARM core. Two independent registers, debug control and debug status, provide overall control of EmbeddedICE operation.

Execution is halted when a match occurs between the values programmed into

EmbeddedICE and the values currently appearing on the address bus, data bus, and various control signals. Any bit can be masked so that its value does not affect the comparison.

Either of the two real-time watchpoint units can be configured to be a watchpoint

(monitoring data accesses) or a breakpoint (monitoring instruction fetches). You can make watchpoints and breakpoints data-dependent.

EmbeddedICE is an additional debug hardware within the core, therefore the EmbeddedICE debug architecture requires almost no target resources (for example, memory, access to exception vectors, and time).

9.3.1

Breakpoints and watchpoints

Breakpoints

A "breakpoint" stops the core when a selected instruction is executed. It is then possible to examine the contents of both memory (and variables).

Watchpoints

A "watchpoint" stops the core if a selected memory location is accessed. For a watchpoint (WP), the following properties can be specified:

• Address (including address mask)

• Type of access (R, R/W, W)

• Data (including data mask)

Software / hardware breakpoints

Hardware breakpoints are "real" breakpoints, using one of the 2 available watchpoint units to breakpoint the instruction at any given address. Hardware breakpoints can be set in any type of memory (RAM, ROM, Flash) and also work with self-modifying code. Unfortunately, there is only a limited number of these available (2 in the

EmbeddedICE). When debugging a program located in RAM, another option is to use software breakpoints. With software breakpoints, the instruction in memory is modified. This does not work when debugging programs located in ROM or Flash, but has one huge advantage: The number of software breakpoints is not limited.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

77

9.3.2

The ICE registers

The two watchpoint units are known as watchpoint 0 and watchpoint 1. Each contains three pairs of registers:

• address value and address mask

• data value and data mask

• control value and control mask

The following table shows the function and mapping of EmbeddedICE registers.

Register Width Function

0x00

0x01

0x04

0x05

0x08

0x09

0x0A

0x0B

32

32

32

32

3

5

6

32

Debug control

Debug status

Debug comms control register

Debug comms data register

Watchpoint 0 address value

Watchpoint 0 address mask

Watchpoint 0 data value

Watchpoint 0 data mask

0x0C

0x0D

0x10

0x11

9

8

32

32

Watchpoint 0 control value

Watchpoint 0 control mask

Watchpoint 1 address value

Watchpoint 1 address mask

0x12

0x13

0x14

0x15

32

32

9

8

Watchpoint 1 data value

Watchpoint 1 data mask

Watchpoint 1 control value

Watchpoint 1 control mask

Table 9.3: Function and mapping of EmbeddedICE registers

For more information about EmbeddedICE please see the technical reference manual of your ARM CPU. (www.arm.com)

9.4

Flash programming

J-Link ARM comes with a DLL, which allows - amongst other functionalities - reading and writing RAM, CPU registers, starting and stopping the CPU and setting breakpoints. The standard DLL does not have API functions for flash programming. However, the functionality offered can be used to program the flash. In that case a flashloader is required.

9.4.1

How does flash programming via J-Link ARM work ?

This requires extra code. This extra code typically downloads a program into the RAM of the target system, which is able to erase and program the flash memory. This program is called RAMCode and "knows" how to program the flash; it contains an implementation of the flash programming algorithm for the particular flash. Different flash devices have different programming algorithms; the programming algorithm also depends on other things such as endianess of the target system and organization of the flash memory (e.g. 1*8 bits, 1*16 bits, 2*16 bits or 32 bits). The RAMCode also requires the data to be programmed into the flash memory. There are two ways of supplying this data:

• Data download to RAM

• Data download via DCC.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

78 CHAPTER 9 Background information

9.4.1.1

Data download to RAM

The data (or part of it) is downloaded to an other part of the RAM of the target system. The instruction pointer (R15) of the CPU is then set to the start address of the

RAMCode, the CPU is started, executing the RAMCode. The RAMCode, which contains the programming algorithm for the flash chip, copies the data into the flash chip. The

CPU is stopped after this. This process may have to be repeated until the entire data is programmed into the flash.

9.4.1.2

Data download via DCC

In this case, the RAMCode is started as described above before downloading any data. The RAMCode then communicates with the PC (via DCC, JTAG and J-Link ARM), transferring data to the target. The RAMCode then programs the data into flash and waits for new data from the host. The write memory functions of J-Link ARM are used to transfer the RAMCode only, but not to transfer the data. The CPU is started and stopped only once. Using DCC for communication is typically faster than using write memory functions for RAM download since the overhead is lower.

9.4.2

Available options for flash programming

There are different solutions available to program internal or external flash memory connected to ARM cores using J-Link ARM.

9.4.2.1

J-Flash ARM - Complete flash programming solution.

J-Flash ARM is a stand-alone Windows application, which can read / write data files and program the flash in almost any ARM core supported by J-Link ARM. J-Flash ARM requires an extra license from SEGGER.

9.4.2.2

JLinkARMFlash.dll - A DLL with flash programming capabilities.

An enhanced version of the JLinkARM.dll with additional API functions, which allow loading and programming of data files. This DLL comes with a sample executable, as well as the source code of this executable and a project file. This can be an interesting option if you want to write your own programs for production purposes.

This DLL also requires an extra license from SEGGER; please contact us for more information.

9.4.2.3

J-Link RDI Flash download - Allows flash download from any

RDI-compliant tool chain.

RDI (Remote Debug Interface) is a standard for "debug transfer agents" such as J-

Link ARM. The J-Link RDI software allows using J-Link ARM from any RDI compliant debugger. You can use the flash download option integrated in the J-Link RDI software to download your application program into flash memory.

The J-Link RDI software as well as the flash download option require licenses from

SEGGER.

9.4.2.4

Flash loader of compiler / debugger vendor such as IAR.

A lot of debuggers (some of them integrated into a workbench / IDE) come with their own flash loaders. The flash loaders can of course be used if they match to your flash configuration, which is something that needs to be checked with the debugger vendor.

9.4.2.5

Write your own flash loader

Implement your own flash loader using the functionality of the JLinkARM.dll as described above. This can be a time consuming process and requires in-depth knowledge of the flash programming algorithm used as well as the target system.

J-Link RDI(UM08004) © 2004-2013 SEGGER Microcontroller GmbH & Co. KG

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Table of contents