User's Manual

Host Interface (HI08)

HI08—External Host Programmer’s Model

Table 6-11

HREQ and HDRQ Settings

HDRQ HREQ

0

0

1

0

1

0

1 1

Effect

HREQ is cleared; no host processor interrupts are requested.

HREQ is set; an interrupt is requested.

HTRQ and HRRQ are cleared, no host processor interrupts are requested.

HTRQ or HRRQ are set; an interrupt is requested.

The HREQ bit may be set from either or both of two conditions—either the Receive

Byte Registers are full or the Transmit Byte Registers are empty. These conditions are indicated by the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ is set if one or more of the two enabled interrupt sources is set.

6.6.4

Interrupt Vector Register (IVR)

The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 family processor vectored interrupts. Only the host processor can read and write this register. The contents of the IVR are placed on the host data bus, H[7:0], when both the HREQ and HACK pins are asserted. The contents of this register are initialized to $0F by a hardware or software reset. This value corresponds to the uninitialized interrupt vector in the MC68000 family.

7

IV7

6

IV6

5

IV5

4

IV4

3

IV3

2

IV2

1

IV1

0

IV0

Figure 6-15

Interrupt Vector Register (IVR)

AA0671

6.6.5

Receive Byte Registers (RXH, RXM, RXL)

The Receive Byte Registers are viewed by the host processor as three 8-bit read-only registers. These registers are the Receive High register (RXH), the Receive Middle register (RXM), and the Receive Low register (RXL). They receive data from the high, middle, and low bytes, respectively, of the HTX register and are selected by the external host address inputs (HA[2:0]) during a host processor read operation.

6-28 DSP56303UM/AD MOTOROLA



The memory address of the Receive Byte Registers are set by the HLEND bit in the

ICR. If the HLEND bit is set, the RXH is located at address $7, RXM at $6, and RXL at

$5. If the HLEND bit is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.

When data is written to the Receive Byte Register at host address $7, the Receive Data

Register Full (RXDF) bit is set. The host processor may program the RREQ bit to assert the external HREQ pin when RXDF is set. This indicates that the HI08 has a full word (either 8, 16, or 24 bits) for the host processor. The host processor may program the RREQ bit to assert the external HREQ pin when RXDF is set. Asserting the HREQ pin informs the host processor that the receive byte registers have data to be read.

When the host reads the Receive Byte Register at host address $7 the RXDF bit is cleared.

6.6.6

Transmit Byte Registers (TXH:TXM:TXL)

The Transmit Byte Registers are viewed as three 8-bit write-only registers by the host processor. These registers are the Transmit High register (TXH), the Transmit Middle register (TXM), and the Transmit Low register (TXL). These registers send data to the high, middle, and low bytes, respectively, of the HRX register and are selected by the external host address inputs, HA[2:0], during a host processor write operation.

If the HLEND bit in the ICR is set, the TXH register is located at address $7, the TXM register at $6 and the TXL register at $5. If the HLEND bit in the ICR is cleared, the

TXH register is located at address $5, the TXM register at $6 and the TXL register at

$7.

Data may be written into the Transmit Byte Registers when the Transmit Data

Register Empty (TXDE) bit is set. The host processor may program the TREQ bit to assert the external HREQ/HTRQ pin when TXDE is set. This informs the host processor that the Transmit Byte Registers are empty. Writing to the data register at host address $7 clears the TXDE bit. The contents of the Transmit Byte Registers are transferred as 24-bit data to the HRX register when both the TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF.

Note:

When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated. If the user reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 Family Manual, appendix

B, Polling a peripheral device for write for further details.

MOTOROLA DSP56303UM/AD 6-29



6.6.7

Host Side Registers After Reset

Table 6-12

shows the result of the four kinds of reset on bits in each of the HI08 registers seen by the host processor. The hardware reset is caused by asserting the

RESET pin. The software reset is caused by executing the RESET instruction. The individual reset is caused by clearing the HEN bit in the HPCR. The stop reset is caused by executing the STOP instruction.

Register

Name

ICR

CVR

ISR

IVR

RX

TX

Table 6-12

Host Side Registers After Reset

Reset Type

Register

Data

All Bits

HC

HV[0:6]

HREQ

HW

Reset

0

0

$2A

0

HF3 -HF2

TRDY

TXDE

RXDF

1

0

0

1

1

0

0

1

IV[0:7] $0F $0F

RXH: RXM:RXL empty empty

TXH: TXM:TXL empty empty

SW

Reset

0

0

$2A

0

IR

Reset

—

0

—

1 if TREQ is set;

0 otherwise

1

0

—

1

— empty empty

ST

Reset

—

0

—

1 if TREQ is set;

0 otherwise

1

0

—

1

— empty empty

6.6.8

General Purpose I/O

When configured as General Purpose I/O (GPIO), the HI08 is viewed by the

DSP56303 as memory-mapped registers (see

Section 6.5

) that control up to sixteen

I/O pins. Software and hardware resets clear all DSP side control registers and configure the HI08 as GPIO with all sixteen pins disconnected. External circuitry connected to the HI08 may need external pull-up/pull-down resistors until the pins



Servicing the Host Interface

are configured for operation. The registers cleared are the HPCR, HDDR, and HDR.

Selection between GPIO and HI08 is made by clearing HPCR bits 6 through 1 for

GPIO or setting these bits for HI08 functionality. If the HI08 is in GPIO mode, the

HDDR configures each corresponding pin in the HDR as an input pin if the HDDR bit is cleared or as an output pin if the HDDR bit is set (see

6.5.7 Host Data Direction

Register (HDDR)

on page 6-17

and

6.5.8 Host Data Register (HDR)

on page 6-17).

6.7

SERVICING THE HOST INTERFACE

The HI08 can be serviced by using one of the following protocols:

• Polling

• Interrupts

The host processor writes to the appropriate HI08 register to reset the control bits an configure the HI08 for proper operation.

6.7.1

HI08 Host Processor Data Transfer

To the host processor, the HI08 looks like a contiguous block of Static RAM. To transfer data between itself and the HI08, the host processor performs the following steps:

1. asserts the HI08 address to select the register to be read or written

2. selects the direction of the data transfer

(If it is writing, the host processor sources the data on the bus.)

3. strobes the data transfer

6.7.2

Polling

In the Polling mode of operation, the HREQ/HTRQ pin is not connected to the host processor and HACK must be deasserted to insure IVR data is not being driven on

H[7:0] when other registers are being polled. (If the HACK function is not needed, the HACK pin can be configured as a GPIO pin; see

6.5.6 Host Port Control

Register (HPCR)

on page 6-13).




The host processor first performs a data read transfer to read the ISR (see

Figure 6-16

). This allows the host processor to assess the status of the HI08 and perform the appropriate actions.

Generally, after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer.

1. If RXDF is set, the Receive Data Register is full and a data read can be performed by the host processor.

2. If TXDE is set, the Transmit Data Register is empty. A data write can be performed by the host processor.

3. If TRDY is set, the Transmit Data Register is empty. This implies that the

Receive Data Register on the DSP side is also empty. Data written by the host processor to the HI08 is transferred directly to the DSP side.

4. If (HF2 and HF3)

≠

0, depending on how the host flags have been used, this may indicate that an application-specific state within the DSP56303 has been reached. Intervention by the host processor may be required.

5. If HREQ is set, the HREQ/TRQ pin has been asserted, and the DSP56303 is requesting the attention of the host processor. One of the previous four conditions exists.

After the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer.

If the host processor has issued a command to the DSP56303 by writing to the CVR and setting the HC bit, it can read the HC bit in the CVR to determine whether the command has been accepted by the interrupt controller in the DSP core. When the command has been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP core.




7

$2

HREQ 0

Host Request

Asserted

0 HF3

Status

0

HF2 TRDY TXDE RXDF ISR

HRRQ

HREQ

HTRQ

$0

7

INIT 0 0 HF1

0

HF0 HBEND TREQ RREQ ICR

Enable

Figure 6-16

HI08 Host Request Structure

AA0672

6.7.3

Servicing Interrupts

If either HREQ/HTRQ or the HRRQ pin or both are connected to the host processor’s interrupt input, the HI08 can request service from the host processor by asserting one of these pins. The HREQ/HTRQ and/or the HRRQ pin is asserted when TXDE is set and/or RXDF is set and the corresponding enable bit (TREQ or RREQ, respectively)

is set. This is depicted in Figure 6-16.

HREQ is normally connected to the maskable interrupt input of the host processor.

The host processor acknowledges host interrupts by executing an interrupt service routine. The two Least Significant Bits (RXDF and TXDE) of the ISR register may be

tested by the host processor to determine the interrupt source (see Figure 6-16). The

host processor interrupt service routine must read or write the appropriate HI08 data register to clear the interrupt. HREQ/HTRQ and/or HRRQ is deasserted under the following conditions.

• The enabled request is cleared or masked.

or

The DSP is reset.

If the host processor is a member of the MC68000 family, there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP56303. Instead, the DSP56303 automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK. The contents of the IVR are placed on the host data bus while HREQ/TRQ (or HRRQ) and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP56303.



HI08 Programming Model - Quick Reference














SECTION 7

ENHANCED SYNCHRONOUS SERIAL

INTERFACE (ESSI)


Enhanced Synchronous Serial Interface (ESSI)

7.1

7.3

7.4

7.5

7.6

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

ESSI DATA AND CONTROL PINS . . . . . . . . . . . . . . . . . . . . 7-4

ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

GPIO PINS AND REGISTERS . . . . . . . . . . . . . . . . . . . . . . 7-44



Introduction

7.1

INTRODUCTION

The Enhanced Synchronous Serial Interface (ESSI) provides a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator.

There are two independent and identical Enhanced Synchronous Serial Interfaces in the DSP56303: ESSI0 and ESSI1. For the sake of simplicity, a single generic ESSI is described.

The ESSI block diagram is shown in Figure 7-1. This interface is synchronous because

all serial transfers are synchronized to a clock.

Note:

This should not be confused with what is known as the Asynchronous channels mode of the ESSI, in which separate clocks are used for the receiver and transmitter. In this mode, the ESSI is still a synchronous device, because all transfers are synchronized to these clocks.

Additional synchronization signals are used to delineate the word frames. The

Normal mode of operation is used to transfer data at a periodic rate, one word per period. The Network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. The Network mode can be used to build Time Division Multiplexed (TDM) networks. In contrast, the

On-Demand mode is intended for non-periodic transfers of data. This mode can be used to transfer data serially at high speed when the data become available. This mode offers a subset of the SPI protocol.

Since each ESSI unit can be configured with one receiver and three transmitters, the two units can be used together for surround sound applications (which need two digital input channels and six digital output channels).

7.2

ENHANCEMENTS TO THE ESSI

The Synchronous Serial Interface (SSI) used in the DSP56000 family has been enhanced in the following ways to make the Enhanced Synchronous Serial Interface

(ESSI):

• Network Enhancements

– Time Slot Mask Registers (receive and transmit) added



ESSI Data and Control Pins

– End-of-frame interrupt added

– Drive Enable pin added (to be used with transmitter 0)

• Audio Enhancements

– Three transmitters per ESSI (for six-channel surround sound)

• General Enhancements

– Can trigger DMA interrupts (receive or transmit)

– Separate exception enable bits

• Other Changes

– One divide by 2 removed from the internal clock source chain

– CRA(PSR) bit definition is reversed

– Gated Clock mode not available

7.3

ESSI DATA AND CONTROL PINS

Three to six pins are required for ESSI operation, depending on the operating mode selected. The Serial Transmit Data (STD) pin and Serial Control (SC0 and SC1) pins are fully synchronized to the clock if they are programmed as transmit-data pins.

7.3.1

Serial Transmit Data Pin (STD)

The STD pin is used for transmitting data from the TX0 Serial Transmit Shift Register.

STD is an output when data is being transmitted from TX0 Shift Register. With an internally generated bit clock, the STD pin becomes a high impedance output pin for a full clock period after the last data bit has been transmitted. If sequential data words are being transmitted, the STD pin does not assume a high-impedance state.

The STD pin may be programmed as a General Purpose Input/Output (GPIO) pin

(P5) when the ESSI STD function is not being used.

7.3.2

Serial Receive Data Pin (SRD)

The SRD pin receives serial data and transfers the data to the ESSI Receive Shift

Register. SRD may be programmed as a GPIO pin (P4) when the ESSI SRD function is not being used.




RSMA

RSMB

TSMA

TSMB

GDB DDB

RCLK

RX SHIFT REG

RX

TCLK

TX0 SHIFT REG

TX0

SRD

STD

CRA

CRB

TX1 SHIFT REG

TX1

SC0

TSR

SSISR

TX2 SHIFT REG

TX2

SC1

Interrupts

Clock/Frame Sync Generators and Control Logic

SC2

SCK

AA0678

Figure 7-1

ESSI Block Diagram

7.3.3

Serial Clock (SCK)

The SCK pin is a bidirectional pin providing the serial bit rate clock for the ESSI interface. The SCK pin is a clock input or output used by all the enabled transmitters and receiver in Synchronous modes or by all the enabled transmitters in




Asynchronous modes (see Table 7-1 on page 7-8). SCK may be programmed as a

GPIO pin (P3) when the ESSI SCK function is not being used.

Notes: 1.

Although an external serial clock can be independent of and asynchronous to the DSP system clock, the external ESSI clock frequency must not exceed F core

/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles.

2.

The internally sourced ESSI clock frequency must not exceed F core

/4.

7.3.4

Serial Control Pin (SC0)

ESSI0: SC00; ESSI: SC10

The function of this pin is determined by selecting either Synchronous or

Asynchronous mode (see Table 7-4 on page 7-24). In Asynchronous mode, this pin is

used for the receive clock I/O. In Synchronous mode, this pin is used as the transmitter data out pin for Transmit Shift Register 1 or for serial flag I/O. A typical application of serial flag I/O would be multiple device selection for addressing in codec systems.

If SC0 is configured as a serial flag pin, its direction is determined by the Serial

Control Direction 0 (SCD0) bit in the ESSI Control Register B (CRB). When configured as an output, its direction is determined by the value of the serial Output

Flag 0 (OF0) bit in the CRB.

If SC0 is an output, this pin can be configured as either serial output flag 0 or a

Receive Shift Register clock output. If SC0 is an input, this pin may be used either as serial input flag 0 or as a Receive Shift Register clock input. If SC0 is used as serial input flag 0, it controls the state of serial Input Flag 0 (IF0) bit in the ESSI Status

Register (SSISR).

When SC0 is configured as a transmit data pin, it is always an output pin regardless of the SCD0 bit value. SC0 is fully synchronized with the other transmit data pins

(STD and SC1).

SC0 may be programmed as a GPIO pin (P0) when the ESSI SC0 function is not being used.

Note:

The ESSI can operate with more than one active transmitter only in

Synchronous mode.




7.3.5


ESSI0:SC01; ESSI1: SCI11

The function of this pin is determined by selecting either Synchronous or

Asynchronous mode (see Table 7-4 on page 7-24). In Asynchronous mode (such as a

single codec with asynchronous transmit and receive), SC1 is the receiver frame sync

I/O. In Synchronous mode, SC1 is used for the transmitter data out pin of Transmit

Shift Register TX2, for the drive enable transmitter 0 signal, or for serial flag SC1.

When used as SC1, it operates like the previously described SC0. SC0 and SC1 are independent flags, but may be used together for multiple serial device selection. SC0 and SC1 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs. If SC1 is configured as a serial flag pin, its direction is determined by the SCD1 bit in the CRB.

When configured as an output, SC1 functionality is determined by control bit OF1 in the SSISR. The SC1 pin can be used as a serial output flag, the transmitter 0 drive enable signal, or the receive frame sync signal output. When configured as an input, this pin can be used as to receive frame sync signals from an external source or it can be used as a serial input flag. When SC1 is a serial input flag, it controls status bit IF1 in the SSISR. When this pin is configured as a transmit data pin, it is always an output pin regardless of the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data pins (STD and SC0). SC1 may be programmed as a

GPIO pin (P1) when the ESSI SC1 function is not being used.



ESSI Programming Model

0

0

0

0

SYN SCKD SCD0

Table 7-1

ESSI Clock Sources

R Clock

Source

RX

Clock

Out

T Clock

Source

1

1

1

1

0

0

0

1

0

1

0

1

0/1

0/1

Asynchronous

EXT, SC0

INT

EXT, SC0

INT

—

SC0

—

SC0

Synchronous

EXT, SCK

INT

—

SCK

EXT, SCK

EXT, SCK

INT

INT

EXT, SCK

INT

TX Clock Out

—

—

SCK

SCK

—

SCK

7.3.6


ESSI0:SC02; ESSI1:SC02

This pin is used for frame sync I/O. SC2 is the frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode. The direction of this pin is determined by the SCD2 bit in the CRB. When configured as an output, this pin outputs the internally generated frame sync signal.

When configured as an input, this pin receives an external frame sync signal for the transmitter in Asynchronous mode and for the receiver when in Synchronous mode.

SC2 may be programmed as a GPIO pin (P2) when the ESSI SC2 function is not being used.

7.4

ESSI PROGRAMMING MODEL

The ESSI is composed of:

• Two control registers (CRA, CRB)

• One status register (SSISR)




• Three transmit data registers (TX0, TX1, TX2)

• One receive data register (RX)

• Two transmit slot mask registers (TSMA, TSMB)

• Two receive slot mask registers (RSMA, RSMB)

• One special-purpose time slot register (TSR)

The following paragraphs give detailed descriptions and operations of each of the

bits in the ESSI registers. The GPIO functionality of the ESSI is described in

Section

7.6

of this manual.

11

PSR

10 9 8 7

PM7

6

PM6

5

PM5

4

PM4

3

PM3

2

PM2

1

PM1

0

PM0

23 22

SSC1

21

WL2

20

WL1

19

WL0

18

ALC

17 16

DC4

15

DC3

14

DC2

13

DC1

12

DC0

AA0857

Figure 7-2

ESSI Control Register A (CRA) (ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)

11

CKP

10

FSP

9

FSR

8

FSL1

7

FSL0

6

SHFD

5

SCKD

4

SCD2

3

SCD1

2

SCD0

1

OF1

0

OF0

23

REIE

22

TEIE

21

RLIE

20

TLIE

19

RIE

18

TIE

17

RE

16

TE0

15

TE1

14

TE2

13

MOD

12

SYN

AA0858

Figure 7-3

ESSI Control Register B (CRB) (ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)

11

23

10

22

9

21

8

20

7

RDF

19

6

TDE

18

5

ROE

17

4

TUE

16

3

RFS

15

2

TFS

14

1

IF1

13

0

IF0

12

AA0859

Figure 7-4

ESSI Status Register (SSISR) (ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)

11

TS11

10

TS10

9

TS9

8

TS8

7

TS7

6

TS6

5

TS5

4

TS4

3

TS3

2

TS2

1

TS1

0

TS0

23 22 21 20 19 18 17 16 15

TS15

14

TS14

13

TS13

12

TS12

AA0860

Figure 7-5

ESSI Transmit Slot Mask Register A (TSMA) (ESSI0 X:$FFFFB4, ESSI1

X:$FFFFA4)




11

TS27

10

TS26

9

TS25

8

TS24

7

TS23

6

TS22

5

TS21

4

TS20

3

TS19

2

TS18

1

TS17

0

TS16

23 22 21 20 19 18 17 16 15

TS31

14

TS30

13

TS29

12

TS28

AA0861

Figure 7-6

ESSI Transmit Slot Mask Register B (TSMB) (ESSI0 X:$FFFFB3, ESSI1

X:$FFFFA3)

11

RS11

10

RS10

9

RS9

8

RS8

7

RS7

6

RS6

5

RS5

4

RS4

3

RS3

2

RS2

1

RS1

0

RS0

23 22 21 20 19 18 17 16 15

RS15

14

RS14

13

RS13

12

RS12

AA0862

Figure 7-7

ESSI Receive Slot Mask Register A (RSMA) (ESSI0 X:$FFFFB2, ESSI1

X:$FFFFA2)

11

RS27

10

RS26

9

RS25

8

RS24

7

RS23

6

RS22

5

RS21

4

RS20

3

RS19

2

RS18

1

RS17

0

RS16

23 22 21 20 19 18 17 16 15

RS31

14

RS30

13

RS29

12

RS28

– Reserved bit - read as zero should be written with zero for future compatibility

AA0863

Figure 7-8

ESSI Receive Slot Mask Register B (RSMB) (ESSI0 X:$FFFFB1, ESSI1

X:$FFFFA1)

7.4.1

ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers used to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and frame sync rates, word length, and number of words per frame for the serial

data. The CRA control bits are described in the following paragraphs (see

Figure

7-2

).

7.4.1.1

CRA Prescale Modulus Select PM[7:0] Bits 7-0

The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock generator. A divide ratio from 1 to 256 (PM = $0 to $FF) may be selected. The bit clock output is available at the transmit clock pin (SCK) and/or the receive clock (SC0) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the Transmit and Receive Shift Registers. The ESSI clock generator functional




diagram is shown in Figure 7-9. F

core

is the DSP56303 core clock frequency (the same frequency as the CLKOUT pin, when that pin is enabled). Careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and

1.536 MHz to be generated. Both the hardware reset signal and the software reset instruction clear PM[7:0].

7.4.1.2

CRA Reserved Bits 8-10

These bits are reserved. They are read as 0 and should be written with 0.

7.4.1.3

CRA Prescaler Range (PSR) Bit 11

The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When PSR is set, the fixed prescaler is bypassed. When

PSR is cleared, the fixed divide-by-eight prescaler is operational (see Figure 7-9).

Note this definition is reversed from that of the 560xx SSI.

The maximum allowed internally generated bit clock frequency is the internal

DSP56303 clock frequency divided by 4; the minimum possible internally generated bit clock frequency is the DSP56303 internal clock frequency divided by 4096. Both the hardware reset signal and the software reset instruction clear PSR.




Note:

The combination PSR = 1 and PM[7:0] = $00 (dividing F core cause synchronization problems and should not be used.

by 2) may

Sync:

SCn0

TX #1, or

Flag0

Async:

RX clk

CRB(SCD0)

TX #1

CRB(TE1) or Flag0 Out

CRB(OF0)

(Sync Mode)

Flag0 In

SSISR(IF0)

(Sync Mode)

CRB(SYN) = 1

SYN = 0

0

CRA(WL2:0)

/8, /12, /16, /24, /32

1 2 3 4,5 SCD0 = 0

SYN = 0

SCD0 = 1

RCLOCK

SYN = 1

RX Shift Register

TCLOCK

CRA(WL2:0)

/8, /12, /16, /24, /32

0 1 2 3 4,5

Internal Bit Clock

SCKn

Sync:

TX/RX clk

Async:

TX clk

CRB(SCKD)

TX Shift Register

F

CORE

/2

CRA(PSR)

/1 or /8

1 0

(Opposite from SSI)

CRA(PM7:0)

/1 to /256

0 255

RX

Word

Clock

TX

Word

Clock

Note: 1. F

CORE is the DSP56300 Core internal clock frequency.

2. ESSI internal clock range: min = F

OSC

/4096 max = F

OSC

/4

3. ‘n’ in pin name is ESSI # (0 or 1)

AA0679

Figure 7-9

ESSI Clock Generator Functional Block Diagram

7.4.1.4

CRA Frame Rate Divider Control DC[4:0] Bits 16–12

The values of the DC[4:0] bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks. In Network mode, this ratio may be interpreted as the number of words per frame minus one. In Normal mode, this ratio determines the word transfer rate.

The divide ratio may range from 1 to 32 (DC = 00000 to 11111) for Normal mode and

2 to 32 (DC = 00001 to 11111) for Network mode. A divide ratio of one (DC = 00000) in Network mode is a special case known as On-demand mode. In Normal mode, a divide ratio of one (DC = 00000) provides continuous periodic data word transfers. A bit-length frame sync must be used in this case and is selected by setting the FSL[1:0] bits in the CRA to (01). Both the hardware reset signal and the software reset instruction clear DC[4:0].

The ESSI frame sync generator functional diagram is shown in Figure 7-10.




RX Word

Clock

CRA(DC4:0)

/1 to /32

0 31

Sync

Type

CRB(FSL1)

CRB(FSR)

Internal Rx Frame Sync

CRB(SCD1)

TX Word

Clock

Receive

Control Logic

These signals are identical in sync mode.

CRB(FSL1:0)

CRB(FSR)

CRB(SYN) = 0

Receive

Frame Sync

SYN = 1

CRB(SCD1) = 1

SCD1 = 0

SYN = 0

SYN = 1

SCn1

Sync:

TX #2,

Flag1, or drive enb.

Async:

RX F.S.

Flag1 In

SSISR(IF1)

(Sync Mode)

TX #2,

CRB(TE2)

Flag1 Out,

CRB(OF1) or drive enb.

CRA(SSC1)

(Sync Mode)

CRB(SCD2)

CRA(DC4:0)

/1 to /32

0 31

Sync

Type

Internal TX Frame Sync

SCn2

Sync:

TX/RX F.S.

Async:

TX F.S.

Transmit

Control Logic

Transmit

Frame Sync

AA0680

Figure 7-10

ESSI Frame Sync Generator Functional Block Diagram

7.4.1.5

CRA Reserved Bit 17

This bit is reserved. It is read as 0 and should be written with 0.

7.4.1.6

CRA Alignment Control (ALC) Bit 18

The ESSI is designed for 24-bit fractional data. Shorter data words are left aligned to the Most Significant Bit (MSB), Bit 23. For applications that use 16 bit fractional data, shorter data words are left aligned to Bit 15. The ALC bit supports shorter data words. If ALC is set, received words are left aligned to Bit 15 in the Receive Shift

Register. Transmitted words must be left aligned to Bit 15 in the Transmit Shift

Register. If the ALC bit is cleared, received words are left aligned to Bit 23 in the

Receive Shift Register. Transmitted words must be left aligned to Bit 23 in the

Transmit Shift Register. The ALC bit is cleared by either a hardware reset signal or a software reset instruction.

Note:

If the ALC bit is set, only 8-, 12-, or 16-bit words should be used. The use of

24- or 32-bit words leads to unpredictable results.




7.4.1.7

CRA Word Length Control (WL[2:0]) Bits 21-19

The WL[2:0] bits are used to select the length of the data words being transferred via

the ESSI. Word lengths of 8-, 12-, 16-, 24-, or 32- bits may be selected (see Table 7-2).

The ESSI data path programming model in Figure 7-16 and Figure 7-17 has

additional information on selecting different length data words. The ESSI data registers are 24 bits long. The ESSI transmits 32-bit words either by duplicating the last bit 8 times when WL[2:0] = 100, or by duplicating the first bit 8 times when

WL[2:0] = 101. The WL[2:0] bits are cleared by a hardware reset signal or by a software reset instruction.

Table 7-2

ESSI Word Length Selection

WL2

0

0

0

0

1

1

1

1

WL1

0

0

1

1

0

0

1

1

WL0

0

1

0

1

0

1

0

1

Number of Bits/Word

8

12

16

24

32

(valid data in the first 24 bits)

32

(valid data in the last 24 bits)

Reserved

Reserved

7.4.1.8

CRA Select SC1 as Transmitter 0 Drive Enable (SSC1) Bit 22

The SSC1 bit controls the functionality of the SC1 pin. If SSC1 is set, the ESSI is configured in Synchronous mode (the CRB synchronous/asynchronous bit (SYN) is set), and transmitter 2 is disabled (Transmit Enable (TE2) = 0)), then the SC1 pin acts as the driver enable of transmitter 0 while the SC1 pin is configured as output (SCD1

= 1). This enables the use of an external buffer for the transmitter 0 output.

If SSC1 is cleared, the ESSI is configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled (TE2 = 0), then the SC1 acts as the serial I/O flag while the

SC1 pin is configured as output (SCD1 = 1).

7.4.1.9

CRA Reserved Bit 23

This bit is reserved. It is read as 0 and should be written with 0.




7.4.2

ESSI Control Register B (CRB)

The CRB is one of two 24-bit read/write control registers used to direct the operation

of the ESSI (see Figure 7-3 on page 7-9). CRB controls the ESSI multifunction pins,

SC[2:0], which can be used as clock inputs or outputs, frame synchronization pins, transmit data pins, or serial I/O flag pins.

The serial output flag control bits and the direction control bits for the serial control pins are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are also in the CRB. The bit setting of the CRB also determines how many transmitters are enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the ESSI operating mode.

Either a hardware reset signal or a software reset instruction clear all the bits in the

CRB.

The relationship between the ESSI pins SC[2:0], SCK, and the CRB bits is summarized

in Table 7-4 on page 7-24. The ESSI CRB bits are described in the following

paragraphs.

7.4.2.1

CRB Serial Output Flags (OF0, OF1) Bits 0, 1

The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting output flags when transmitting data (by transmitter 0 through the STD pin only) is:

1. Wait for TDE (TX0 empty) to be set.

2. Write the flags.

3. Write the transmit data to the TX register.

Bits OF0 and OF1 are double-buffered so that the flag states appear on the pins when the TX data is transferred to the Transmit Shift Register. The flag bits values are synchronized with the data transfer.

Note:

The timing of the optional serial output pins SC[2:0] is controlled by the frame timing and is not affected by the settings of TE2, TE1, TE0, or the

Receive Enable (RE) bit of the CRB.

7.4.2.1.1

CRB Serial Output Flag 0 (OF0) Bit 0

When the ESSI is in Synchronous mode and transmitter 1 is disabled (TE1 = 0), the

SC0 pin is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the

SC0 pin is an output. Data present in bit OF0 is written to SC0 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode.


User's Manual

6.6.4

Interrupt Vector Register (IVR)

6.6.5

Receive Byte Registers (RXH, RXM, RXL)

6.6.6

Transmit Byte Registers (TXH:TXM:TXL)

6.6.7

Host Side Registers After Reset

6.6.8

General Purpose I/O

6.7

SERVICING THE HOST INTERFACE

6.7.1

HI08 Host Processor Data Transfer

6.7.2

Polling

6.7.3

Servicing Interrupts

SECTION 7

ENHANCED SYNCHRONOUS SERIAL

INTERFACE (ESSI)

7.1

INTRODUCTION

7.2

ENHANCEMENTS TO THE ESSI

7.3

ESSI DATA AND CONTROL PINS

7.3.1

Serial Transmit Data Pin (STD)

7.3.2

Serial Receive Data Pin (SRD)

7.3.3

Serial Clock (SCK)

7.3.4

Serial Control Pin (SC0)

7.3.5

Serial Control Pin (SC1)

7.3.6

Serial Control Pin (SC2)

7.4

ESSI PROGRAMMING MODEL

7.4.1

ESSI Control Register A (CRA)

7.4.2

ESSI Control Register B (CRB)

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