Appendix
B
M0-M1 Files and G Files
This appendix contains important information about M0-M1 files and
G files. The information is general in nature and supplements specific information contained in earlier chapters of this manual.
Topics include:
• M0-M1 Files
• G Files
M0 and M1 files are data files that reside in specialty I/O modules only. There is no image for these files in the processor memory. The application of these files depends on the function of the particular specialty I/O module. With respect to the SLC processor (SLC 5/02 or later), the M0 file is a module output file (a write only file) and the
M1 file is a module input file (a read only file). The opposite is true for specialty I/O modules, where the M0 file is a read only file, and the M1 file is a write only file.
M0-M1 Files
M0 and M1 files can be addressed in your ladder program and they can also be acted upon by the specialty I/O module - independent of the processor scan. It is important that you keep the following in mind in creating and applying your ladder logic:
Important:
During the processor scan, the ladder program can address M0 and M1 data with bit, word, or file instructions. Each time an M0-M1 file address is encountered in the program, an immediate data transfer to or from the specialty I/O module occurs. The impact these immediate data transfers have on processor scan time is described in appendix D of the SLC 500 and
MicroLogix 1000 Instruction Set Reference Manual,
Publication 1747-6.15.
Configuring M0-M1 Files
READ
CONFIG
F1
ONLINE
CONFIG
F2
M0 and M1 files are configured as part of the I/O configuration procedure for the processor file. After you have assigned the specialty
I/O module to a slot (the procedure is the same as assigning other modules), the following functions appear at the bottom of the screen:
MODIFY
RACKS
F4
MODIFY
SLOT
F5
DELETE
SLOT
F6
UNDEL
SLOT
F7
EXIT
F8
SPIO
CONFIG
F9
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Complete the following steps to configure the M0 and M1 files:
1. Press
[F9]
, Specialty I/O Configuration. The following functions appear:
ISR
NUMBER
F1
MODIFY
G FILE
F3
ADVNCD
SETUP
F5
G FILE
SIZE
F7
2. Press
[F5]
, Advanced Setup. The following functions appear:
INPUT
SIZE
F1
OUTPUT
SIZE
F2
SCANNED
INPUT
F3
SCANNED
OUTPUT
F4
M0 FILE
SIZE
F5
M1 FILE
SIZE
F6
3. Press
[F5]
, then enter the number of M0 file words required (the required number is listed in the user manual for the specific specialty I/O module).
4. Press
[F6]
, then enter the number of M1 file words required (the required number is listed in the user manual for the specific specialty I/O module).
The specialty I/O module may require that you also configure the G file and specify an ISR (interrupt subroutine) number. These tasks are accomplished with function keys F1, F3, and F7 shown in step 1 above. G files are discussed later in this appendix.
Addressing M0-M1 Files
The addressing format for M0 and M1 files is below:
Mf:e.s/b
Where
M = module f = file type (0 or 1) e = slot (1-30) s = word (0 to max. supplied by module b = bit (0-15)
Using M0-M1 Data File Addresses
M0 and M1 data file addresses can be used in all instructions except the OSR instruction and the instruction parameters noted below:
Instruction
BSL, BSR
SQO, SQC, SQL
LFL, LFU
FFL, FFU
Parameter (uses file indicator #)
File (bit array)
File (sequencer file)
LIFO (stack)
FIFO (stack)
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Monitoring Bit Addresses
For SLC 5/02 processors, the M0/M1 Monitoring option is always disabled. (This processor does not allow you to monitor the actual state of each addressed M0/M1 address.) For SLC 5/03 and SLC 5/04 processors, you can choose to disable or enable the monitoring option by selecting
[F6]
, System Config, from the main menu.
M0/M1 Monitoring Option Disabled
When you monitor a ladder program in the Run or Test mode with the
M0/M1 Monitoring option disabled, the following bit instructions, addressed to an M0 or M1 file, are indicated as false regardless of their actual true/false logical state.
Mf:e.s
] [
b
Mf:e.s
]/[
b
Mf:e.s
( )
b
Mf:e.s
(L)
b
Mf:e.s
(U)
b
f = file (0 or 1)
When you are monitoring the ladder program in the Run or Test mod, the HHT display does not show these instructions as being true when the processor evaluates them as true.
If you need to show the state of the M0 or M1 addressed bit, you can transfer the state to an internal processor bit. This is illustrated below, where an internal processor bit is used to indicate the true/false state of a rung.
B3
] [
0
B3
] [
1
EQU
EQUAL
Source A N7:12
M0:3.0
( )
1
Source B N7:3
This rung will not show its true rung state because the EQU instruction is always shown as true and the M0 instruction is always shown as false.
B3
] [
0
B3
] [
1
EQU
EQUAL
Source A
Source B
N7:12
N7:3
B3
( )
2
M0:3.0
( )
1
OTE instruction B3/2 has been added to the rung. This instruction shows the true or false state of the rung.
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M0/M1 Monitoring Option Enabled
Important:
This option is not supported by the SLC 5/02 processor.
The SLC 5/03 and SLC 5/04 processors allows you to monitor the actual state of each addressed M0/M1 address (or data table). The highlighting appears normal when compared to the other processor data files. The processor’s performance will be degraded to the degree of M0/M1 referenced screen data. For example, if your screen has only one M0/M1 element, degradation is minimal. If your screen has 69 M0/M1 elements, degradation is significant.
Transferring Data Between Processor Files and M0 or
M1 Files
The processor does not contain an image of the M0 or M1 file. As a result, you must edit and monitor M0 and M1 file data via instructions in your ladder program. For example, you can copy a block of data from a processor data file to an M0 or M1 data file or vice versa using the COP instruction in your ladder program.
The COP instructions below copy data from a processor bit file and integer file to an M0 file. For the example, assume the data is configuration information affecting the operation of the specialty I/O module.
First scan bit. It makes this rung true only for the first scan after entering Run mode.
S:1
] [
15
COP
COPY FILE
Source
Dest
Length
#B3:0
#M0:1.0
16
COP
COPY FILE
Source
Dest
Length
#N7:0
#M0:1.16
27
The COP instruction below copies data from an M1 data file to an integer file. This technique is used to monitor the contents of an M0 or M1 data file indirectly, in a processor data file.
COP
COPY FILE
Source
Dest
Length
#M1:4.3
#N10:0
6
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Access Time
During the program scan, the processor must access the specialty I/O card to read/write M0 or M1 data. This access time must be added to the execution time of each instruction referencing M0 or M1 data.
For the SLC 5/03 and SLC 5/04 processors, the instruction types vary in their execution times.
The following table shows approximate access times per instruction or word of data for the SLC 5/02, SLC 5/03, and SLC 5/04 processors.
Processor Instruction Type
SLC 5/02 Series B All types
1
SLC 5/02 Series C All types
1
SLC 5/03 (All
Series)
XIC or XIO
OTU, OTE, or OTL
COP to M file
COP from M file
FLL
MVM to M file any source or Destination M file address
SLC 5/04 OS400 XIC or XIO
OTU, OTE, or OTL
COP to M file
COP from M file
FLL
MVM to M file any source or Destination M file address
Access Time per Bit
Instruction or Word of Data
850
694
µ
µ s s
1930
1160
782
925
--
--
--
894
730
743
879
--
--
--
µ
µ
µ
µ
µ
µ
µ
µ s s s s s s s s
1. Except the OSR instruction and the instruction parameters noted on page C-2.
Multi-Word Instruction
1580
950
--
µ
µ
Access Time per
s plus 670 s plus 400 µ
µ s per word s per word
--
772
µ s plus 23
µ s per word
760
µ s plus 22
µ s per word
753
µ s plus 30
µ s per word
--
--
--
--
735 µ s plus 23 µ s per word
722 µ s plus 22 µ s per word
716 µ s plus 30 µ s per word
--
--
SLC 5/02 Processor Example
M0:2.1
] [
1
M1:3.1
]/[
1
M0:2.1
( )
10
If you are using a SLC 5/02 Series B processor, add 1930 µs to the program scan time for each bit instruction addressed to an M0 or M1 data file. If you are using a SLC 5/03 Series C processor, add 1160
µs.
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COP
COPY FILE
Source
Dest
Length
#B3:0
#M0:1.0
34
If you are using a SLC 5/02 Series B processor, add 1580 µs plus 670
µs per word of data addressed to the M0 or M1 file. As shown above,
34 words are copied from #B3:0 to M0:1.0. Therefore, this adds
24360 µs to the scan time of the COP instruction. If you are using a
SLC 5/02 Series C processor, add 950 µs plus 400 µs per word. This adds 14550 µs to the scan time of the COP instruction.
SLC 5/03 Processor Example
COP
COPY FILE
Source
Dest
Length
#B3:0
#M0:1.0
34
The SLC 5/03 processor access times depend on the instruction type.
Consult the table on B-5 for the correct access times to add. As an example, if you use a COP to M file instruction like the one shown above, add 772 µs plus 23 µs per word. This adds 1554 µs to the SLC
5/03 processor scan time due to the COP instruction.
SLC 5/04 Processor Example
COP
COPY FILE
Source
Dest
Length
#B3:0
#M0:1.0
34
The SLC 5/04 processor access times depend on the instruction type.
Consult the table on B-5 for the correct access times to add. As an example, if you use a COP to M file instruction like the one shown above, add 735 µs plus 23 µs per word. This adds 1517 µs to the SLC
5/04 processor scan time due to the COP instruction.
Minimizing the Scan Time
You can keep the processor scan time to a minimum by economizing on the use of instructions addressing the M0 or M1 files. For example, XIC instruction M0:2.1/1 is used in rungs 1 and 2 of the figure below, adding approximately 2 ms to the scan time if you are using a SLC 5/02 Series B processor.
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1
2
M0:2.1
] [
B3
1
] [
12
M0:2.1
] [
1
B3
( )
10
B3
( )
14
XIC instructions in rungs 1 and 2 are addressed to the M0 data file. Each of these instructions adds approximately 1 ms to the scan time (SLC 5/02
Series B Processor).
In the equivalent rungs of the figure below, XIC instruction M0:2.1/1 is used only in rung 1, reducing the SLC 5/02 scan time by approximately 1 ms.
1
2
M0:2.1
] [
1
B3
] [
12
B3
] [
10
B3
( )
10
B3
( )
14
These rungs provide equivalent operation to those of figure A by substituting XlC instruction B3/10 for XlC instruction M0:2.1/1 in rung 2.
Scan time is reduced by approximately 1ms (Series B processor).
The following figure illustrates another economizing technique. The
COP instruction addresses an M1 file, adding approximately 4.29 ms to the scan time if you are using a SLC 5/02 Series B processor. Scan time economy is realized by making this rung true only periodically, as determined by clock bit S:4/8. (Clock bits are discussed in appendix B of the SLC 500 and MicroLogix 1000 Instruction Set
Reference Manual, Publication 1747-6.15.) A rung such as this might be used when you want to monitor the contents of the M1 file, but monitoring need not be on a continuous basis.
S:4/8 causes the #M1:4.3 file to update the #N10:0 file every 2.56 seconds.
S:4
] [
8
B11
[OSR]
0
COP
COPY FILE
Source
Dest
Length
#M1:4.3
#N10:0
6
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Capturing M0-M1 File Data
The first two ladder diagrams in the last section illustrate a technique allowing you to capture and use M0 or M1 data as it exists at a particular time. In the first figure, bit M0:2.1/1 could change state between rungs 1 and 2. This could interfere with the logic applied in rung 2. The second figure avoids the problem. If rung 1 is true, bit
B3/10 captures this information and places it in rung 2.
In the second example of the last section, a COP instruction is used to monitor the contents of an M1 file. When the instruction goes true, the 6 words of data in file #M1:4.3 is captured as it exists at that time and placed in file #N10.0.
Specialty I/O Modules with Retentive Memory
Certain specialty I/O modules retain the status of M0-M1 data after power is removed. See your specialty I/O module user’s manual. This means that an OTE instruction having an M0 or M1 address remains on if it is on when power is removed. A “hold-in” rung as shown below will not function as it would if the OTE instruction were nonretentive on power loss. If the rung is true at the time power is removed, the OTE instruction latches instead of dropping out. When power is again applied, the rung will be evaluated as true instead of false.
B3
] [
0
M0:2.1
] [
1
M0:2.1
( )
1
!
ATTENTION: When used with a speciality I/O module having retentive outputs, this rung can cause unexpected start-up on powerup.
You can achieve non-retentive operation by unlatching the retentive output with the first pass bit at powerup:
S:1
] [
15
B3
] [
0
M0:2.1
] [
1
M0:2.1
(U)
1
M0:2.1
( )
1
This rung is true for the first scan after powerup to unlatch M0:2.1/1.
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