Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

Product overview

4

4.1

4.2

Product overview

STM8S003K3 STM8S003F3

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual

(RM0016).

Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching for most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations

8-bit accumulator

24-bit program counter - 16-Mbyte linear memory space

16-bit stack pointer - access to a 64 K-level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address space

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.

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4.3

4.4

Product overview

SWIM

Single wire interface module for direct access to the debug module and memory programming.

The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator.

Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

R/W access to all resources by stalling the CPU

Breakpoints on all program-memory instructions (software breakpoints)

Two advanced breakpoints, 23 predefined configurations

Interrupt controller

Nested interrupts with three software priority levels

32 interrupt vectors with hardware priority

Up to 27 external interrupts on 6 vectors including TLI

Up to 37 external interrupts on 6 vectors including TLI

Trap and reset interrupts

Flash program memory and data EEPROM

8 Kbytes of Flash program single voltage Flash memory

128 bytes of true data EEPROM

User option byte area

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, the data EEPROM, and the option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of the main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page

(64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: 8 Kbytes minus UBC

User-specific boot code (UBC): Configurable up to 8 Kbytes

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Product overview STM8S003K3 STM8S003F3

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the

IAP and communication routines.

Figure 2: Flash memory organization

Option bytes

Data EEPROM (128 bytes)

UBC area

Remains write protected during IAP

Programmable area from 64 bytes(1 page) up to 8 Kbytes

(in 1 page steps)

Low density

Flash program

 

(8 Kbytes)

Program memory area

Write access possible for IAP

4.5

12/99

Read-out protection (ROP)

The read-out protection blocks reading and writing from/to the Flash program memory and the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Clock controller

The clock controller distributes the system clock (f

MASTER

) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master clock:

-

1-16 MHz high-speed external crystal (HSE)

-

Up to 16 MHz high-speed user-external clock (HSE user-ext)

-

16 MHz high-speed internal RC oscillator (HSI)

-

128 kHz low-speed internal RC (LSI)

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STM8S003K3 STM8S003F3 Product overview

Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the application.

Bit

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral clock

Bit Peripheral clock

Bit Peripheral clock

Bit Peripheral clock

PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC

PCKEN16

PCKEN15

PCKEN14

Reserved

TIM2

TIM4

PCKEN12

PCKEN11

PCKEN10

Reserved

SPI

I

2

C

PCKEN26

PCKEN25

PCKEN24

Reserved

Reserved

Reserved

PCKEN22

PCKEN21

PCKEN20

AWU

Reserved

Reserved

4.6

4.7

Power management

For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.

Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

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Product overview

4.8

4.9

4.10

STM8S003K3 STM8S003F3

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to

64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

Auto wakeup counter

Used for auto wakeup from active halt mode

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

Synchronization module to control the timer with external signals

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

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Encoder mode

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11

TIM2 - 16-bit general purpose timer

16-bit autoreload (AR) up-counter

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

3 individually configurable capture/compare channels

PWM mode

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

4.12

Timer

TIM1

TIM2

TIM4 8

TIM4 - 8-bit basic timer

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

Clock source: CPU clock

Interrupt source: 1 x overflow/update

Table 3: TIM timer features

Counter size (bits)

Prescaler

Counting mode

CAPCOM channels

Complem.

outputs

Ext.

trigger

Timer synchronization/ chaining

16

Any integer from 1 to

65536

Up/down 4 3 Yes

16

Any power of

2 from 1 to

32768

Up 3 0 No No

Any power of

2 from 1 to

128

Up 0 0 No

4.13

Analog-to-digital converter (ADC1)

The STM8S003xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 5 external multiplexed inputs channels and the following features:

The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features:

Input voltage range: 0 to V

DD

Input voltage range: 0 to V

DDA

Conversion time: 14 clock cycles

Single and continuous and buffered continuous conversion modes

Buffer size (n x 10 bits) where n = number of input channels

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Product overview STM8S003K3 STM8S003F3

Scan mode for single and continuous conversion of a sequence of channels

Analog watchdog capability with programmable upper and lower thresholds

Analog watchdog interrupt

External trigger input

Trigger from TIM1 TRGO

End of conversion (EOC) interrupt

Note: Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

4.14

4.14.1

Communication interfaces

The following communication interfaces are implemented:

UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.1 master capability

SPI : Full and half-duplex, 8 Mbit/s

I²C: Up to 400 Kbit/s

UART1

Main features

One Mbit/s full duplex SCI

SPI emulation

High precision baud rate generator

Smartcard emulation

IrDA SIR encoder decoder

LIN master mode

Single wire half duplex mode

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space)

Programmable transmit and receive baud rates up to 1 Mbit/s (f

CPU

/16) and capable of following any standard baud rate regardless of the input frequency

Separate enable bits for transmitter and receiver

Two receiver wakeup modes:

-

Address bit (MSB)

-

Idle line (interrupt)

Transmission error detection with interrupt generation

Parity control

Synchronous communication

Full duplex synchronous transfers

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SPI master operation

8-bit data communication

Maximum speed: 1 Mbit/s at 16 MHz (f

CPU

/16)

LIN master mode

Emission: Generates 13-bit synch break frame

Reception: Detects 11-bit break frame

4.14.2

4.14.3

Product overview

SPI

Maximum speed: 8 Mbit/s (f

MASTER

/2) both for master and slave

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave/master selection input pin

I²C

I²C master features:

-

Clock generation

-

Start and stop generation

I²C slave features:

-

Programmable I2C address detection

-

Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

-

Standard speed (up to 100 kHz)

-

Fast speed (up to 400 kHz)

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