Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes

Electrical characteristics

9

9.1

9.1.1

9.1.2

9.1.3

9.1.4

Electrical characteristics

STM8S003K3 STM8S003F3

Parameter conditions

Unless otherwise specified, all voltages are referred to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100 % of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

Amax

(given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ).

Typical values

Unless otherwise specified, typical data are based on T

A only as design guidelines and are not tested.

= 25 °C, V

DD

= 5 V. They are given

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in the following figure.

Figure 7: Pin loading conditions

STM8 pin

50 pF

9.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in the following figure.

46/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

Figure 8: Pin input voltage

STM8 pin

VIN

Electrical characteristics

9.2

Absolute maximum ratings

Symbol

V

DDx

- V

SS

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Ratings

Table 15: Voltage characteristics

Min

Supply voltage

(1)

-0.3

Max

6.5

Unit

V

IN

Input voltage on true open drain pins

(2)

V

SS

- 0.3

6.5

V

Input voltage on any other pin

(2)

V

SS

- 0.3

V

DD

+ 0.3

|V

DDx

- V

DD

|

Variations between different power pins

50 mV

|V

SSx

- V

SS

|

Variations between all the different ground pins

50

V

ESD

Electrostatic discharge voltage

See "Absolute maximum ratings

(electrical sensitivity)"

(1)

All power (V

DD

) and ground (V

SS

) pins must always be connected to the external power supply

(2)

I

INJ(PIN) must never be exceeded. This is implicitly insured if V

IN maximum is respected. If V cannot be respected, the injection current must be limited externally to the I

INJ(PIN) injection is induced by V

IN

>V

DD while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V

IN

IN

<V

SS

IN maximum value. A positive

. For true open-drain maximum must always be respected

Symbol

I

VDD

Ratings

Table 16: Current characteristics

Total current into V

DD power lines (source)

(2)

Max

(1)

100

Unit

mA

DocID018576 Rev 2 47/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

I

I

I

VSS

IO

INJ(PIN)

ΣI

(3) (4)

INJ(PIN)

(3)

Ratings

Total current out of V

SS ground lines (sink)

(2)

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

Injected current on NRST pin

Injected current on OSCIN pin

Injected current on any other pin

(5)

Total injected current (sum of all I/O and control pins)

(5)

Max

80

20

- 20

± 4

± 4

± 4

± 20

(1)

Unit

(1)

Data based on characterization results, not tested in production.

(2)

All power (V

DD

) and ground (V

SS

) pins must always be connected to the external supply.

(3)

I

INJ(PIN) must never be exceeded. This is implicitly insured if V

IN maximum is respected. If V

IN cannot be respected, the injection current must be limited externally to the I

INJ(PIN) maximum value. A positive injection is induced by V

IN

>V

DD while a negative injection is induced by V pads, there is no positive injection current, and the corresponding V

IN

IN

<V

SS

. For true open-drain maximum must always be respected

(4)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins

I which may potentially inject negative current. Any positive injection current within the limits specified for

INJ(PIN) and ΣI

INJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.

(5)

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI

INJ(PIN) maximum current injection on four I/O port pins of the device.

Symbol

T

STG

T

J

Table 17: Thermal characteristics

Ratings

Storage temperature range

Value

-65 to +150

Maximum junction temperature 150

Unit

°C

48/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3

Symbol

f

CPU

V

DD

VCAP

(1)

P

D

(3)

T

A

T

J

Operating conditions

Table 18: General operating conditions

Parameter

Internal CPU clock frequency

Conditions

Standard operating voltage

C

EXT

: capacitance of external capacitor

ESR of external capacitor at 1 MHz

(2)

ESL of external capacitor

TSSOP20

Power dissipation at T

A

= 85 °C for suffix 6

UFQFPN20

LQFP32

Ambient temperature for 6 suffix Maximum power dissipation version

Junction temperature range for suffix 6

Min

0

2.95

Max

16

5.5

Unit

MHz

V

470

-

-

-

-

-

-40

-40

3300

0.3

15

238

220

330

85

105 nF

Ω nH mW

°C

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

(2)

This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

(3)

To calculate P value for T

Jmax

Dmax

(T

A

), use the formula P

Dmax

=(T

Jmax

- T

A

)/Θ given in the previous table and the value for Θ

JA

JA

(see

Thermal characteristics

) with the given in

Thermal characteristics

.

DocID018576 Rev 2 49/99

Electrical characteristics STM8S003K3 STM8S003F3

f

CPU (MHz)

Functionality not guaranteed in this area

16

12

8

4

0

Figure 9: f

CPUmax versus V

DD

Functionality guaranteed

@TA-40 to 85 °C

2.95

4.0

5.0

Supply voltage

5.5

Symbol

t

VDD t

TEMP

V

IT+

V

IT-

V

HYS(BOR)

Table 19: Operating conditions at power-up/power-down

Parameter Conditions Min Typ

2 V

DD rise time rate

V

DD fall time rate

(1)

Reset release delay V

DD rising

2

Power-on reset threshold 2.6

2.7

Brown-out reset threshold

Brown-out reset hysteresis

2.5

2.65

70

Max

1.7

2.85

2.8

Unit

μs/V ms

V mV

(1)

Reset is always generated after a t

TEMP minimum ooperating voltage (V

DD delay. The application must ensure that V

DD min) when the t

TEMP delay has elapsed.

is still above the

9.3.1

VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

EXT

V

CAP pin. C

EXT to the is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH.

Figure 10: External capacitor C

EXT

C

ESR ESL

Rleak

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

50/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3.2

Supply current characteristics

The current consumption is measured as described in

Pin input voltage

.

9.3.2.1

Total current consumption in run mode

The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at V

DD or V

SS

(no load)

All peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned.

Subject to general operating conditions for V

DD and T

A

.

Symbol

Table 20: Total current consumption with code execution in run mode at V

DD

= 5 V

Parameter Conditions Typ

Max

(1)

Unit

f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz) 2.3

HSE user ext. clock (16 MHz) 2

HSI RC osc. (16 MHz) 1.7

I

DD(RUN)

Supply current in run mode, code executed from RAM f

CPU

= f

MASTER

/128 =

125 kHz f

CPU

= f

MASTER

/128 =

15.625 kHz

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

0.86

0.7

0.46

2.35

2

0.87

0.58

mA f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.41

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

=

16 MHz f

CPU

= f

MASTER

=

2 MHz

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

I

DD(RUN)

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

/128 =

125 kHz f

CPU

= f

MASTER

/128 =

15.625 kHz

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8) f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz)

(2)

4.5

4.3

3.7

0.84

0.72

0.46

0.42

0.55

4.75

4.5

1.05

0.9

0.58

0.57

mA

DocID018576 Rev 2 51/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 21: Total current consumption with code execution in run mode at V

DD

= 3.3 V

Symbol Parameter Conditions Typ

Max

(1)

Unit

f

CPU

= f

MASTER

=

16 MHz

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

Supply current in run mode, code executed from RAM f

CPU

= f

MASTER

/

128 = 125 kHz f

CPU

= f

MASTER

/

128 = 15.625 kHz

HSI RC osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

HSI RC osc. (16 MHz/8)

1.8

2

1.5

0.81

0.7

0.46

2.3

2

0.87

0.58

f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.41

0.55

I

DD(RUN) f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz) f

CPU

= f

MASTER

=

2 MHz

Supply current in run mode, code executed from Flash f

CPU

= f

MASTER

/

128 = 125 kHz f

CPU

= f

MASTER

/

128 = 15.625 kHz

HSI RC osc. (16 MHz/8) f

CPU

= f

MASTER

=

128 kHz

HSI RC osc. (16 MHz/8)

HSI RC osc. (16 MHz)

LSI RC osc. (128 kHz)

(2)

4

3.9

3.7

0.84

0.72

0.46

0.42

4.7

4.5

1.05

0.9

0.58

0.57

mA

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

52/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

9.3.2.2

Total current consumption in wait mode

Symbol

Table 22: Total current consumption in wait mode at V

DD

= 5 V

Parameter Conditions Typ

f

CPU

= f

MASTER

16 MHz

=

HSE crystal osc. (16 MHz)

HSE user ext. clock (16 MHz)

HSI RC osc. (16 MHz)

I

DD(WFI)

Supply current in wait mode f

CPU

= f

MASTER

/128 =

125 kHz

HSI RC osc. (16 MHz) f

CPU

= f

MASTER

/128 =

15.625 kHz

HSI RC osc. (16 MHz/8)

(2)

Max

(1)

Unit

1.6

1.1

0.89

1.3

1.1

0.7

0.88

0.45

0.57

mA f

CPU

= f

MASTER

=

128 kHz

LSI RC osc. (128 kHz) 0.4

0.54

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Symbol

Table 23: Total current consumption in wait mode at V

DD

= 3.3 V

Parameter Conditions Typ

Max

(1)

HSE crystal osc.

(16 MHz)

1.1

Unit

I

DD(WFI) f

CPU

= f

MASTER

=

16 MHz

HSE user ext. clock

(16 MHz)

HSI RC osc.

(16 MHz)

Supply current in wait mode f

CPU

= f

MASTER

/ 128 =

125 kHz

HSI RC osc.

(16 MHz) f

CPU

= f

MASTER

/ 128 =

15.625 kHz

HSI RC osc.

(16 MHz/8)

(2)

f

CPU

= f

MASTER

=

128 kHz

LSI RC osc.

(128 kHz)

1.1

0.89

0.7

0.45

0.4

1.3

1.1

0.88

0.57

0.54

mA

DocID018576 Rev 2 53/99

Electrical characteristics

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

STM8S003K3 STM8S003F3

9.3.2.3

Total current consumption in active halt mode

Symbol

Table 24: Total current consumption in active halt mode at V

DD

= 5 V

Conditions

Parameter

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Typ

I

DD(AH)

Supply current in active halt mode

On Operating mode

HSE crystal osc.

(16 MHz)

1030

Max at 85

°C

(1)

Unit

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

On

I

DD(AH)

Supply current in active halt mode

Off

I

DD(AH)

Supply current in active halt mode

Operating mode

Power-down mode

Power-down mode

Operating mode

Power-down mode

LSI RC osc.

(128 kHz)

200

HSE crystal osc.

(16 MHz)

970

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

150

66

10

260

200

85

20

μA

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Symbol

Table 25: Total current consumption in active halt mode at V

DD

= 3.3 V

Conditions

Parameter

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Typ

Max at

85 °C

(1)

I

DD(AH)

Supply current in active halt mode

On Operating mode

HSE crystal osc.

(16 MHz)

550

Unit

μA

54/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

I

I

DD(AH)

Supply current in active halt mode

I

DD(AH)

DD(AH)

Parameter

I

DD(AH)

Supply current in active halt mode

Conditions

Main voltage regulator

(MVR)

(2)

Flash mode

(3)

Clock source

Operating mode

LSI RC osc.

(128 kHz)

On

Off

Power-down mode

Operating mode

HSE crystal osc.

(16 MHz)

LSI RC osc.

(128 kHz)

LSI RC osc.

(128 kHz)

I

DD(AH)

Power-down mode

Typ

200

970

150

66

10

Max at

85 °C

(1)

260

200

80

18

Unit

μA

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

9.3.2.4

Symbol

I

DD(H)

Total current consumption in halt mode

Table 26: Total current consumption in halt mode at V

DD

= 5 V

Parameter Conditions Typ

Max at 85

°C

(1)

Unit

Supply current in halt mode

Flash in operating mode, HSI clock after wakeup

Flash in power-down mode, HSI clock after wakeup

63

6.0

75

20

μA

(1)

Data based on characterization results, not tested in production

Symbol

I

DD(H)

Table 27: Total current consumption in halt mode at V

DD

= 3.3 V

Parameter Conditions Typ

Max at 85

°C

(1)

Unit

Supply current in halt mode

Flash in operating mode, HSI clock after wakeup

60 75 μA

DocID018576 Rev 2 55/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter Conditions Typ

Max at 85

°C

(1)

Unit

17

Flash in power-down mode, HSI clock after wakeup

(1)

Data based on characterization results, not tested in production

4.5

9.3.2.5

Low power mode wakeup times

Table 28: Wakeup times

Symbol Parameter Conditions

t

WU(WFI)

Wakeup time from wait mode to run mode

(3)

0 to 16 MHz

Wakeup time active halt mode to run mode

(3)

Typ

Max

(1)

Unit

See note

(2)

f

CPU

= f

MASTER

= 16 MHz 0.56

MVR voltage regulator on

(4)

Flash in operating mode

(5)

HSI

(after wakeup)

1

(6)

2

(6)

Wakeup time active halt mode to run mode

(3)

t

WU(AH)

Wakeup time active halt mode to run mode

(3)

t

WU(H)

Wakeup time active halt mode to run mode

(3)

Wakeup time from halt mode to run mode

(3)

MVR voltage regulator on

(4)

Flash in power-down mode

(5)

MVR voltage regulator off

(4)

Flash in operating mode

(5)

HSI

(after wakeup)

48

(6)

MVR voltage Flash in regulator off

(4)

power-down mode

(5)

Flash in operating mode

(5)

Flash in power-down mode

(5)

HSI

(after wakeup)

3

(6)

HSI

(after wakeup)

50

52

54

(6)

μs

(1)

Data guaranteed by design, not tested in production.

(2) t

WU(WFI)

= 2 x 1/f master

+ x 1/f

CPU.

56/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3

(3)

Measured from interrupt event to interrupt vector fetch.

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

(6)

Plus 1 LSI clock depending on synchronization.

Electrical characteristics

9.3.2.6

Symbol

I

DD(R) t

RESETBL

Total current consumption and timing in forced reset state

Table 29: Total current consumption and timing in forced reset state

Parameter Conditions Typ

Max

(1)

Supply current in reset state

(2)

V

V

DD

DD

= 5 V

= 3.3 V

400

300

Reset pin release to vector fetch

150

Unit

μA

μs

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to V

SS

.

9.3.2.7

Symbol

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM4)

I

DD(UART1)

Current consumption of on-chip peripherals

Subject to general operating conditions for V

DD and T

A

.

HSI internal RC/f

CPU

= f

MASTER

= 16 MHz, V

DD

= 5 V

Table 30: Peripheral current consumption

Parameter Typ.

210

TIM1 supply current

(1)

TIM2 supply current

(1)

130

TIM4 timer supply current

(1)

50

UART1 supply current

(2)

120

I

DD(SPI)

SPI supply current

(2)

45

I

DD(I

2

C)

I

2

C supply current

(2)

65

I

DD(ADC1)

ADC1 supply current when converting

(3)

1000

DocID018576 Rev 2

Unit

μA

57/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on a differential I

DD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

(2)

Data based on a differential I

DD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling.

Not tested in production.

(3)

Data based on a differential I

DD measurement between reset configuration and continuous A/D conversions. Not tested in production.

9.3.2.8

Current consumption curves

The following figures show typical current consumption measured with code executing in

RAM.

Figure 11: Typ I

DD(RUN) vs. V

DD

HSE user external clock, f

CPU

= 16 MHz

Figure 12: Typ I

DD(RUN) vs. f

CPU

HSE user external clock, V

DD

= 5 V

58/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 13: Typ I

DD(RUN) vs. V

DD

HSI RC osc, f

CPU

= 16 MHz

Figure 14: Typ I

DD(WFI) vs. V

DD

HSE user external clock, f

CPU

= 16 MHz

DocID018576 Rev 2 59/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 15: Typ I

DD(WFI) vs. f

CPU

HSE user external clock, V

DD

= 5 V

Figure 16: Typ I

DD(WFI) vs. V

DD

HSI RC osc, f

CPU

= 16 MHz

9.3.3

External clock sources and timing characteristics

Symbol

f

HSE_ext

V

HSEH

(1)

V

HSEL

(1)

I

LEAK_HSE

HSE user external clock

Subject to general operating conditions for V

DD and T

A

.

Parameter

Table 31: HSE user external clock characteristics

Conditions Min

User external clock source frequency

0

OSCIN input pin high level voltage

OSCIN input pin low level voltage

0.7 x V

DD

V

SS

OSCIN input leakage current V

SS

V

DD

< V

IN

<

-1

Max

16

V

DD

+ 0.3 V

0.3 x V

DD

+1

Unit

M z

V

μA

60/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

(1)

Data based on characterization results, not tested in production.

Figure 17: HSE external clock source

V

HSEH

V HSEL

External clock source

OSCIN fHSE

STM8

Symbol

f

I

HSE

R

C

F

(1)

DD(HSE)

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Parameter

Table 32: HSE oscillator characteristics

Conditions Min Typ Max

External high speed oscillator frequency

1 16

Unit

MHz

Feedback resistor

Recommended load capacitance

(2)

220

20 kΩ pF

HSE oscillator power consumption

C = 20 pF, f

OSC

= 16 MHz

6 (startup)

1.6 (stabilized)

(3)

mA

C = 10 pF, f

OSC

=16 MHz

6 (startup)

1.2 (stabilized)

(3)

g m

Oscillator transconductance t

SU(HSE)

(4)

Startup time V

DD is stabilized

5

1 mA/V ms

DocID018576 Rev 2 61/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

C is approximately equivalent to 2 x crystal Cload.

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R m value. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4) t

SU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16

MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 18: HSE oscillator circuit diagram

Rm

Lm

CO

Cm

Resonator

CL1

OSCIN

CL2

Resonator

OSCOUT f HSE to core

RF gm

Consumption control

STM8

9.3.4

Symbol

f

HSI

HSE oscillator critical g

g mcrit

= (2 × Π × f

HSE

)

2 m

equation

× R m

(2Co + C)

2

R m

: Notional resistance (see crystal specification)

L m

: Notional inductance (see crystal specification)

C m

: Notional capacitance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

C

L1

= C

L2

= C: Grounded external capacitance g m

>> g mcrit

Internal clock sources and timing characteristics

Subject to general operating conditions for V

DD and T

A

.

High speed internal RC oscillator (HSI)

Parameter

Frequency

Table 33: HSI oscillator characteristics

Conditions Min Typ

16

Max Unit

MHz

62/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

I t

ACC

HSI su(HSI)

DD(HSI)

Parameter

Accuracy of HSI oscillator

Conditions

User-trimmed with

CLK_HSITRIMR register for given V

DD and T

A conditions

(1)

Min

Accuracy of HSI oscillator (factory calibrated)

V

DD

= 5 V,

25 °C ≤ T

A

≤ 85 °C

HSI oscillator wakeup time including calibration

HSI oscillator power consumption

-5

(1)

Refer to application note.

(2)

Data based on characterization results, not tested in production.

(3)

Guaranteed by design, not tested in production.

Typ

170

Max

5

1.0

1.0

250

(3)

(3)

(2)

Figure 19: Typical HSI frequency variation vs V

DD

@ 4 temperatures

Unit

%

μs

μA

DocID018576 Rev 2 63/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

f

LSI t su(LSI)

I

DD(LSI)

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for V

DD and T

A

.

Parameter

Frequency

Table 34: LSI oscillator characteristics

Typ Max

128

LSI oscillator wake-up time

7

LSI oscillator power consumption

5

Unit

kHz

μs

μA

Figure 20: Typical LSI frequency variation vs V

DD

@ 4 temperatures

9.3.5

Memory characteristics

RAM and hardware registers

Symbol Parameter

Table 35: RAM and hardware registers

Conditions

V

RM

Data retention mode

(1)

Halt mode (or reset)

Min

V

IT-max

(2)

Unit

V

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.

(2)

Refer to the Operating conditions section for the value of V

IT-max

64/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Flash program memory and data EEPROM

Symbol

Table 36: Flash program memory and data EEPROM

Parameter Conditions Typ

Min

(1)

Max

V

DD

I t t t prog erase

N

RW

RET

DD

Operating voltage (all modes, execution/ write/erase)

Standard programming time

(including erase) for byte/word/block (1 byte/

4 bytes/64 bytes)

Fast programming time for

1 block (64 bytes) f

CPU

≤ 16 MHz

Erase time for 1 block

(64 bytes)

Erase/write cycles

(2)

(program memory)

Erase/write cycles

(2)

(data memory)

Data retention (program memory) after 100 erase/write cycles at T

A

85 °C

=

Data retention (data memory) after 10 k erase/write cycles at T

A

85 °C

=

Data retention (data memory) after 100 k erase/write cycles at T

A

85 °C

=

Supply current (Flash programming or erasing for 1 to 128 bytes)

T

T

T

A

= 85 °C

RET

RET

= 55°C

= 85°C

2.95

100

100 k

20

20

1

6

3

3

2

5.5

6.6

3.33

3.33

Unit

V ms cycles years mA

DocID018576 Rev 2 65/99

Electrical characteristics STM8S003K3 STM8S003F3

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

9.3.6

Symbol

V

IL

V

IH

V hys

R pu t

R

, t

F

I lkg

I lkg ana

I lkg(inj)

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V

DD and T

A unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Parameter

Table 37: I/O static characteristics

Conditions Min

Input low level voltage

V

DD

= 5 V

-0.3 V

Typ

Input high level voltage

0.7 x

V

DD

Max

0.3 x

V

DD

V

DD

+

0.3

Unit

V

Hysteresis

(1)

Pull-up resistor

V

DD

= 5 V, V

IN

= V

SS

Rise and fall time

(10 % - 90 %)

Fast I/Os

Load = 50 pF

Standard and high sink

I/Os

Load = 50 pF

Digital input leakage current

V

SS

≤ V

IN

≤V

DD

Analog input leakage current

V

SS

≤ V

IN

≤ V

DD

Leakage current in adjacent

I/O

Injection current ±4 mA

30

700

55 80

20

(2)

125

(2)

±1

(2)

μA

±250

(2)

nA

±1

(2)

mV kΩ ns

μA

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

(2)

Data based on characterisation results, not tested in production.

66/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 21: Typical V

IL and V

IH vs V

DD

@ 4 temperatures

Figure 22: Typical pull-up resistance vs V

DD

@ 4 temperatures

DocID018576 Rev 2 67/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 23: Typical pull-up current vs V

DD

@ 4 temperatures

68/99

Symbol

Table 38: Output driving current (standard ports)

Parameter Conditions Min

Output low level with 8 pins sunk I

IO

= 10 mA,

V

DD

= 5 V

V

OL

Output low level with 4 pins sunk I

IO

= 4 mA,

V

DD

= 3.3 V

Output high level with 8 pins sourced

V

OH

Output high level with 4 pins sourced

I

IO

= 10 mA,

V

DD

= 5 V

I

IO

= 4 mA,

V

DD

= 3.3 V

2.8

2.1

(1)

Max Unit

2.0

1.0

(1)

V

(1)

Data based on characterization results, not tested in production

Symbol

V

OL

Table 39: Output driving current (true open drain ports)

Parameter Conditions Max

Output low level with 2 pins sunk

I

IO

= 10 mA, V

DD

5 V

= 1 .0

V

OL

Output low level with 2 pins sunk

I

IO

= 10 mA, V

DD

3.3 V

= 1.5

(1)

Unit

V

DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

V

OL

Parameter

Output low level with 2 pins sunk

Conditions Max

I

IO

= 20 mA, V

DD

5 V

=

2.0

(1)

Unit

(1)

Data based on characterization results, not tested in production

Symbol

V

V

V

OL

OL

OH

Table 40: Output driving current (high sink ports)

Parameter Conditions Min

Output low level with 8 pins sunk

I

IO

= 10 mA,

V

DD

= 5 V

Output low level with 4 pins sunk

Output low level with 4 pins sunk

I

IO

= 10 mA,

V

DD

= 3.3 V

I

IO

= 20 mA,

V

DD

= 5 V

Output high level with 8 pins sourced

Output high level with 4 pins sourced

Output high level with 4 pins sourced

I

IO

= 10 mA,

V

DD

= 5 V

I

IO

= 10 mA,

V

DD

= 3.3 V

I

IO

= 20 mA,

V

DD

= 5 V

4.0

2.1

3.3

(1)

(1)

Max

0.8

1.0

1.5

(1)

(1)

Unit

V

V

(1)

Data based on characterization results, not tested in production

DocID018576 Rev 2 69/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 24: Typ. V

OL

@ V

DD

= 5 V (standard ports)

Figure 25: Typ. V

OL

@ V

DD

= 3.3 V (standard ports)

70/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 26: Typ. V

OL

@ V

DD

= 5 V (true open drain ports)

Figure 27: Typ. V

OL

@ V

DD

= 3.3 V (true open drain ports)

DocID018576 Rev 2 71/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 28: Typ. V

OL

@ V

DD

= 5 V (high sink ports)

Figure 29: Typ. V

OL

@ V

DD

= 3.3 V (high sink ports)

72/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 30: Typ. V

DD

- V

OH

@ V

DD

= 5 V (standard ports)

Figure 31: Typ. V

DD

- V

OH

@ V

DD

= 3.3 V (standard ports)

DocID018576 Rev 2 73/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 32: Typ. V

DD

- V

OH

@ V

DD

= 5 V (high sink ports)

Figure 33: Typ. V

DD

- V

OH

@ V

DD

= 3.3 V (high sink ports)

9.3.7

Symbol

V

IL(NRST)

Reset pin characteristics

Subject to general operating conditions for V

DD and T

A unless otherwise specified.

Parameter

Table 41: NRST pin characteristics

Conditions Min Typ Max Unit

NRST input low

-0.3 V 0.3 x V

DD

V

74/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Unit Symbol

t t

V

V

R

IH(NRST)

OL(NRST)

PU(NRST)

I FP(NRST) t

IN FP(NRST)

OP(NRST)

Parameter

level voltage

(1)

Conditions

NRST input high level voltage

(1)

I

OL

=2 mA

NRST output low level voltage

(1)

NRST pull-up resistor

(2)

NRST input filtered pulse

(3)

NRST input not filtered pulse

(3)

NRST output pulse

(3)

Min

0.7 x V

30

500

20

DD

Typ

55

(1)

Data based on characterization results, not tested in production.

(2)

The R

PU pull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

Max

V

DD

0.5

80

75

+ 0.3

kΩ ns

μs

DocID018576 Rev 2 75/99

Electrical characteristics STM8S003K3 STM8S003F3

Figure 34: Typical NRST V

IL and V

IH vs V

DD

@ 4 temperatures

Figure 35: Typical NRST pull-up resistance vs V

DD

@ 4 temperatures

76/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Figure 36: Typical NRST pull-up current vs V

DD

@ 4 temperatures

The reset network shown in the following figure protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below V

IL

(NRST) max. (see

#unique_55/CD662

), otherwise the reset is not taken into account internally.

For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.

Figure 37: Recommended reset pin protection

External reset circuit

(optional)

0.1 µF

NRST

VDD

RPU

Filter

Internal reset

STM8

9.3.8

SPI serial peripheral interface

Unless otherwise specified, the parameters given in the following table are derived from tests t performed under ambient temperature, f

MASTER

MASTER

= 1/f

MASTER

.

frequency and V

DD supply voltage conditions.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

DocID018576 Rev 2 77/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter

SPI clock frequency f

SCK

1/ t c(SCK)

Table 42: SPI characteristics

Conditions

(1)

Min

Master mode

0

Max Unit

t t t f

SCK

1/ t c(SCK) f

SCK

1/ t c(SCK) r(SCK) f(SCK) su(NSS) t h(SO)

(3)

t h(MO)

(3)

(3)

Data output hold time

Data output hold time

SPI clock frequency

SPI clock rise and Capacitive load: C = 30 pF fall time

NSS setup time Slave mode t h(NSS)

(3)

t w(SCKH)

(3)

t w(SCKL)

(3)

t su(MI)

(3)

t su(SI)

(3)

t h(MI)

(3)

t h(SI)

(3)

t a(SO)

(3) (4)

NSS hold time Slave mode

SCK high and low Master mode time t dis(SO)

(3) (5)

Data output disable time t v(SO)

(3)

Data input setup time

Data input hold time

Data output access time

Data output valid time

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

Slave mode

(after enable edge) t v(MO)

(3)

Data output valid time

Master mode

(after enable edge)

Slave mode

(after enable edge)

Master mode

(after enable edge)

0 7

(2)

4 x t

MASTER

70 t

SCK

/

2 - 15 t

SCK

/

2 +15

5

5

7

10

25

27

11

(2)

(2)

t

8

25

3 x

MASTER

65

30

(2)

ns

MHz

MHz

78/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

(1)

Parameters are given by selecting 10 MHz I/O output frequency.

(2)

Data characterization in progress.

(3)

Values based on design simulation and/or characterization results, and not tested in production.

(4)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

(5)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 38: SPI timing diagram - slave mode and CPHA = 0

NSS input tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL)

MISO ta(SO)

OUT P UT tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN th(NSS) tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN

Figure 39: SPI timing diagram - slave mode and CPHA = 1

ai14134

NSS input tSU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 tw(SCKH) tw(SCKL)

MISO

OUT P UT ta(SO) tsu(SI)

MOSI

I NPUT tc(SCK) tv(SO)

MS B O UT th(SI)

M SB IN B I T1 IN th(SO)

BI T6 OUT th(NSS) tr(SCK) tf(SCK) tdis(SO)

LSB OUT

LSB IN ai14135

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

DocID018576 Rev 2 79/99

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

STM8S003K3 STM8S003F3

Figure 40: SPI timing diagram - master mode

(1)

tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTUT tsu(MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136

1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.

9.3.9

I

2

C interface characteristics

Symbol Parameter

Table 43: I

2

C characteristics

Standard mode I

2

C

t w(SCLL) t w(SCLH)

SCL clock low time

SCL clock high time

SDA setup time t su(SDA) t h(SDA)

SDA data hold time t r(SDA) t r(SCL)

SDA and SCL rise time t f(SDA) t f(SCL) t h(STA) t su(STA)

SDA and SCL fall time

START condition hold time 4.0

Repeated START condition setup time 4.7

Min

(2)

4.7

4.0

250

0

(3)

Max

(2)

Fast mode I

2

C

(1)

Unit

Min

1.3

0.6

100

0

(4)

(2)

Max

(2)

900

(3)

μs

1000

300

0.6

0.6

300

300 ns

μs

80/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol Parameter

Standard mode I

Min

4.0

(2)

2

C

Max

(2)

Fast mode I

2

C

(1)

Unit

Min

0.6

(2)

Max

(2)

t su(STO)

STOP condition setup time t w(STO:STA)

STOP to START condition time

(bus free)

C b

Capacitive load for each bus line

4.7

400

1.3

400

μs pF

(1) f

MASTER

, must be at least 8 MHz to achieve max fast I

2

C speed (400kHz)

(2)

Data based on standard I

2

C protocol requirement, not tested in production

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the low time

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL

Figure 41: Typical application with I

2

C bus and timing diagram

I

2

C bus

4.7k

V

DD

4.7k

V

DD

100

100

SDA

SCL

STM8S

START

SDA t f(SDA)

SCL t r(SDA) t h(STA) t w(SCLH) t w(SCLL) t su(SDA) t h(SDA) t r(SCL) t f(SCL) t su(STA)

REPEATED

START t w(STO:STA)

START t su(STO)

STOP ai17490

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.

9.3.10

10-bit ADC characteristics

Subject to general operating conditions for V

DD

, f

MASTER

, and T

A unless otherwise specified.

DocID018576 Rev 2 81/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol Parameter

f

ADC

ADC clock frequency

Table 44: ADC characteristics

Conditions Min Typ Max Unit

1 4 V

DD

=2.95 to 5.5 V

V

DD

=4.5 to 5.5 V 1 6

MHz

V

AIN

Conversion voltage range

(1)

V

SS

V

DD

V

C

ADC

Internal sample and hold capacitor t

S

(1)

Minimum sampling time f

ADC

= 4 MHz f

ADC

= 6 MHz t

STAB

Wake-up time from standby t

CONV

Minimum total conversion time

(including sampling time,

10-bit resolution) f

ADC

= 4 MHz f

ADC

= 6 MHz

3.5

2.33

3

0.75

0.5

7 pF

μs

μs

μs

μs

14 1/f

ADC

(1)

During the sample time the input capacitance C

AIN

(3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

S.

After the end of the sample time t

S

, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t

S depend on programming.

Symbol

|E

T

|

Table 45: ADC accuracy with R

AIN

< 10 kΩ , V

DD

= 5 V

Parameter Conditions Typ Max

(1)

Unit

Total unadjusted error

(2)

f

ADC

= 2 MHz 1.6

3.5

2.2

4 f

ADC

= 4 MHz f

ADC

= 6 MHz 2.4

4.5

LSB

|E

O

| Offset error

(2)

f

ADC

= 2 MHz 1.1

2.5

82/99 DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

Symbol

|E

|E

|E

G

D

L

|

|

|

Parameter

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2)

Conditions

f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 6 MHz

Typ

1.5

1.8

1.5

2.1

2.2

0.7

0.7

0.7

0.6

0.8

0.8

Max

(1)

3

3

3

3

4

1.5

1.5

1.5

1.5

2

2

Unit

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I

INJ(PIN) port pin characteristics section does not affect the ADC accuracy.

and ΣI

INJ(PIN) in the I/O

Symbol

Table 46: ADC accuracy with R

AIN

< 10 kΩ R

AIN

, V

DD

= 3.3 V

Parameter Conditions Typ Max

(1)

Unit

|E

T

| Total unadjusted error

(2)

f

ADC

= 2 MHz 1.6

3.5

1.9

4 LSB

|E

O

| Offset error

(2)

f

ADC

= 4 MHz f

ADC

= 2 MHz 1 2.5

DocID018576 Rev 2 83/99

Electrical characteristics STM8S003K3 STM8S003F3

Symbol

|E

|E

|E

G

D

L

|

|

|

Parameter

Gain error

(2)

Differential linearity error

Integral linearity error

(2)

(2)

Conditions

f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz f

ADC

= 2 MHz f

ADC

= 4 MHz

Typ

1.5

1.3

2

0.7

0.7

0.6

0.8

Max

2.5

3

3

1

1.5

1.5

2

(1)

Unit

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I

pin characteristics

does not affect the ADC accuracy.

INJ(PIN) and ΣI

INJ(PIN) in

I/O port

Figure 42: ADC accuracy characteristics

84/99

1. Example of an actual transfer curve.

2. The ideal transfer curve

DocID018576 Rev 2

STM8S003K3 STM8S003F3 Electrical characteristics

3. End point correlation line

E

T

= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

E

O

= Offset error: deviation between the first actual transition and the first ideal one.

E

G

= Gain error: deviation between the last ideal transition and the last actual one.

E

D

= Differential linearity error: maximum deviation between actual steps and the ideal one.

E

L

= Integral linearity error: maximum deviation between any actual transition and the end point correlation line.

Figure 43: Typical application with ADC

VAIN

RAIN

CAIN

AINx

VDD

VT

0.6 V

VT

0.6 V

IL

± 1 µA

10-bit A/D conversion

STM8

CADC

9.3.11

EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

9.3.11.1

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

FTB: A burst of fast transient voltage (positive and negative) is applied to V

DD and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for STMicrocontrollers).

9.3.11.2

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

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Electrical characteristics STM8S003K3 STM8S003F3

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontroller EMC performance).

Symbol

V

FESD

Parameter

Table 47: EMS data

Conditions Level/ class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

V

DD

= 3.3 V, T

A

= 25 °C, f

MASTER

= 16 MHz

(HSI clock), conforming to IEC 61000-4-2

2/B

(1)

V

EFTB

Fast transient voltage burst limits to be applied through 100 pF on V

DD and V

SS pins to induce a functional disturbance

V

DD

= 3.3 V, T

A

= 25 °C ,f

MASTER

= 16 MHz

(HSI clock),conforming to IEC 61000-4-4

4/A

(1)

(1)

Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers).

9.3.11.3

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE

IEC 61967-2 which specifies the board and the loading of each pin.

Table 48: EMI data

Conditions

Symbol Parameter

General conditions

Max f

HSE

/f

CPU

(1)

Monitored frequency band

16 MHz/ 16 MHz/

8 MHz 16 MHz

Unit

S

EMI

Peak level V

DD

= 5 V

T

A

= 25 °C

LQFP32 package

0.1 MHz to

30 MHz

30 MHz to

5

4

5

5 dBμV

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STM8S003K3 STM8S003F3 Electrical characteristics

Conditions

Symbol Parameter

General conditions

Max f

HSE

/f

CPU

(1)

Monitored frequency band

16 MHz/ 16 MHz/

8 MHz 16 MHz

Conforming to

SAE IEC

61967-2

130 MHz

130 MHz to

1 GHz

5 5

SAE EMI level

SAE EMI level

2.5

2.5

(1)

Data based on characterisation results, not tested in production.

Unit

9.3.11.4

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

9.3.11.5

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:

Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.

Table 49: ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value

(1)

Unit

V

ESD(HBM)

Electrostatic discharge voltage

(Human body model)

V

ESD(CDM)

Electrostatic discharge voltage

(Charge device model)

T

A

= 25°C, conforming to

JESD22-A114

A

T

A

LQFP32 package =

25°C, conforming to

SD22-C101

IV

4000

1000

V

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(1)

Data based on characterization results, not tested in production

9.3.11.6

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance:

A supply overvoltage (applied to each power supply pin)

A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter

Table 50: Electrical sensitivities

Conditions

LU Static latch-up class

T

A

= 25 °C

T

A

= 85 °C

Class

(1)

A

A

(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

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