Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data

Electrical characteristics

Figure 9.

f

CPUmax

versus V

DD

f

CPU

[MHz]

STM8S103x

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

16

12

8

4

0

FUNCTIONALITY

GUARANTEED

@ T

A

-40 to 125 ¬

2.95

4.0

5.0

SUPPLY VOLTAGE [V]

5.5

Table 20.

Operating conditions at power-up/power-down

Symbol Parameter Conditions Min

V t t

VDD

TEMP

V

V

IT+

IT-

HYS(BOR)

V

DD

rise time rate

V

DD

fall time rate

(1)

Reset release delay

Power-on reset threshold

Brown-out reset threshold

Brown-out reset hysteresis

V

DD

rising

2

2

2.6

2.5

Typ

2.7

2.65

70

Max

∞

∞

1.7

2.85

2.8

1.

Reset is always generated after a t

TEMP

delay. The application must ensure that V

DD minimum ooperating voltage (V

DD

min) when the t

TEMP

delay has elapsed.

is still above the

Unit

µs/V ms

V mV

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C

EXT

to the

V

CAP

pin. C

EXT

is specified in

Table 19

. Care should be taken to limit the series inductance

to less than 15 nH.

Figure 10.

External capacitor C

EXT

ESR C ESL

Rleak

1.

ESR is the equivalent series resistance and ESL is the equivalent inductance.

50/95 15441 Rev 3