Register Descriptions. Lattice Semiconductor Ethernet MAC, 10/100 and 1Gig Ethernet MAC

Below you will find brief information for Ethernet Media Access Controller 10/100 and 1Gig. This 10/100 and 1Gig Ethernet Media Access Controller allows for communication between a host processor and Ethernet networks, adhering to IEEE 802.3z standards. It supports Gigabit and Fast Ethernet modes, full- and half-duplex operation, and features configurable data bus widths and FIFO interfaces. The device also includes multicast address filtering and supports Jumbo Frames.

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Lattice Semiconductor

10/100 and 1Gig Ethernet

Media Access Controller User’s Guide

Table 4. Tri-Speed MAC Internal Registers

Register Description

Mode register

Transmit and Receive Control register

Maximum Packet Size register

Inter Packet Gap register

Tri-Speed MAC Address register 0

Tri-Speed MAC Address register 1

Tri-Speed MAC Address register 2

Mnemonic

MODE

TX_RX_CTL

MAX_PKT_SIZE

IPG_VAL

MAC_ADDR_0

MAC_ADDR_1

MAC_ADDR_2

Transmit and Receive Status TX_RX_STS

GMII Management Interface Control register GMII_MNG_CTL

GMII Management Data register

VLAN Tag Length/type register

GMII_MNG_DAT

VLAN_TAG

Multicast_table_0

Multicast_table_1

Multicast_table_2

Multicast_table_3

MLT_TAB_0

MLT_TAB_1

MLT_TAB_2

MLT_TAB_3

Multicast_table_4

Multicast_table_5

Multicast_table_6

Multicast_table_7

Pause_opcode

MLT_TAB_4

MLT_TAB_5

MLT_TAB_6

MLT_TAB_7

PAUS_OP

I/O Address

00H - 01H

02H - 03H

04H - 05H

08H - 09H

0AH - 0BH

0CH - 0DH

0EH - 0FH

12H - 13H

14H - 15H

16H - 17H

32H - 33H

22H - 23H

24H - 25H

26H - 27H

28H - 29H

2AH - 2BH

2CH - 2DH

2EH - 2FH

30H - 31H

34H - 35H

POR Value

0000H

05EEH

0048H

0000H

0080H

Register Descriptions

MODE (R/W)

Mnemonic: MODE

POR Value = 0000H

Name

Rsvd

Tx_en

Rx_en

FC_en

Gbit_en

Range

15:4

Description

Reserved.

Transmit Enable. When this bit is set, the Tx MAC is enabled to transmit frames. When reset, the

Tx MAC completes transmission of the packet currently being processed, then stops.

Receive Enable. When this bit is set, the Rx MAC is enabled to receive frames. When reset, the

Rx MAC completes reception of the packet currently being processed, then stops.

Flow-control Enable. When set, this enables the flow control functionality of the Tx MAC. This bit should be set for the Tx MAC either to pause or to transmit a PAUSE frame.

Gigabit Enable. In Gigabit mode, this bit is always high and cannot be overwritten. In 10/100 mode, this bit is always low and cannot be overwritten.

Lattice Semiconductor

10/100 and 1Gig Ethernet

Media Access Controller User’s Guide

Transmit and Receive Control (R/W)

Mnemonic: TX_RX_CTL

POR Value = 0000H

This register can be overwritten only when the Rx MAC and the Tx MAC are disabled. This register controls the various features of the MAC.

Name

Rsvd

Receive_short

Receive_brdcst

Dis_rtry

Hden

Receive_mltcst

Receive_pause

Tx_dis_fcs

Discard_fcs

Prms

Range

15:9

Description

Reserved.

Receive Short Frames. When high, enables the Rx MAC to receive frames shorter than

64 bytes.

Receive Broadcast. When high, enables the Rx MAC to receive broadcast frames

Disable Retry (10/100 mode only). When high, disables retry on collision.

Half-duplex Enable (10/100 mode only). When high, configures the Tx MAC to operate in half-duplex mode.

Receive Multicast. When high, the multicast frames will be received per the filtering rules for such frames. When low, no Multicast (except PAUSE) frames will be received.

Receive PAUSE. When set, the Rx MAC will indicate the PAUSE frame reception to the Tx

MAC. In either case, PAUSE frames are received and transferred to the FIFO.

Transmit Disable FCS. When set, the FCS field generation is disabled in the Tx MAC.

Rx Discard FCS and Pad. When set, the FCS and any of the padding bytes are stripped off the frame before it is transferred to the FIFO. When low, the entire frame is transferred as is.

Promiscuous Mode. When asserted, all filtering schemes are abandoned and the Rx

MAC receives frames with any address.

Maximum Packet Size (R/W)

Mnemonic: MAX_PKT_SIZE

POR Value = 05EEH (1518 decimal)

This register can be overwritten only when the MAC is disabled. All frames longer than the value (number of bytes) in this register will be tagged as long frames.

Name

Max_frame

Range

15:0

Description

Maximum size of the packet than can be handled by the core.

IPG (Inter Packet Gap) (R/W)

Mnemonic: IPG_VAL

POR Value = 0048H

Rsvd

IPG

Name Range

15:5

4:0

Description

Reserved.

Inter-packet gap value in units of bit time.

Lattice Semiconductor

10/100 and 1Gig Ethernet

Media Access Controller User’s Guide

MAC Address Register {0,1,2} (R/W), Set of Three

Mnemonic: MAC_ADD

POR Value = 0000H.

The MAC Address Registers 0-2 contain the Ethernet address of the port. The MAC Address Register [0] has the two bytes that are transmitted first and the MAC Address Register [2] has the two bytes that are transmitted last.

Bit[15] is transmitted first while bit[0] is transmitted last.

Name

Mac_addr

Range

15:0

Description

Ethernet address assigned to the port supported by the Tri-speed MAC.

Transmit and Receive Status (RO)

Mnemonic: TX_RX_STS

POR Value = 0000H

This register reports events that have occurred during packet reception and transmission.

Name

Rsvd

Rx_idle

Tagged_frame

Brdcst_frame

Multcst_frame

IPG_shrink

Short_frame

Long_frame

Error frame

CRC

Pause_frame

Tx_idle

Range

15:11

Description

Reserved.

Receive MAC Idle. Receive MAC in idle condition used to reset configurations by CPU interface.

Tagged Frame. Tagged frame received.

Broadcast Frame. Indicates that a Broadcast packet was received.

Multicast Frame. Indicates that a Multicast packet was received.

IPG Shrink. Received frame with shrunk IPG (IPG < 96 bit time).

Short Packet. Indicates that a packet shorter than 64 bytes has been received.

Too Long Packet. Indicates receipt of a packet longer than the maximum allowable packet size specified in the MAX_PKT_SIZE register.

Rx_er Asserted. Indicates the frame was received with the rx_er signal asserted.

CRC Error. Indicates a packet was received with a CRC error.

PAUSE Frame. Indicates a PAUSE frame was received.

Transmit MAC Idle. Transmit MAC in idle condition, used to reset configurations by CPU interface.

VLAN Tag (RO)

Mnemonic: VLAN_TAG

POR Value = 0000H.

The VLAN tag register has the VLAN TAG field of the most recent tagged frame that was received. This is a read only register.

VLAN

Name Range

15:0

Description

This field defines length/type of field of the VLAN tag when inserted into transmitted frames.

Lattice Semiconductor

10/100 and 1Gig Ethernet

Media Access Controller User’s Guide

GMII Management Register Access Control (R/W)

Mnemonic: GMII_MNG_CTL

POR Value = 0000H.

The GMII Management Access register controls the Management Interface Module. This register can be overwritten only when the interface is not busy. A write operation will be ignored when the interface is busy.

Name

Rsvd

Cmd_fin

RW_phyreg

Phy_add

Rsvd

Reg_add

Range

12:8

7:5

4:0

Description

Reserved.

Command Finished. When high, it means the interface has completed the intended operation. This bit is set to 0 when the interface is busy.

Read/Write PHY Registers

• When ‘1’ -> write operation

• When ‘0’ -> read operation

GMII PHY Address. The address of the accessed PHY Bit 12 is the most significant bit, and it is the first PHY address bit to be transmitted and received.

Reserved.

GMII Register Address. The address of the register accessed. Bit 4 is the most significant bit and is the first register address bit to be transmitted or received.

GMII Management Access Data (R/W)

Mnemonic: GMII_MNG_DAT

POR Value = 0000H.

The contents of this register will be transmitted when a write operation is to be performed. When a read operation is performed, this register will contain the value that was read from a PHY register. This register should be read only after the cmd_fin bit in the control register is set.

Name

GMII_dat

Range

15:0

Description

GMII Data. Bit 15 is the most significant bit, corresponding to bit 15 of the accessed register.

Multicast Tables (R/W), set of eight

Mnemonic: MLT_TAB_[0-7]

POR Value = 0000H.

When the core is programmed to receive multicast frames, a filtering scheme is used to decide whether the frame should be received or not. The six middle bits of the most significant byte of the CRC value, calculated for the destination address, are used as a key to the 64-bit hash table. The three most significant bits select one of the eight tables, and the three least significant bits select a bit. The frame is received only if this bit is set.

Name

Multicast_table_[0-7]

Range

15:0

Description

Multicast Table. Eight tables that make a 64-bit hash.

Key features

Compliant to IEEE 802.3z Standard
Generic Host Interface
Full-duplex Operation in Gigabit Mode
Supports Jumbo Frames up to 8192 kbytes
Reference Design for GMII to RGMII Bridge
Transmit and Receive Statistics Vector
Multicast Address Filtering
Supports VLAN Tagged Frames
Supports Full-duplex Control Using PAUSE Frames

Frequently asked questions

The configurable parameters include the operating mode (Gigabit or Fast Ethernet), the data bus width, and whether or not the optional MIIM module is included.

The Rx MAC supports various filtering methods to block unwanted frames, including filtering based on MAC address, frame length, and multicast address.

The Tx MAC supports two methods for transmitting PAUSE frames: by receiving a PAUSE frame from the network and by directly signaling the Tx MAC to transmit a PAUSE frame.