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ATmega8(L)
Two-wire Serial
Interface
Features
Two-wire Serial
Interface Bus
Definition
•
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
•
Both Master and Slave Operation Supported
•
Device can Operate as Transmitter or Receiver
•
7-bit Address Space Allows up to 128 Different Slave Addresses
•
Multi-master Arbitration Support
•
Up to 400kHz Data Transfer Speed
•
Slew-rate Limited Output Drivers
•
Noise Suppression Circuitry Rejects Spikes on Bus Lines
•
Fully Programmable Slave Address with General Call Support
•
Address Recognition Causes Wake-up When AVR is in Sleep Mode
The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol.
Figure 68. TWI Bus Interconnection
V
CC
Device 1
Device 2
Device 3 ........
Device n R1 R2
TWI Terminology
SDA
SCL
The following definitions are frequently encountered in this section.
Table 64. TWI Terminology
Term Description
Master The device that initiates and terminates a transmission. The Master also generates the SCL clock
Slave The device addressed by a Master
Transmitter The device placing data on the bus
Receiver The device reading data from the bus
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Electrical
Interconnection
As depicted in Figure 68 on page 157
, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in
“Two-wire Serial Interface Characteristics” on page 238
. Two different sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz.
Data Transfer and
Frame Format
Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions.
Figure 69. Data Validity
SDA
START and STOP
Conditions
SCL
Data Stable Data Stable
Data Change
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high.
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Figure 70. START, REPEATED START and STOP conditions
SDA
Address Packet
Format
SCL
START STOP START REPEATED START STOP
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one
READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Master’s request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or
SLA+W, respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.
The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 71. Address Packet Format
Addr MSB
SDA
Addr LSB R/W ACK
SCL
1 2 7 8 9
START
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Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 72. Data Packet Format
Data MSB
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
SLA+R/W
2 7
Data Byte
Data LSB ACK
8 9
STOP, REPEATED
START or Next
Data Byte
Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 73 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software.
Figure 73. Typical Data Transmission
Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK
SDA
SCL
START
1 2 7
SLA+R/W
8 9 1 2
Data Byte
7 8 9
STOP
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Multi-master Bus
Systems,
Arbitration and
Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, that is, the data being transferred on the bus must not be corrupted
• Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Figure 74. SCL Synchronization Between Multiple Masters
TA
low
TA
high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TB
low
Masters Start
Counting Low Period
TB
high
Masters Start
Counting High Period
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet.
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Figure 75. Arbitration Between Two Masters
START
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
Master A Loses
Arbitration, SDA
A
SDA
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit
• A STOP condition and a data bit
• A REPEATED START and a STOP condition
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
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Overview of the
TWI Module
The TWI module is comprised of several submodules, as shown in
Figure 76 . All registers drawn
in a thick line are accessible through the AVR data bus.
Figure 76. Overview of the TWI Module
SCL
Slew-rate
Control
Spike
Filter
SDA
Slew-rate
Control
Spike
Filter
START / STOP
Control
Bus Interface Unit
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Ack
Address Match Unit
Address Register
(TWAR)
Address Comparator
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Status Register
(TWSR)
Control Unit
Control Register
(TWCR)
State Machine and
Status control
SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones.
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Bit Rate Generator
Unit
Bus Interface Unit
Address Match Unit
Control Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation:
SCL frequency =
16 + 2(TWBR) 4
TWPS
• TWBR = Value of the TWI Bit Rate Register
• TWPS = Value of the prescaler bits in the TWI Status Register
Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See Table 101 on page 238 for value of pull-up resistor
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated.
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (for example,
INT0) occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts operation and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down.
The Control unit monitors the TWI bus and generates responses corresponding to settings in the
TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue.
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The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition
• After the TWI has transmitted SLA+R/W
• After the TWI has transmitted an address byte
• After the TWI has lost arbitration
• After the TWI has been addressed by own slave address or general call
• After the TWI has received a data byte
• After a STOP or REPEATED START has been received while still addressed as a Slave
• When a bus error has occurred due to an illegal START or STOP condition
TWI Register
Description
TWI Bit Rate Register
– TWBR
Bit
Read/Write
Initial Value
7 6
TWBR7 TWBR6
R/W
0
R/W
0
5 4 3
TWBR5 TWBR4 TWBR3
R/W
0
R/W
0
R/W
0
2 1
TWBR2 TWBR1
R/W
0
R/W
0
0
TWBR0
R/W
0
TWBR
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 164 for calculating bit rates.
TWI Control Register –
TWCR
Bit
Read/Write
Initial Value
7
TWINT
R/W
0
6
TWEA
R/W
0
5 4
TWSTA TWSTO
R/W
0
R/W
0
3
TWWC
R
0
2
TWEN
R/W
0
R
0
1
–
0
TWIE
R/W
0
TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
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• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met:
1.
The device’s own slave address has been received
2.
A general call has been received, while the TWGCE bit in the TWAR is set
3.
A data byte has been received in Master Receiver or Slave Receiver mode
By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the Twowire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed
Slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high.
TWI Status Register –
TWSR
Bit
Read/Write
Initial Value
7
TWS7
R
1
6
TWS6
R
1
5
TWS5
R
1
4
TWS4
R
1
3
TWS3
R
1
R
0
2
–
1
TWPS1
R/W
0
0
TWPS0
R/W
0
TWSR
• Bits 7..3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted.
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• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 65. TWI Bit Rate Prescaler
0
1
1
TWPS1
0
1
0
1
TWPS0
0
Prescaler Value
1
4
16
64
To calculate bit rates, see
“Bit Rate Generator Unit” on page 164
. The value of TWPS1..0 is used in the equation.
TWI Data Register –
TWDR
Bit
Read/Write
Initial Value
7
TWD7
R/W
1
6
TWD6
R/W
1
5
TWD5
R/W
1
4
TWD4
R/W
1
3
TWD3
R/W
1
2
TWD2
R/W
1
1
TWD1
R/W
1
0
TWD0
R/W
1
TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus.
TWI (Slave) Address
Register – TWAR
Bit
Read/Write
Initial Value
7
TWA6
R/W
1
6
TWA5
R/W
1
5
TWA4
R/W
1
4
TWA3
R/W
1
3
TWA2
R/W
1
2
TWA1
R/W
1
1
TWA0
R/W
1
0
TWGCE
R/W
0
TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated.
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• Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented.
Figure 77. Interfacing the Application to the TWI in a Typical Transmission
1. Application writes to TWCR to initiate transmission of
START
3. Check TWSR to see if START was sent. Application loads SLA+W into
TWDR, and loads appropriate control signals into TWCR, makin sure that
TWINT is written to one, and TWSTA is written to zero.
5. Check TWSR to see if SLA+W was sent and ACK received.
Application loads data into TWDR, and loads appropriate control signals into
TWCR, making sure that TWINT is written to one
7. Check TWSR to see if data was sent and ACK received.
Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one
TWI bus START SLA+W A Data A STOP
2. TWINT set.
Status code indicates
START condition sent
4. TWINT set.
Status code indicates
SLA+W sent, ACK received
6. TWINT set.
Status code indicates data sent, ACK received
Indicates
TWINT set
1.
The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition
2.
When the START condition has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the START condition has successfully been sent
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3.
The application software should now examine the value of TWSR, to make sure that the
START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on.
However, it is important that the TWINT bit is set in the value written. Writing a one to
TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in
TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet
4.
When the address packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not
5.
The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in
TWDR. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet
6.
When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent.
The status code will also reflect whether a Slave acknowledged the packet or not
7.
The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent
Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
• When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT is cleared
• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle
• After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting
In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files.
169
1
2
3
4
5
6
7
Assembly Code Example ldi
r16, (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
out
TWCR, r16 wait1:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait1
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, START
brne
ERROR
ldi
r16, SLA_W
out
TWDR, r16
ldi
r16, (1<<TWINT) | (1<<TWEN)
out
TWCR, r16 wait2:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait2
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, MT_SLA_ACK
brne
ERROR
ldi
r16, DATA
out
TWDR, r16
ldi
r16, (1<<TWINT) | (1<<TWEN)
out
TWCR, r16 wait3:
in
r16,TWCR
sbrs
r16,TWINT
rjmp
wait3
in
r16,TWSR
andi
r16, 0xF8
cpi
r16, MT_DATA_ACK
brne
ERROR
ldi
r16, (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out
TWCR, r16
C Example
TWCR = (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
while if
(!(TWCR & (1<<TWINT)))
;
((TWSR & 0xF8) != START)
ERROR();
TWDR = SLA_W;
TWCR = (1<<TWINT) | (1<<TWEN);
while if
(!(TWCR & (1<<TWINT)))
;
MT_SLA_ACK)
TWDR = DATA;
TWCR = (1<<TWINT) | (1<<TWEN);
while if
((TWSR & 0xF8) !=
ERROR();
(!(TWCR & (1<<TWINT)))
;
((TWSR & 0xF8) !=
MT_DATA_ACK)
ERROR();
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO);
Comments
Send START condition
Wait for TWINT Flag set. This indicates that the START condition has been transmitted
Check value of TWI Status
Register. Mask prescaler bits. If status different from START go to
ERROR
Load SLA_W into TWDR Register.
Clear TWINT bit in TWCR to start transmission of address
Wait for TWINT Flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received.
Check value of TWI Status
Register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR
Load DATA into TWDR Register.
Clear TWINT bit in TWCR to start transmission of data
Wait for TWINT Flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received.
Check value of TWI Status
Register. Mask prescaler bits. If status different from
MT_DATA_ACK go to ERROR
Transmit STOP condition
170
ATmega8(L)
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ATmega8(L)
Transmission
Modes
Master Transmitter
Mode
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
to Figure 85 on page 183 , circles are used to indicate that the TWINT
Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in
to
. Note that the prescaler bits are masked to zero in these tables.
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see
Figure 78 on page 172 ). In order to enter a Master mode, a START condition must be
transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
171
2486Z–AVR–02/11
Figure 78. Data Transfer in Master Transmitter Mode
V
CC
Device 1
MASTER
TRANSMITTER
Device 2
SLAVE
RECEIVER
Device 3
........
Device n R1 R2
172
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
1
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The
TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see
). In order to enter
MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
0
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in Table 66 on page 173 .
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
0
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
0
TWSTO
1
TWWC
X
TWEN
1
–
0
TWIE
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
1
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START
ATmega8(L)
2486Z–AVR–02/11
ATmega8(L)
enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
Table 66. Status codes for Master Transmitter Mode
Status Code
(TWSR)
Prescaler Bits are 0
0x08
0x10
Status of the Two-wire Serial
Bus and Two-wire Serial Interface Hardware
A START condition has been transmitted
A repeated START condition has been transmitted
To/from TWDR
Application Software Response
To TWCR
STA STO TWINT TWEA
Load SLA+W 0 0 1 X
Load SLA+W or
Load SLA+R
0
0
0
0
1
1
X
X
0x18
0x20
0x28
0x30
0x38
SLA+W has been transmitted;
ACK has been received
SLA+W has been transmitted;
NOT ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Data byte has been transmitted;
ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Data byte has been transmitted;
NOT ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action
Arbitration lost in SLA+W or data bytes
No TWDR action or
No TWDR action
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
Two-wire Serial Bus will be released and not addressed
Slave mode entered
A START condition will be transmitted when the bus becomes free
173
2486Z–AVR–02/11
Figure 79. Formats and States in the Master Transmitter Mode
MT
Successfull transmission to a slave receiver
S
$08
Next transfer started with a repeated start condition
SLA
Not acknowledge received after the slave address
W A
$18
A
$20
P
DATA A
$28
P
R
S
SLA
$10
Not acknowledge received after a data byte
Arbitration lost in slave address or data byte
Arbitration lost and addressed as slave
A or A
Other master continues
$38
A
Other master continues
$68 $78 $B0
A P
$30
A or A
Other master continues
$38
To corresponding states in slave mode
W
R
MR
From master to slave
From slave to master
DATA n
A
Any number of data bytes and their associated acknowledge bits
This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
174
ATmega8(L)
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ATmega8(L)
Master Receiver Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(see
). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master
Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 80. Data Transfer in Master Receiver Mode
V
CC
Device 1
MASTER
RECEIVER
Device 2
SLAVE
TRANSMITTER
Device 3
........
Device n R1 R2
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
1
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see
). In order to enter
MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
0
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in
. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
0
TWSTO
1
TWWC
X
TWEN
1
–
0
TWIE
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
1
TWEA
X
TWSTA
1
TWSTO
0
TWWC
X
TWEN
1
–
0
TWIE
X
175
2486Z–AVR–02/11
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
Table 67. Status codes for Master Receiver Mode
Status Code
(TWSR)
Prescaler Bits are 0
0x08
0x10
Status of the Two-wire Serial
Bus and Two-wire Serial Interface Hardware
A START condition has been transmitted
A repeated START condition has been transmitted
To/from TWDR
Application Software Response
To TWCR
STA STO TWINT TWEA
Load SLA+R 0 0 1 X
Load SLA+R or
Load SLA+W
0
0
0
0
1
1
X
X
0x38
0x40
Arbitration lost in SLA+R or NOT
ACK bit
No TWDR action or
No TWDR action
SLA+R has been transmitted;
ACK has been received
No TWDR action or
No TWDR action
0
0
0
1
0
0
0
0
1
1
1
1
0
1
X
X
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
Two-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
0x48
0x50
0x58
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag will be reset
STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset
176
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ATmega8(L)
Figure 81. Formats and States in the Master Receiver Mode
MR
Successfull reception from a slave receiver
S
$08
Next transfer started with a repeated start condition
SLA
Not acknowledge received after the slave address
Arbitration lost in slave address or data byte
Arbitration lost and addressed as slave
R A
$40
DATA
A P
$48
A or A
Other master continues
$38
A
Other master continues
$68 $78 $B0
A DATA A
$50 $58
P
R
S
SLA
$10
A
Other master continues
$38
To corresponding states in slave mode
R
W
MT
Slave Receiver Mode
From master to slave
From slave to master
DATA n
A
Any number of data bytes and their associated acknowledge bits
This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see
Figure 82 ). All the status codes mentioned in this section assume that the prescaler bits are
zero or are masked to zero.
Figure 82. Data transfer in Slave Receiver mode
V
CC
Device 1
SLAVE
RECEIVER
Device 2
MASTER
TRANSMITTER
Device 3 ........
Device n R1 R2
SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
value
TWA6 TWA5 TWA4 TWA3 TWA2
Device’s Own Slave Address
TWA1 TWA0 TWGCE
177
2486Z–AVR–02/11
The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWCR
value
TWINT
0
TWEA
1
TWSTA
0
TWSTO
0
TWWC
0
TWEN
1
–
0
TWIE
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared
(by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes.
178
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ATmega8(L)
Table 68. Status Codes for Slave Receiver Mode
Status Code
(TWSR)
Prescaler Bits are 0
0x60
0x68
0x70
Status of the Two-wire Serial Bus and Two-wire Serial Interface
Hardware
Own SLA+W has been received;
ACK has been returned
Arbitration lost in SLA+R/W as
Master; own SLA+W has been received; ACK has been returned
General call address has been received; ACK has been returned
Application Software Response
To TWCR
To/from TWDR
STA STO TWINT TWEA
No TWDR action or X 0 1 0
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
X
X
X
X
0
0
0
0
1
1
1
1
1
0
1
0
0x78
No TWDR action
No TWDR action or
X
X
0
0
1
1
1
0
0x80
0x88
Arbitration lost in SLA+R/W as
Master; General call address has been received; ACK has been returned
Previously addressed with own
SLA+W; data has been received;
ACK has been returned
Previously addressed with own
SLA+W; data has been received;
NOT ACK has been returned
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0x90
0x98
0xA0
Read data byte or
Read data byte
Previously addressed with general call; data has been received; ACK has been returned
Previously addressed with general call; data has been received; NOT ACK has been returned
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte or
Read data byte
A STOP condition or repeated
START condition has been received while still addressed as
Slave
No action
1
1
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode; no recognition of own SLA or GCA
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode; no recognition of own SLA or GCA
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; no recognition of own SLA or GCA
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
179
2486Z–AVR–02/11
Figure 83. Formats and States in the Slave Receiver Mode
Reception of the own slave address and one or more data bytes. All are acknowledged
S SLA W A DATA
$60
Last data byte received is not acknowledged
A DATA A P or S
$80 $80 $A0
A P or S
$88
Arbitration lost as master and addressed as slave
A
Reception of the general call address and one or more data bytes
General Call
$68
A DATA A DATA A P or S
Last data byte received is not acknowledged
$70 $90 $90 $A0
A P or S
$98
Arbitration lost as master and addressed as slave by general call
A
$78
From master to slave
From slave to master
DATA n
A
Any number of data bytes and their associated acknowledge bits
This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
180
ATmega8(L)
2486Z–AVR–02/11
Slave Transmitter
Mode
ATmega8(L)
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see
Figure 84 ). All the status codes mentioned in this section assume that the prescaler bits are
zero or are masked to zero.
Figure 84. Data Transfer in Slave Transmitter Mode
V
CC
Device 1
SLAVE
TRANSMITTER
Device 2
MASTER
RECEIVER
Device 3
........
Device n R1 R2
SDA
SCL
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR
value
TWA6 TWA5 TWA4 TWA3 TWA2
Device’s Own Slave Address
TWA1 TWA0 TWGCE
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
TWCR
value
TWINT
0
TWEA
1
TWSTA
0
TWSTO
0
TWWC
0
TWEN
1
–
0
TWIE
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
in the Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire
Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire
Serial Bus.
181
2486Z–AVR–02/11
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the
AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the
SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes.
Table 69. Status Codes for Slave Transmitter Mode
Status Code
(TWSR)
Prescaler Bits are 0
0xA8
Status of the Two-wire Serial Bus and Two-wire Serial Interface
Hardware
Own SLA+R has been received;
ACK has been returned
Application Software Response
To TWCR
To/from TWDR
STA STO TWINT TWEA
Load data byte or X 0 1 0
Load data byte X 0 1 1
0xB0
0xB8
0xC0
0xC8
Arbitration lost in SLA+R/W as
Master; own SLA+R has been received; ACK has been returned
Load data byte or
Load data byte
Data byte in TWDR has been transmitted; ACK has been received
Data byte in TWDR has been transmitted; NOT ACK has been received
Load data byte or
Load data byte
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
0
0
X
X
X
X
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Switched to the not addressed Slave mode; no recognition of own SLA or GCA
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; no recognition of own SLA or GCA
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free
Switched to the not addressed Slave mode; own SLA will be recognized;
GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free
182
ATmega8(L)
2486Z–AVR–02/11
ATmega8(L)
Figure 85. Formats and States in the Slave Transmitter Mode
Reception of the own slave address and one or more data bytes
S SLA R A DATA A
$A8 $B8
Arbitration lost as master and addressed as slave
A
DATA A
$C0
P or S
$B0
Last data byte transmitted.
Switched to not addressed slave (TWEA = '0')
A All 1's P or S
$C8
From master to slave
From slave to master
DATA n
A
Any number of data bytes and their associated acknowledge bits
This number (contained in TWSR) corresponds to a defined state of the Two-Wire Serial Bus. The prescaler bits are zero or masked to zero
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 70
.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
Table 70. Miscellaneous States
Status Code
(TWSR)
Prescaler Bits are 0
0xF8
0x00
Status of the Two-wire Serial
Bus and Two-wire Serial Interface Hardware
No relevant state information available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
To/from TWDR
Application Software Response
To TWCR
STA STO TWINT TWEA
No TWDR action No TWCR action
No TWDR action 0 1 1 X
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared.
183
2486Z–AVR–02/11
Combining Several
TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps:
1.
The transfer must be initiated
2.
The EEPROM must be instructed what location should be read
3.
The reading must be performed
4.
The transfer must be finished
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated in a multimaster system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer.
Figure 86. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter Master Receiver
S SLA+W A ADDRESS
S = START
Transmitted from master to slave
A Rs SLA+R A
Rs = REPEATED START
Transmitted from slave to master
DATA A P
P = STOP
Multi-master
Systems and
Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver.
Figure 87. An Arbitration Example
V
CC
Device 1
MASTER
TRANSMITTER
Device 2
MASTER
TRANSMITTER
Device 3
SLAVE
RECEIVER
........
Device n R1 R2
184
SDA
SCL
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention
ATmega8(L)
2486Z–AVR–02/11
2486Z–AVR–02/11
ATmega8(L)
• Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action
This is summarized in
Figure 88 . Possible status values are given in circles.
Figure 88. Possible Status Codes Caused by Arbitration
START SLA Data STOP
Arbitration lost in SLA Arbitration lost in Data
Own
Address / General Call received
No
Yes
Direction
Write
Read
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
68/78
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
B0
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
185
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Table of contents
- 1 Features
- 2 Pin Configurations
- 3 Overview
- 3 Block Diagram
- 4 Disclaimer
- 5 Pin Descriptions
- 5 VCC
- 5 GND
- 5 Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2
- 5 Port C (PC5..PC0)
- 5 PC6/RESET
- 5 Port D (PD7..PD0)
- 5 RESET
- 6 AVCC
- 6 AREF
- 6 ADC7..6 (TQFP and QFN/MLF Package Only)
- 7 Resources
- 7 Data Retention
- 8 About Code Examples
- 9 Atmel AVR CPU Core
- 9 Introduction
- 9 Architectural Overview
- 11 Arithmetic Logic Unit – ALU
- 11 Status Register
- 12 General Purpose Register File
- 13 The X-register, Y- register and Z-register
- 13 Stack Pointer
- 13 Instruction Execution Timing
- 14 Reset and Interrupt Handling
- 16 Interrupt Response Time
- 17 AVR ATmega8 Memories
- 17 In-System Reprogrammable Flash Program Memory
- 18 SRAM Data Memory
- 19 Data Memory Access Times
- 19 EEPROM Data Memory
- 19 EEPROM Read/Write Access
- 20 The EEPROM Address Register – EEARH and EEARL
- 20 The EEPROM Data Register – EEDR
- 20 The EEPROM Control Register – EECR
- 23 EEPROM Write during Power-down Sleep Mode
- 23 Preventing EEPROM Corruption
- 24 I/O Memory
- 25 System Clock and Clock Options
- 25 Clock Systems and their Distribution
- 25 CPU Clock – clkCPU
- 25 I/O Clock – clkI/O
- 25 Flash Clock – clkFLASH
- 26 Asynchronous Timer Clock – clkASY
- 26 ADC Clock – clkADC
- 26 Clock Sources
- 27 Crystal Oscillator
- 28 Low-frequency Crystal Oscillator
- 28 External RC Oscillator
- 30 Calibrated Internal RC Oscillator
- 31 Oscillator Calibration Register – OSCCAL
- 32 External Clock
- 32 Timer/Counter Oscillator
- 33 Power Management and Sleep Modes
- 33 MCU Control Register – MCUCR
- 34 Idle Mode
- 34 ADC Noise Reduction Mode
- 34 Power-down Mode
- 34 Power-save Mode
- 35 Standby Mode
- 35 Minimizing Power Consumption
- 35 Analog-to-Digital Converter (ADC)
- 35 Analog Comparator
- 36 Brown-out Detector
- 36 Internal Voltage Reference
- 36 Watchdog Timer
- 36 Port Pins
- 37 System Control and Reset
- 37 Resetting the AVR
- 37 Reset Sources
- 39 Power-on Reset
- 40 External Reset
- 40 Brown-out Detection
- 41 Watchdog Reset
- 41 MCU Control and Status Register – MCUCSR
- 42 Internal Voltage Reference
- 42 Voltage Reference Enable Signals and Start-up Time
- 43 Watchdog Timer
- 43 Watchdog Timer Control Register – WDTCR
- 45 Timed Sequences for Changing the Configuration of the Watchdog Timer
- 45 Safety Level 1 (WDTON Fuse Unprogrammed)
- 45 Safety Level 2 (WDTON Fuse Programmed)
- 46 Interrupts
- 46 Interrupt Vectors in ATmega8
- 49 Moving Interrupts Between Application and Boot Space
- 49 General Interrupt Control Register – GICR
- 51 I/O Ports
- 51 Introduction
- 52 Ports as General Digital I/O
- 52 Configuring the Pin
- 53 Reading the Pin Value
- 55 Digital Input Enable and Sleep Modes
- 56 Unconnected pins
- 56 Alternate Port Functions
- 58 Special Function IO Register – SFIOR
- 58 Alternate Functions of Port B
- 61 Alternate Functions of Port C
- 63 Alternate Functions of Port D
- 65 Register Description for I/O Ports
- 65 The Port B Data Register – PORTB
- 65 The Port B Data Direction Register – DDRB
- 65 The Port B Input Pins Address – PINB
- 65 The Port C Data Register – PORTC
- 65 The Port C Data Direction Register – DDRC
- 65 The Port C Input Pins Address – PINC
- 65 The Port D Data Register – PORTD
- 65 The Port D Data Direction Register – DDRD
- 65 The Port D Input Pins Address – PIND
- 66 External Interrupts
- 66 MCU Control Register – MCUCR
- 67 General Interrupt Control Register – GICR
- 67 General Interrupt Flag Register – GIFR
- 69 8-bit Timer/Counter0
- 69 Overview
- 69 Registers
- 69 Definitions
- 70 Timer/Counter Clock Sources
- 70 Counter Unit
- 70 Operation
- 70 Timer/Counter Timing Diagrams
- 71 8-bit Timer/Counter Register Description
- 71 Timer/Counter Control Register – TCCR0
- 72 Timer/Counter Register – TCNT0
- 72 Timer/Counter Interrupt Mask Register – TIMSK
- 72 Timer/Counter Interrupt Flag Register – TIFR
- 73 Timer/Counter0 and Timer/Counter1 Prescalers
- 73 Internal Clock Source
- 73 Prescaler Reset
- 73 External Clock Source
- 74 Special Function IO Register – SFIOR
- 75 16-bit Timer/Counter1
- 75 Overview
- 76 Registers
- 77 Definitions
- 77 Compatibility
- 77 Accessing 16-bit Registers
- 80 Reusing the Temporary High Byte Register
- 80 Timer/Counter Clock Sources
- 80 Counter Unit
- 81 Input Capture Unit
- 82 Input Capture Pin Source
- 83 Noise Canceler
- 83 Using the Input Capture Unit
- 83 Output Compare Units
- 85 Force Output Compare
- 85 Compare Match Blocking by TCNT1 Write
- 85 Using the Output Compare Unit
- 85 Compare Match Output Unit
- 87 Compare Output Mode and Waveform Generation
- 87 Modes of Operation
- 87 Normal Mode
- 87 Clear Timer on Compare Match (CTC) Mode
- 88 Fast PWM Mode
- 90 Phase Correct PWM Mode
- 92 Phase and Frequency Correct PWM Mode
- 94 Timer/Counter Timing Diagrams
- 96 16-bit Timer/Counter Register Description
- 96 Timer/Counter 1 Control Register A – TCCR1A
- 98 Timer/Counter 1 Control Register B – TCCR1B
- 99 Timer/Counter 1 – TCNT1H and TCNT1L
- 99 Output Compare Register 1 A – OCR1AH and OCR1AL
- 99 Output Compare Register 1 B – OCR1BH and OCR1BL
- 100 Input Capture Register 1 – ICR1H and ICR1L
- 100 Timer/Counter Interrupt Mask Register – TIMSK(1)
- 101 Timer/Counter Interrupt Flag Register – TIFR(1)
- 102 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 102 Overview
- 103 Registers
- 103 Definitions
- 103 Timer/Counter Clock Sources
- 104 Counter Unit
- 105 Output Compare Unit
- 106 Force Output Compare
- 106 Compare Match Blocking by TCNT2 Write
- 106 Using the Output Compare Unit
- 107 Compare Match Output Unit
- 108 Compare Output Mode and Waveform Generation
- 108 Modes of Operation
- 108 Normal Mode
- 109 Clear Timer on Compare Match (CTC) Mode
- 110 Fast PWM Mode
- 111 Phase Correct PWM Mode
- 112 Timer/Counter Timing Diagrams
- 114 8-bit Timer/Counter Register Description
- 114 Timer/Counter Control Register – TCCR2
- 116 Timer/Counter Register – TCNT2
- 116 Output Compare Register – OCR2
- 117 Asynchronous Operation of the Timer/Counter
- 117 Asynchronous Status Register – ASSR
- 117 Asynchronous Operation of Timer/Counter2
- 119 Timer/Counter Interrupt Mask Register – TIMSK
- 119 Timer/Counter Interrupt Flag Register – TIFR
- 120 Timer/Counter Prescaler
- 120 Special Function IO Register – SFIOR
- 121 Serial Peripheral Interface – SPI
- 125 SS Pin Functionality
- 125 Slave Mode
- 125 Master Mode
- 125 SPI Control Register – SPCR
- 126 SPI Status Register – SPSR
- 127 SPI Data Register – SPDR
- 127 Data Modes
- 129 USART
- 129 Overview
- 130 AVR USART vs. AVR UART – Compatibility
- 130 Clock Generation
- 131 Internal Clock Generation – The Baud Rate Generator
- 132 Double Speed Operation (U2X)
- 132 External Clock
- 132 Synchronous Clock Operation
- 133 Frame Formats
- 134 Parity Bit Calculation
- 134 USART Initialization
- 136 Data Transmission – The USART Transmitter
- 136 Sending Frames with 5 to 8 Data Bits
- 137 Sending Frames with 9 Data Bits
- 137 Transmitter Flags and Interrupts
- 138 Parity Generator
- 138 Disabling the Transmitter
- 138 Data Reception – The USART Receiver
- 138 Receiving Frames with 5 to 8 Data Bits
- 139 Receiving Frames with 9 Data Bits
- 141 Receive Compete Flag and Interrupt
- 141 Receiver Error Flags
- 141 Parity Checker
- 142 Disabling the Receiver
- 142 Flushing the Receive Buffer
- 142 Asynchronous Data Reception
- 142 Asynchronous Clock Recovery
- 143 Asynchronous Data Recovery
- 144 Asynchronous Operational Range
- 145 Multi-processor Communication Mode
- 145 Using MPCM
- 146 Accessing UBRRH/UCSRC Registers
- 146 Write Access
- 147 Read Access
- 148 USART Register Description
- 148 USART I/O Data Register – UDR
- 148 USART Control and Status Register A – UCSRA
- 149 USART Control and Status Register B – UCSRB
- 150 USART Control and Status Register C – UCSRC
- 152 USART Baud Rate Registers – UBRRL and UBRRHs
- 153 Examples of Baud Rate Setting
- 157 Two-wire Serial Interface
- 157 Features
- 157 Two-wire Serial Interface Bus Definition
- 157 TWI Terminology
- 158 Electrical Interconnection
- 158 Data Transfer and Frame Format
- 158 Transferring Bits
- 158 START and STOP Conditions
- 159 Address Packet Format
- 160 Data Packet Format
- 160 Combining Address and Data Packets into a Transmission
- 161 Multi-master Bus Systems, Arbitration and Synchronization
- 163 Overview of the TWI Module
- 163 SCL and SDA Pins
- 164 Bit Rate Generator Unit
- 164 Bus Interface Unit
- 164 Address Match Unit
- 164 Control Unit
- 165 TWI Register Description
- 165 TWI Bit Rate Register – TWBR
- 165 TWI Control Register – TWCR
- 166 TWI Status Register – TWSR
- 167 TWI Data Register – TWDR
- 167 TWI (Slave) Address Register – TWAR
- 168 Using the TWI
- 171 Transmission Modes
- 171 Master Transmitter Mode
- 175 Master Receiver Mode
- 177 Slave Receiver Mode
- 181 Slave Transmitter Mode
- 183 Miscellaneous States
- 184 Combining Several TWI Modes
- 184 Multi-master Systems and Arbitration
- 186 Analog Comparator
- 186 Special Function IO Register – SFIOR
- 186 Analog Comparator Control and Status Register – ACSR
- 188 Analog Comparator Multiplexed Input
- 189 Analog-to- Digital Converter
- 189 Features
- 191 Starting a Conversion
- 191 Prescaling and Conversion Timing
- 194 Changing Channel or Reference Selection
- 194 ADC Input Channels
- 194 ADC Voltage Reference
- 195 ADC Noise Canceler
- 195 Analog Input Circuitry
- 196 Analog Noise Canceling Techniques
- 196 ADC Accuracy Definitions
- 199 ADC Conversion Result
- 199 ADC Multiplexer Selection Register – ADMUX
- 200 ADC Control and Status Register A – ADCSRA
- 201 The ADC Data Register – ADCL and ADCH
- 202 Boot Loader Support – Read- While-Write Self- Programming
- 202 Boot Loader Features
- 202 Application and Boot Loader Flash Sections
- 202 Application Section
- 202 BLS – Boot Loader Section
- 202 Read-While-Write and No Read- While-Write Flash Sections
- 203 RWW – Read-While- Write Section
- 203 NRWW – No Read- While-Write Section
- 204 Boot Loader Lock Bits
- 205 Entering the Boot Loader Program
- 206 Store Program Memory Control Register – SPMCR
- 207 Addressing the Flash During Self- Programming
- 208 Self-Programming the Flash
- 209 Performing Page Erase by SPM
- 209 Filling the Temporary Buffer (Page Loading)
- 209 Performing a Page Write
- 209 Using the SPM Interrupt
- 209 Consideration While Updating BLS
- 209 Prevent Reading the RWW Section During Self-Programming
- 209 Setting the Boot Loader Lock Bits by SPM
- 210 EEPROM Write Prevents Writing to SPMCR
- 210 Reading the Fuse and Lock Bits from Software
- 210 Preventing Flash Corruption
- 211 Programming Time for Flash when using SPM
- 212 Simple Assembly Code Example for a Boot Loader
- 213 ATmega8 Boot Loader Parameters
- 215 Memory Programming
- 215 Program And Data Memory Lock Bits
- 216 Fuse Bits
- 217 Latching of Fuses
- 218 Signature Bytes
- 218 Calibration Byte
- 218 Page Size
- 219 Parallel Programming Parameters, Pin Mapping, and Commands
- 219 Signal Names
- 221 Parallel Programming
- 221 Enter Programming Mode
- 221 Considerations for Efficient Programming
- 221 Chip Erase
- 222 Programming the Flash
- 224 Programming the EEPROM
- 225 Reading the Flash
- 225 Reading the EEPROM
- 225 Programming the Fuse Low Bits
- 226 Programming the Fuse High Bits
- 226 Programming the Lock Bits
- 226 Reading the Fuse and Lock Bits
- 227 Reading the Signature Bytes
- 227 Reading the Calibration Byte
- 227 Parallel Programming Characteristics
- 230 Serial Downloading
- 230 Serial Programming Pin Mapping
- 231 Serial Programming Algorithm
- 231 Data Polling Flash
- 232 Data Polling EEPROM
- 234 SPI Serial Programming Characteristics
- 235 Electrical Characteristics
- 235 Absolute Maximum Ratings*
- 235 DC Characteristics
- 237 External Clock Drive Waveforms
- 237 External Clock Drive
- 238 Two-wire Serial Interface Characteristics
- 239 SPI Timing Characteristics
- 241 ADC Characteristics
- 242 ATmega8 Typical Characteristics
- 242 Active Supply Current
- 246 Idle Supply Current
- 249 Power-down Supply Current
- 250 Power-save Supply Current
- 251 Standby Supply Current
- 255 Pin Pull-up
- 257 Pin Driver Strength
- 261 Pin Thresholds and Hysteresis
- 265 Bod Thresholds and Analog Comparator Offset
- 268 Internal Oscillator Speed
- 274 Current Consumption of Peripheral Units
- 278 Current Consumption in Reset and Reset Pulsewidth
- 280 Register Summary
- 282 Instruction Set Summary
- 285 Ordering Information
- 286 Packaging Information
- 286 32A
- 287 28P3
- 288 32M1-A
- 289 Errata
- 289 ATmega8 Rev. D to I, M
- 291 Datasheet Revision History
- 291 Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11
- 291 Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10
- 291 Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10
- 291 Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10
- 291 Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09
- 291 Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08
- 291 Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08
- 292 Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07
- 292 Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07
- 292 Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06
- 292 Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06
- 292 Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- 293 Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- 293 Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- 293 Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- 294 Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- 294 Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- 295 Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- 295 Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- 295 Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- 295 Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- 295 Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- 295 Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- 296 Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- 297 Table of Contents