ATtiny15

ATtiny15L

I/O Port B

Unconnected Pins

Alternative Functions of

Port B

The Port B Data Register –

PORTB

All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).

Port B is a 6-bit bi-directional I/O port.

Three data memory address locations are allocated for Port B, one each for the Data

Register – PORTB, $18, Data Direction Register – DDRB, $17, and the Port B Input

Pins – PINB, $16. The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write.

Ports PB5..0 have special functions as described in the section “Pin Descriptions” on page 4. If PB5 is not configured as External Reset, it is input with no pull-up or as an

open-drain output. All I/O pins have individually selectable pull-ups, which can be overridden with pull-up disable.

The Port B output buffers on PB0 to PB4 can sink 20 mA and thus drive LED displays directly. PB5 can sink 12 mA. When pins PB0 to PB4 are used as inputs and are externally pulled low, they will source current (I

IL

) if the internal pull-ups are activated.

If some pins are unused, it is recommended to ensure that these pins have a defined level. The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to Vcc or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.

In ATtiny15L four Port B pins – PB2, PB3, PB4, and PB5 – have alternative functions as inputs for the ADC. If some Port B pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. During Power-down mode and ADC Noise Reduction mode, the Schmitt triggers of the digital inputs are disconnected on these pins. This allows an analog input voltage close to V

CC

/2 to be present during Power-down without causing excessive power consumption. The Port B pins with alternate functions are shown in Table 1 on page 4.

When the pins PB4..0 are used for the alternate function, the DDRB and PORTB Registers have to be set according to the alternate function description. When PB5 is used as

External Reset pin, the values in the corresponding DDRB and PORTB bit are ignored.

Bit

$18

Read/Write

Initial Value

R

0

7

–

R

0

6

–

R

0

5

–

4

PORTB4

R/W

0

3

PORTB3

R/WS

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

0

PORTB0

R/W

0

PORTB

The Port B Data Direction

Register – DDRB

Bit

$17

Read/Write

Initial Value

R

0

7

–

R

0

6

–

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

0

DDB0

R/W

0

DDRB

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1187H–AVR–09/07

The Port B Input Pins Address

– PINB

Bit

$16

Read/Write

Initial Value

R

0

7

–

R

0

6

–

5

PINB5

R

N/A

4

PINB4

R

N/A

3

PINB3

R

N/A

2

PINB2

R

N/A

1

PINB1

R

N/A

0

PINB0

R

N/A

PINB

The Port B Input Pins address (PINB) is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read.

PORT B as General Digital I/O

The lower five pins in Port B are equal when used as digital I/O pins.

PBn, general I/O pin: The DDBn bit in the DDRB Register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero),

PBn is configured as an input pin. If PORTBn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the

PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. Pullups for all ports can be disabled also by setting PUD-bit in the MCUCR Register.

Table 22. DDBn Effects on Port B Pins

(1)

DDBn PORTBn I/O Pull-up Comment

0

0

0

1

1

0

1

1

0

1

Input

Input

Input

Output

Output

No

No

Yes

No

No

Tri-state (High-Z)

PUD bit in the MCUCR Register is set.

PBn will source current if ext. pulled low.

PUD bit in the MCUCR Register is cleared.

Push-pull Zero Output

Push-pull One Output

Note: 1. n: 4, 3…0, pin number.

On ATtiny15L, PB5 is input or open-drain output. Because this pin is used for 12V programming, there is no ESD protection diode limiting the voltage on the pin to

V

CC

+ 0.5V. Thus, special care should be taken to ensure that the voltage on this pin does not rise above V

CC

+ 1V during normal operation. This may cause the MCU to reset or enter Programming mode unintentionally.

All Port B pins are connected to a pin change detector that can trigger the pin change

interrupt. See “Pin Change Interrupt” on page 22 for details.

Alternate Functions of Port B

The alternate pin functions of Port B are:

• RESET – PORT B, Bit 5

When the RSTDISBL Fuse is unprogrammed, this pin serves as External Reset. When the RSTDISBL Fuse is programmed, this pin is a general input pin or a open-drain output pin. If DDB5 is cleared (zero), PB5 is configured as an input pin. If DDB5 is set

(one), the pin is a open-drain output.

• SCK/INT0/T0 – PORT B, Bit 2

In Serial Programming mode, this pin serves as the serial clock input, SCK.

In Normal mode, this pin can serve as the external interrupt0 input. See the interrupt description for details on how to enable this interrupt. Note that activity on this pin will trigger the interrupt even if the pin is configured as an output.

52

ATtiny15L

1187H–AVR–09/07

1187H–AVR–09/07

ATtiny15L

In Normal mode, this pin can serve as the external counter clock input. See the

Timer/Counter0 description for further details. If external Timer/Counter clocking is selected, activity on this pin will clock the counter even if it is configured as an output.

• MISO/OC1A/AIN1 – PORT B, Bit 1

In Serial Programming mode, this pin serves as the serial data output, MISO.

In Normal mode, this pin can serve as Timer/Counter1 output compare match output

(OC1A). See the Timer/Counter1 description for further details, and how to enable the output. The OC1A pin is also the output pin for PWM mode timer function.

This pin also serves as the negative input of the On-chip Analog Comparator.

• MOSI/AIN0/AREF – PORT B, Bit 0

In Serial Programming mode, this pin serves as the serial data input, MOSI.

In Normal mode, this pin also serves as the positive input of the On-chip Analog

Comparator.

In ATtiny15L, this pin can be chosen to be the reference voltage for the ADC. Refer to

the section “The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages” for

details.

53