CHAPTER 2 REGISTERS
2.1 Control Registers
The control registers have dedicated functions such as controlling the program sequence, statuses, and stack memory. The control registers include a program counter, program status word, and stack pointer.
2.1.1 Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set.
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When the RESET signal is input, the program counter is set to the value of the reset vector table, which are located at addresses 0000H and 0001H.
Figure 2-1. Format of Program Counter
PC
15 0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
2.1.2 Program status word (PSW)
Program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
The contents of program status word are automatically stacked when an interrupt request is generated or when the PUSH PSW instruction is executed and, are automatically reset when the RETI and POP PSW instruction are executed.
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RESET input sets PSW to 02H.
Figure 2-2. Format of Program Status Word
7
IE Z 0 AC 0 0 1
0
CY
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CHAPTER 2 REGISTERS
(1) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is controlled by the interrupt mask flag for each interrupt source.
The IE flag is reset (0) when the DI instruction execution is executed or when an interrupt is acknowledged, and set (1) when the EI instruction is executed.
(2) Zero flag (Z)
When the operation result is zero, this flag is set (1); otherwise, it is reset (0).
(3) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set (1); otherwise, it is reset (0).
(4) Carry flag (CY)
This flag records an overflow or underflow upon add/subtract instruction execution. It also records the shiftout value upon rotate instruction execution, and functions as a bit accumulator during bit operation instruction execution.
2.1.3 Stack pointer (SP)
This is a 16-bit register that holds the first address of the stack area in the memory. Only the internal high-speed
RAM area can be set as the stack area.
Figure 2-3. Format of Stack Pointer
SP
15 0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory, and is incremented after read (reset) from the stack memory.
The data saved/restored as a result of each stack operation are as shown in Figures 2-4 and 2-5.
Caution Since
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RESET input makes the SP contents undefined, be sure to initialize the SP before executing an instruction.
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User’s Manual U11047EJ3V0UM00