CHAPTER 4 INSTRUCTION SET
4.1 Operation
4.1.1 Operand representation and description formats
In the operand column of each instruction, an operand is described according to the description format for operand representation of that instruction (for details, refer to the assembler specifications). When there are two or more description methods, select one of them. Uppercase characters, #, !, $ and [ ] are keywords and must be described as is. Each symbol has the following meaning.
•
# : Immediate data
•
!
: Absolute address
•
$ : Relative address
•
[ ] : Indirect address
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe #, !, $, or [ ].
For operand register description formats, r and rp, either functional names (X, A, C, etc.) or absolute names
(names in parentheses in the table below, R0, R1, R2, etc.) can be described.
Table 4-1. Operand Representation and Description Formats
Operand Description Format r rp sfr saddr saddrp addr16 addr5 word byte bit
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark
Refer to the User's Manual of each product for symbols of special function registers.
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CHAPTER 4 INSTRUCTION SET
4.1.2 Description of operation column
D:
E:
H:
L:
A:
X:
B:
C:
AX:
BC:
DE:
HL:
A register; 8-bit accumulator
X register
B register
C register
D register
E register
H register
L register
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
PC:
SP:
Program counter
Stack pointer
PSW: Program status word
CY: Carry flag
AC:
Z:
Auxiliary carry flag
Zero flag
IE: Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses
X
H
, X
L
: Higher 8 bits and lower 8 bits of 16-bit register
∧
:
∨
:
∨
:
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
: Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value)
4.1.3 Description of flag column
(Blank): Not affected
0: Cleared to 0
1:
×
:
R:
Set to 1
Set/cleared according to the result
Previously saved value is restored
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CHAPTER 4 INSTRUCTION SET
4.1.4 Description of clock column
The number of clock cycles during instruction execution is outlined as follows.
One instruction clock cycle is equal to one CPU clock cycle (f
CPU
) selected by the processor clock control register
(PCC).
The operation list is shown below.
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4.1.5 Operation list
Mnemonic Operand Byte Clock Operation Flag
Z AC CY
MOV
XCH
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, X
A, r
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL + byte] r, #byte saddr, #byte sfr, #byte
A, r r, A
A, saddr saddr, A
A, sfr sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
Notes 1. Except r = A.
2. Except r = A, X.
Note 1
Note 1
Note 2
2
2
1
2
2
2
1
1
1
1
2
1
1
2
2
3
3
2
3
2
2
2
2
3
2
3
3
6 r
←
byte
6 (saddr)
←
byte
6 sfr
←
byte
4 A
←
r
4 r
←
A
4 A
←
(saddr)
4 (saddr)
←
A
4 A
←
sfr
4 sfr
←
A
8 A
←
(addr16)
8 (addr16)
←
A
6 PSW
←
byte
4 A
←
PSW
4 PSW
←
A
6 A
←
(DE)
6 (DE)
←
A
6 A
←
(HL)
6 (HL)
←
A
6 A
←
(HL + byte)
6 (HL + byte)
←
A
4 A
↔
X
6 A
↔
r
6 A
↔
(saddr)
6 A
↔
sfr
8 A
↔
(DE)
8 A
↔
(HL)
8 A
↔
(HL + byte)
× × ×
× × ×
Remark
One instruction clock cycle is equal to one CPU clock (f
CPU
) cycle selected by the processor clock control register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic Operand Byte Clock Operation Flag
Z AC CY
MOVW
XCHW
ADD
ADDC rp, #word
AX, saddrp saddrp, AX
AX, rp rp, AX
AX, rp
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
Note
Note
Note
SUB
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Note Only when rp = BC, DE, or HL.
3
2
2
2
2
3
3
1
2
2
2
3
1
1
2
1
3
2
3
1
2
2
2
2
3
1
2
6 rp
←
word
6 AX
←
(saddrp)
8 (saddrp)
←
AX
4 AX
←
rp
4 rp
←
AX
8 AX
↔
rp
4 A, CY
←
A + byte
6 (saddr), CY
←
(saddr) + byte
4 A, CY
←
A + r
4 A, CY
←
A + (saddr)
8 A, CY
←
A + (addr16)
6 A, CY
←
A + (HL)
6 A, CY
←
A + (HL + byte)
4 A, CY
←
A + byte + CY
6 (saddr), CY
←
(saddr) + byte + CY
4 A, CY
←
A + r + CY
4 A, CY
←
A + (saddr) + CY
8 A, CY
←
A + (addr16) + CY
6 A, CY
←
A + (HL) + CY
6 A, CY
←
A + (HL + byte) + CY
4 A, CY
←
A – byte
6 (saddr), CY
←
(saddr) – byte
4 A, CY
←
A – r
4 A, CY
←
A – (saddr)
8 A, CY
←
A – (addr16)
6 A, CY
←
A – (HL)
6 A, CY
←
A – (HL + byte)
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
Remark
One instruction clock cycle is equal to one CPU clock (f
CPU
) cycle selected by the processor clock control register (PCC).
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Mnemonic Operand Byte Clock Operation Flag
SUBC
AND
OR
XOR
CMP
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4 A, CY
←
A – byte – CY
6 (saddr), CY
←
(saddr) – byte – CY
4 A, CY
←
A – r – CY
4 A, CY
←
A – (saddr) – CY
8 A, CY
←
A – (addr16) – CY
6 A, CY
←
A – (HL) – CY
6 A, CY
←
A – (HL + byte) – CY
4 A
←
A
∧ byte
6 (saddr)
←
(saddr)
∧ byte
4 A
←
A
∧ r
4 A
←
A
∧
(saddr)
8 A
←
A
∧
(addr16)
6 A
←
A
∧
(HL)
6 A
←
A
∧
(HL + byte)
4 A
←
A
∨ byte
6 (saddr)
←
(saddr)
∨ byte
4 A
←
A
∨ r
4 A
←
A
∨
(saddr)
8 A
←
A
∨
(addr16)
6 A
←
A
∨
(HL)
6 A
←
A
∨
(HL + byte)
4 A
←
A
∨ byte
6 (saddr)
←
(saddr)
∨ byte
4 A
←
A
∨ r
4 A
←
A
∨
(saddr)
8 A
←
A
∨
(addr16)
6 A
←
A
∨
(HL)
6 A
←
A
∨
(HL + byte)
4 A – byte
6 (saddr) – byte
4 A – r
4 A – (saddr)
8 A – (addr16)
6 A – (HL)
6 A – (HL + byte)
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
Remark
One instruction clock cycle is equal to one CPU clock (f
CPU
) cycle selected by the processor clock control register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic Operand Byte Clock Operation Flag
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
CALL
CALLT r r
AX, #word
AX, #word
AX, #word saddr saddr rp rp
A, 1
A, 1
A, 1
A, 1 saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
!addr16
[addr5]
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
3
1
6 AX, CY
←
AX + word
6 AX, CY
←
AX – word
6 AX – word
4 r
←
r + 1
4 (saddr)
←
(saddr) + 1
4 r
←
r – 1
4 (saddr)
←
(saddr) – 1
4 rp
←
rp + 1
4 rp
←
rp – 1
2 (CY, A
7
←
A
0
, A m–1
←
A m
)
×
1
2 (CY, A
0
←
A
7
, A m+1
←
A m
)
×
1
2 (CY
←
A
0
, A
7
←
CY, A m–1
←
A m
)
×
1
2 (CY
←
A
7
, A
0
←
CY, A m+1
←
A m
)
×
1
6 (saddr.bit)
←
1
6 sfr.bit
←
1
4 A.bit
←
1
6 PSW.bit
←
1
10 (HL).bit
←
1
6 (saddr.bit)
←
0
6 sfr.bit
←
0
4 A.bit
←
0
6 PSW.bit
←
0
10 (HL).bit
←
0
2 CY
←
1
2 CY
←
0
2
CY
←
_____
CY
6 (SP – 1)
←
(PC + 3)
H
, (SP – 2)
←
(PC + 3)
L
,
PC
←
addr16, SP
←
SP – 2
8 (SP – 1)
←
(PC + 1)
H
, (SP – 2)
←
(PC + 1)
L
,
PC
H
←
(00000000, addr5 + 1),
PC
L
←
(00000000, addr5), SP
←
SP – 2
Z AC CY
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
×
×
×
×
× × ×
× × ×
1
0
×
Remark
One instruction clock cycle is equal to one CPU clock (f
CPU
) cycle selected by the processor clock control register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic Operand Byte Clock Operation Flag
Z AC CY
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
PSW rp
PSW rp
SP,AX
AX,SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16 saddr, $addr16
4
3
2
4
2
2
1
2
3
2
2
2
1
1
1
1
2
3
4
2
4
3
4
4
3
1
1
3
1
1
1
6 PC
H
←
(SP + 1), PC
L
←
(SP), SP
←
SP + 2
8 PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3, NMIS
←
0
2 (SP – 1)
←
PSW, SP
←
SP – 1
4 (SP – 1)
←
rp
H
, (SP – 2)
←
rp
L
, SP
←
SP – 2
4 PSW
←
(SP), SP
←
SP + 1
6 rp
H
←
(SP + 1), rp
L
←
(SP), SP
←
SP + 2
8 SP
←
AX
6 AX
←
SP
6 PC
←
addr16
6 PC
←
PC + 2 + jdisp8
6 PC
H
←
A, PC
L
←
X
6 PC
←
PC + 2 + jdisp8 if CY = 1
6 PC
←
PC + 2 + jdisp8 if CY = 0
6 PC
←
PC + 2 + jdisp8 if Z = 1
6 PC
←
PC + 2 + jdisp8 if Z = 0
10 PC
←
PC + 4 + jdisp8 if (saddr.bit) = 1
10 PC
←
PC + 4 + jdisp8 if sfr.bit = 1
8 PC
←
PC + 3 + jdisp8 if A.bit = 1
10 PC
←
PC + 4 + jdisp8 if PSW.bit = 1
10 PC
←
PC + 4 + jdisp8 if (saddr.bit) = 0
10 PC
←
PC + 4 + jdisp8 if sfr.bit = 0
8 PC
←
PC + 3 + jdisp8 if A.bit = 0
10 PC
←
PC + 4 + jdisp8 if PSW.bit = 0
6 B
←
B – 1, then PC
←
PC + 2 + jdisp8 if B
≠
0
6 C
←
C – 1, then PC
←
PC + 2 + jdisp8 if C
≠
0
8 (saddr)
←
(saddr) – 1, then
PC
←
PC + 3 + jdisp8 if (saddr)
≠
0
2 No Operation
6 IE
←
1 (Enable Interrupt)
6 IE
←
0 (Disable Interrupt)
2 Set HALT Mode
2 Set STOP Mode
R R R
R R R
Remark
One instruction clock cycle is equal to one CPU clock (f
CPU
) cycle selected by the processor clock control register (PCC).
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CHAPTER 4 INSTRUCTION SET
4.1.6 Instruction list by addressing
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd operand
#byte
1st operand
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP r
A r sfr saddr !addr16
PSW [DE] [HL]
[HL + byte]
$addr16
MOV MOV
Note
MOV
Note
XCH
Note
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1
ROR
ROL
RORC
ROLC
None
INC
DEC
B, C sfr saddr
DBNZ
DBNZ INC
DEC
!addr16
PSW
MOV MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
MOV MOV PUSH
POP
[DE]
[HL]
MOV
MOV
[HL + byte] MOV
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
AX rp
Note
saddrp 2nd operand
1st operand
AX rp
#word
ADDW
SUBW
CMPW
MOVW MOVW
Note
MOVW
XCHW
MOVW MOVW
SP None
INCW
DECW
PUSH
POP saddrp
SP
MOVW
MOVW
Note Only when rp = BC, DE, HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd operand
1st operand
A.bit
sfr.bit
saddr.bit
PSW.bit
BT
BF
BT
BF
BT
BF
BT
BF
[HL].bit
$saddr
CY
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
None
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CHAPTER 4 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, DBNZ
!addr16
2nd operand
1st operand
Basic instructions BR
AX
CALL
BR
[addr5]
CALLT
Compound instructions
$addr16
BR
BC
BNC
BZ
BNZ
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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