CHAPTER 4 INSTRUCTION SET
4.2 Instruction Codes
4.2.1 Description of instruction code table
r
R
2
1
1
1
1
0
0
0
0
R
1
1
1
0
0
1
1
0
0
R
0
0
1
0
1
0
1
0
1
R4
R5
R6
R7
R0
R1
R2
R3 reg
L
H
E
D
C
B
X
A rp
P
1
1
1
0
0
P
0
0
1
0
1 reg-pair
RP0 AX
RP1 BC
RP2 DE
RP3 HL
Bn:
Data:
Immediate data corresponding to “bit”
8-bit immediate data corresponding to “byte”
Low/High byte: 16-bit immediate data corresponding to “word”
Saddr-offset: 16-bit address lower 8-bit offset data corresponding to “saddr”
Sfr-offset: sfr 16-bit address lower 8-bit offset data
Low/High addr: 16-bit immediate data corresponding to “addr16” jdisp: Signed two's complement data (8 bits) of relative address distance between the start and branch addresses of the next instruction ta
4 to 0
: 5 bits of immediate data corresponding to “addr5”
User’s Manual U11047EJ3V0UM00
51
CHAPTER 4 INSTRUCTION SET
4.2.2 Instruction code list
Mnemonic Operand Instruction Code
B1 B2
MOV
XCH
MOVW r, #byte saddr, #byte sfr, #byte
A, r r, A
A, saddr saddr, A
A, sfr sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
[DE], A
Note 1
Note 1
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, X
A, r
A, saddr
A, sfr
Note 2
A, [DE]
A, [HL]
A, [HL + byte] rp, #word
AX, saddrp saddrp, AX
AX, rp rp, AX
AX, rp
Note 3
Note 3
Note 3
0 0 0 0 1 0 1 0 1 1 1 1 R
2
R
1
R
0
1
1 1 1 1 0 1 0 1 Saddr-offset
1 1 1 1 0 1 1 1 Sfr-offset
0 0 0 0 1 0 1 0 0 0 1 0 R
2
R
1
R
0
1
0 0 0 0 1 0 1 0 1 1 1 0 R
2
R
1
R
0
1
0 0 1 0 0 1 0 1 Saddr-offset
1 1 1 0 0 1 0 1
0 0 1 0 0 1 1 1
Saddr-offset
Sfr-offset
1 1 1 0 0 1 1 1
0 0 1 0 1 0 0 1
Sfr-offset
Low addr
1 1 1 0 1 0 0 1 Low addr
1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0
1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0
0 0 1 0 1 0 1 1
1 1 1 0 1 0 1 1
0 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1
0 0 1 0 1 1 0 1
1 1 1 0 1 1 0 1
Data
Data
1 1 0 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0 0 0 R
2
R
1
R
0
1
0 0 0 0 0 1 0 1
0 0 0 0 0 1 1 1
0 0 0 0 1 0 1 1
0 0 0 0 1 1 1 1
Saddr-offset
Sfr-offset
0 0 0 0 1 1 0 1
1 1 1 1 P
1
P
0
0 0
1 1 0 1 0 1 1 0
1 1 1 0 0 1 1 0
1 1 0 1 P
1
P
0
0 0
1 1 1 0 P
1
P
0
0 0
1 1 0 0 P
1
P
0
0 0
Data
Low byte
Saddr-offset
Saddr-offset
XCHW
Notes 1. Except r = A.
2. Except r = A, X.
3. Only when rp = BC, DE, or HL.
B3
Data
Data
Data
High addr
High addr
Data
High byte
52
User’s Manual U11047EJ3V0UM00
B4
CHAPTER 4 INSTRUCTION SET
Mnemonic Operand
ADD
ADDC
SUB
SUBC
AND
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
Instruction Code
B1 B2
1 0 0 0 0 0 1 1
1 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1
1 0 0 0 1 1 1 1
Data
Saddr-offset
0 0 0 0 1 0 1 0 1 0 0 0 R
2
R
1
R
0
1
1 0 0 0 0 1 0 1 Saddr-offset
Low addr
1 0 0 0 1 1 0 1
1 0 1 0 0 0 1 1
Data
Data
1 0 1 0 0 0 0 1 Saddr-offset
0 0 0 0 1 0 1 0 1 0 1 0 R
2
R
1
R
0
1
1 0 1 0 0 1 0 1
1 0 1 0 1 0 0 1
Saddr-offset
Low addr
1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1
1 0 0 1 0 0 1 1
1 0 0 1 0 0 0 1
Data
Data
Saddr-offset
0 0 0 0 1 0 1 0 1 0 0 1 R
2
R
1
R
0
1
1 0 0 1 0 1 0 1 Saddr-offset
1 0 0 1 1 0 0 1
1 0 0 1 1 1 1 1
1 0 0 1 1 1 0 1
1 0 1 1 0 0 1 1
Low addr
Data
Data
1 0 1 1 0 0 0 1 Saddr-offset
0 0 0 0 1 0 1 0 1 0 1 1 R
2
R
1
R
0
1
1 0 1 1 0 1 0 1
1 0 1 1 1 0 0 1
Saddr-offset
Low addr
1 0 1 1 1 1 1 1
1 0 1 1 1 1 0 1
0 1 1 0 0 0 1 1
0 1 1 0 0 0 0 1
Data
Data
Saddr-offset
0 0 0 0 1 0 1 0 0 1 1 0 R
2
R
1
R
0
1
0 1 1 0 0 1 0 1
0 1 1 0 1 0 0 1
0 1 1 0 1 1 1 1
0 1 1 0 1 1 0 1
Saddr-offset
Low addr
Data
B3
Data
High addr
Data
High addr
Data
High addr
Data
High addr
Data
High addr
B4
User’s Manual U11047EJ3V0UM00
53
CHAPTER 4 INSTRUCTION SET
Mnemonic Operand
INCW
DECW
ROR
ROL
RORC
ROLC
OR
XOR
CMP
ADDW
SUBW
CMPW
INC
DEC
A, 1
A, 1
A, 1
A, 1 r saddr rp rp
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word r saddr
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte saddr, #byte
A, r
A, saddr
Instruction Code
B1 B2
0 1 1 1 0 0 1 1
0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1
0 1 1 1 1 1 1 1
Data
Saddr-offset
0 0 0 0 1 0 1 0 0 1 1 1 R
2
R
1
R
0
1
0 1 1 1 0 1 0 1 Saddr-offset
Low addr
0 1 1 1 1 1 0 1
0 1 0 0 0 0 1 1
Data
Data
0 1 0 0 0 0 0 1 Saddr-offset
0 0 0 0 1 0 1 0 0 1 0 0 R
2
R
1
R
0
1
0 1 0 0 0 1 0 1
0 1 0 0 1 0 0 1
Saddr-offset
Low addr
0 1 0 0 1 1 1 1
0 1 0 0 1 1 0 1
0 0 0 1 0 0 1 1
0 0 0 1 0 0 0 1
Data
Data
Saddr-offset
0 0 0 0 1 0 1 0 0 0 0 1 R
2
R
1
R
0
1
0 0 0 1 0 1 0 1 Saddr-offset
B3
Data
High addr
Data
High addr
Data
0 0 0 1 1 0 0 1
0 0 0 1 1 1 1 1
0 0 0 1 1 1 0 1
1 1 0 1 0 0 1 0
1 1 0 0 0 0 1 0
1 1 1 0 0 0 1 0
Low addr
Data
Low byte
Low byte
Low byte
0 0 0 0 1 0 1 0 1 1 0 0 R
2
R
1
R
0
1
1 1 0 0 0 1 0 1 Saddr-offset
0 0 0 0 1 0 1 0 1 1 0 1 R
2
R
1
R
0
1
1 1 0 1 0 1 0 1 Saddr-offset
1 0 0 0 P
1
P
0
0 0
1 0 0 1 P
1
P
0
0 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0
High addr
High byte
High byte
High byte
B4
54
User’s Manual U11047EJ3V0UM00
CHAPTER 4 INSTRUCTION SET
Mnemonic Operand
SET1
CLR1
BC
BNC
BZ
BNZ
BT
SET1
CLR1
NOT1
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
PSW rp
PSW rp
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
PSW.bit
[HL].bit
CY
CY
CY
!addr16
[addr5] saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
Instruction Code
B1 B2 B3
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
1 0 1 0
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
0 1 1 0
Saddr-offset
Sfr-offset
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
0 0 1 0
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
1 1 1 0
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
1 0 1 0
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
0 1 1 0
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
0 0 1 0
Saddr-offset
Sfr-offset
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
1 1 1 0
0 0 0 1 0 1 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 1 1 0
0 0 1 0 0 0 1 0
0 1 ta
4 to 0
0
0 0 1 0 0 0 0 0
0 0 1 0 0 1 0 0
0 0 1 0 1 1 1 0
Low addr High addr
1 0 1 0 P
1
P
0
1 0
0 0 1 0 1 1 0 0
1 0 1 0 P
1
P
0
0 0
1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0
1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0
1 0 1 1 0 0 1 0 Low addr
0 0 1 1 0 0 0 0
1 0 1 1 0 0 0 0 jdisp
High addr
0 0 1 1 1 0 0 0
0 0 1 1 1 0 1 0
0 0 1 1 1 1 0 0
0 0 1 1 1 1 1 0 jdisp jdisp jdisp jdisp
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
1 0 0 0
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
0 1 0 0
Saddr-offset
Sfr-offset
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
0 0 0 0 jdisp
0 0 0 0 1 0 1 0 1 B
2
B
1
B
0
1 0 0 0 0 0 0 1 1 1 1 0
B4 jdisp jdisp jdisp
User’s Manual U11047EJ3V0UM00
55
CHAPTER 4 INSTRUCTION SET
NOP
EI
DI
HALT
STOP
Mnemonic
BF
DBNZ
Operand saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16 saddr, $addr16
Instruction Code
B1 B2 B3
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
1 0 0 0
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
0 1 0 0
Saddr-offset
Sfr-offset
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
0 0 0 0 jdisp
0 0 0 0 1 0 1 0 0 B
2
B
1
B
0
1 0 0 0 0 0 0 1 1 1 1 0
0 0 1 1 0 1 1 0
0 0 1 1 0 1 0 0
0 0 1 1 0 0 1 0
0 0 0 0 1 0 0 0 jdisp jdisp
Saddr-offset jdisp
0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 1 0 0
0 0 0 0 1 1 1 0
B4 jdisp jdisp jdisp
56
User’s Manual U11047EJ3V0UM00
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
This chapter explains the instructions of 78K/0S Series. Each instruction is described in the unit of mnemonic, including description of multiple operands.
The basic configuration of instruction descriptions is shown on the next page.
For the number of instruction bytes and operation codes, refer to CHAPTER 4 INSTRUCTION SET.
All the instructions are common to 78K/0S Series products.
User’s Manual U11047EJ3V0UM00
57
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
MOV
Mnemonic
[Instruction format]
[Operation]
[Operand]
DESCRIPTION EXAMPLE
Full name
Move
Byte Data Transfer
Meaning of instruction
MOV dst, src: Indicates the basic description format of the instruction.
dst
←
src: Indicates instruction operation using symbols.
Indicates operands that can be specified with this instruction. Refer to 4.1 Operation for a description of each operand symbol.
Mnemonic
MOV
Operand (dst, src) r, #byte
A, saddr saddr, A
PSW, #byte
Mnemonic
MOV
Operand (dst, src)
A, PSW
[HL], A
A, [HL + byte]
[HL + C], A
[Flag]
Z AC
Indicates the operation of the flag that changes by instruction execution.
Each flag operation symbol is shown in the legend.
CY
Symbol
Blank
0
1
×
R
Legend
Description
Unchanged
Cleared to 0
Set to 1
Set or cleared according to the result
Previously saved value is restored
[Description] Describes the instruction operation in detail.
•
The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand.
[Description example]
MOV A, #4DH; 4DH is transferred to A register.
58
User’s Manual U11047EJ3V0UM00