SSD1303

7.6 MPU Serial Interface

The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as

SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins can be connected to external ground.

SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D

7

, D

6

, ... D

0

. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock.

During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to

Figure 6.

Figure 6 – Display data write procedure in SPI mode

CS#

D/C

SDIN/

SCLK

DB1 DB2 DBn NOP COMMAND

SCLK(D0)

SDIN(D1) D7 D6 D5 D4 D3 D2 D1 D0

7.7 Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is

132 x 64 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software.

For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display.

7.8 Current Control and Voltage Control

This block is used to derive the incoming power sources into different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive the driving voltage for segments and commons. IREF is a reference current source for segment current drivers.

SSD1303

Rev 1.7 P 17/56 May 2005

Solomon Systech

7.9 Segment Drivers / Common Drivers

Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted from

0 to 300uA with 256 steps. Common drivers generate voltage scanning pulses.

7.10 Area Colour Decoder

Page 0 and Page 1 of the display are divided into 32 banks. Bank16 and Bank32 comprise of a display area of 12 x 8 pixels. Other banks (0~15 & 17~31) have matrices of 8 x 8 pixels. Each bank can be programmed to any one of the four colours (colour A, B, C, D). Detailed operation can be referred to the Command

Table.

Page 0, bank

1 Page 0, bank 16

Page 1, bank

17

Page 1, bank 32

Bank 0 (background)

Page 2 – Page 7

Solomon Systech

May 2005 P 18/56 Rev 1.7

SSD1303

7.11 DC-DC Voltage Converter

It is a switching voltage generator circuit, designed for handheld applications. In SSD1303, internal DC-DC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply V

CC

from a low voltage supply input V

DD

. V

CC

is the voltage supply to the OLED driver block. Below application circuit is an example for the input voltage of 3V VDD to generate V

CC

of 12V

@0mA ~ 20mA application.

Figure 7 - DC-DC voltage converter circuit

L1

VDD

+

D1

VCC

C5

AGND

Q1

VDDB GDR

R1

+

C6

VBREF RESE

+

C7

+

C2

+

C3

+

C1

R3

VSSB FB

AGND

+

C4

R2

AGND

Remark:

1.

2.

3.

4.

DGND

VSSB is tied to VSS on SSD1303T3 package.

L1, D1, Q1, C5 should be grouped closed together on PCB layout.

R1, R2, C1, C4 should be grouped closed together on PCB layout.

The VCC output voltage level can be adjusted by R1and R2, the reference formula is:

VCC = 1.2 x (R1+R2) / R2

The value of (R1+R2) should be between 500k to 1M Ohm.

SSD1303

Rev 1.7 P 19/56 May 2005

Solomon Systech

Table 3 - Passive component selection:

D1

Q1

R1, R2

R3

C2

Schottky diode

MOSFET

Resistor

Resistor, 1.2

Ω

Capacitor, 6.8µF

Remark

1A, 25V e.g. 1N5822, BAT54 [Philips

Semiconductors]

N-FET with low R

DS

(on) and low Vth voltage. e.g. MGSF1N02LT1 [ON SEMI]

1%,1/10W

1%, 1/2W

Low ESR, 25V

C5

C6

Capacitor, 1 ~ 10 µF

Capacitor, 0.1 ~ 1µF

16V

16V

Solomon Systech

May 2005 P 20/56 Rev 1.7

SSD1303