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1 TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor
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TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
3.3.8 Reset Status Register (RESET_STAT)
The reset status register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.
•
In case of local reset:
The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives a local reset without receiving a global reset.
•
In case of global reset:
The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.
The Reset Status Register is shown in Figure 3-7 and described in Table 3-9 .
Figure 3-7 Reset Status Register (RESET_STAT)
31
GR
30
R, +1
Legend: R = Read only; -n = value after reset
Reserved
R, + 000 0000 0000 0000 0000 0000
1 0
LR0
R,+0
Table 3-9
Bit
31
30-1
0
Field
GR
Reserved
LR0
Reset Status Register (RESET_STAT) Field Descriptions
Description
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
Reserved.
CorePac0 reset status
0 = CorePac0 has not received a local reset.
1 = CorePac0 received a local reset.
End of Table 3-9
3.3.9 Reset Status Clear Register (RESET_STAT_CLR)
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in
and described in
.
Figure 3-8 Reset Status Clear Register (RESET_STAT_CLR)
31
GR
30
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Reserved
R, + 000 0000 0000 0000 0000 0000
1 0
LR0
RW,+0
Table 3-10
Bit
31
Field
GR
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 1 of 2)
Description
Global reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
82 Device Configuration Copyright 2014 Texas Instruments Incorporated
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Table of contents
- 1 TMS320C6671 Features and Description
- 1 Features
- 2 Applications
- 2 KeyStone Architecture
- 2 Device Description
- 4 Functional Block Diagram
- 5 Release History
- 13 Device Overview
- 13 Device Characteristics
- 14 DSP Core Description
- 17 Memory Map Summary
- 23 Boot Sequence
- 24 Boot Modes Supported and PLL Settings
- 25 Boot Device Field
- 26 Device Configuration Field
- 31 Boot Parameter Table
- 38 PLL Boot Configuration Settings
- 38 Second-Level Bootloaders
- 39 Terminals
- 39 Package Terminals
- 39 Pin Map
- 44 Terminal Functions
- 70 Development and Support
- 70 Development Support
- 70 Device Support
- 72 Related Documentation from Texas Instruments
- 73 Device Configuration
- 73 Device Configuration at Device Reset
- 74 Peripheral Selection After Device Reset
- 74 Device State Control Registers
- 78 Device Status Register
- 79 Device Configuration Register (DEVCFG)
- 79 JTAG ID Register (JTAGID) Description
- 80 Kicker Mechanism Register (KICK0 and KICK1)
- 80 (DSP_BOOT_ADDRn)
- 80 (LRSTNMIPINSTAT)
- 81 (LRSTNMIPINSTAT_CLR)
- 82 Reset Status Register (RESET_STAT)
- 82 (RESET_STAT_CLR)
- 83 Boot Complete Register (BOOTCOMPLETE)
- 83 (PWRSTATECTL)
- 84 (NMIGRx)
- 84 IPC Generation Registers (IPCGRx)
- 86 IPC Acknowledgement Registers (IPCARx)
- 86 IPC Generation Host Register (IPCGRH)
- 87 (IPCARH)
- 88 Timer Input Selection Register (TINPSEL)
- 90 (TOUTPSEL)
- 90 Reset Mux Register (RSTMUXx)
- 91 (DSP_SUSP_CTL)
- 93 Device Speed Register (DEVSPEED)
- 93 (CHIP_MISC_CTL)
- 94 Pullup/Pulldown Resistors
- 95 System Interconnect
- 95 Internal Buses and Switch Fabrics
- 96 Switch Fabric Connections
- 104 Bus Priorities
- 105 C66x CorePac
- 106 Memory Architecture
- 106 L1P Memory
- 107 L1D Memory
- 108 L2 Memory
- 109 MSM SRAM
- 109 L3 Memory
- 110 Memory Protection
- 111 Bandwidth Management
- 111 Power-Down Control
- 112 C66x CorePac Revision
- 112 C66x CorePac Register Descriptions
- 113 Device Operating Conditions
- 113 Absolute Maximum Ratings
- 114 Recommended Operating Conditions
- 115 Electrical Characteristics
- 116 Power Supply to Peripheral I/O Mapping
- 117 Electrical Specifications
- 117 Parameter Information
- 117 Analysis
- 117 1.8-V LVCMOS Signal Transition Levels
- 117 Transition Behavior
- 118 Power Supplies
- 119 Power-Supply Sequencing
- 124 Power-Down Sequence
- 124 Bulk Capacitors
- 125 SmartReflex
- 126 Power Sleep Controller (PSC)
- 126 Power Domains
- 127 Clock Domains
- 128 PSC Register Memory Map
- 130 Reset Controller
- 131 Power-on Reset
- 132 Hard Reset
- 133 Soft Reset
- 134 Local Reset
- 134 Reset Priority
- 134 Reset Controller Register
- 135 Reset Electrical Data / Timing
- 137 Main PLL and PLL Controller
- 138 Information
- 140 PLL Controller Memory Map
- 147 Main PLL Control Register
- 148 Sequence
- 148 Clock Input Electrical Data/Timing
- 150 DD3 PLL
- 150 DDR3 PLL Control Register
- 151 DDR3 PLL Device-Specific Information
- 151 DDR3 PLL Initialization Sequence
- 153 PASS PLL
- 153 PASS PLL Control Register
- 154 PASS PLL Device-Specific Information
- 154 PASS PLL Initialization Sequence
- 155 PASS PLL Input Clock Electrical Data/Timing
- 156 Controller
- 157 EDMA3 Device-Specific Information
- 157 EDMA3 Channel Controller Configuration
- 157 EDMA3 Transfer Controller Configuration
- 158 EDMA3 Channel Synchronization Events
- 162 Interrupts
- 162 Interrupt Sources and Interrupt Controller
- 175 CIC Registers
- 181 Inter-Processor Register Map
- 182 NMI and LRESET
- 183 External Interrupts Electrical Data/Timing
- 183 Host Interrupt Output
- 184 Memory Protection Unit (MPU)
- 187 MPU Registers
- 192 MPU Programmable Range Registers
- 197 DDR3 Memory Controller
- 197 Information
- 197 Consideration
- 198 Data/Timing
- 199 C Peripheral
- 199 C Device-Specific Information
- 200 C Peripheral Register Description(s)
- 201 C Electrical Data/Timing
- 204 SPI Peripheral
- 204 SPI Electrical Data/Timing
- 207 HyperLink Peripheral
- 207 HyperLink Device-Specific Interrupt Event
- 209 HyperLink Electrical Data/Timing
- 211 UART Peripheral
- 212 PCIe Peripheral
- 213 TSIP Peripheral
- 213 TSIP Electrical Data/Timing
- 215 EMIF16 Peripheral
- 215 EMIF16 Electrical Data/Timing
- 217 Packet Accelerator
- 217 Security Accelerator
- 218 Gigabit Ethernet (GbE) Switch Subsystem
- 220 Management Data Input/Output (MDIO)
- 221 Timers
- 221 Timers Device-Specific Information
- 222 Timers Electrical Data/Timing
- 222 Serial RapidIO (SRIO) Port
- 223 General-Purpose Input/Output (GPIO)
- 223 GPIO Device-Specific Information
- 223 GPIO Electrical Data/Timing
- 224 Semaphore
- 224 Emulation Features and Capability
- 224 Advanced Event Triggering (AET)
- 225 Trace
- 226 IEEE 1149.1 JTAG
- 228 Revision History
- 233 Mechanical Data
- 233 Thermal Data
- 233 Packaging Information