1 TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor

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1  TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor | Manualzz

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

3.3.8 Reset Status Register (RESET_STAT)

The reset status register (RESET_STAT) captures the status of local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

In case of local reset:

The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives a local reset without receiving a global reset.

In case of global reset:

The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

The Reset Status Register is shown in Figure 3-7 and described in Table 3-9 .

Figure 3-7 Reset Status Register (RESET_STAT)

31

GR

30

R, +1

Legend: R = Read only; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

1 0

LR0

R,+0

Table 3-9

Bit

31

30-1

0

Field

GR

Reserved

LR0

Reset Status Register (RESET_STAT) Field Descriptions

Description

Global reset status

0 = Device has not received a global reset.

1 = Device received a global reset.

Reserved.

CorePac0 reset status

0 = CorePac0 has not received a local reset.

1 = CorePac0 received a local reset.

End of Table 3-9

3.3.9 Reset Status Clear Register (RESET_STAT_CLR)

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The

Reset Status Clear Register is shown in

Figure 3-8

and described in

Table 3-10

.

Figure 3-8 Reset Status Clear Register (RESET_STAT_CLR)

31

GR

30

RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

1 0

LR0

RW,+0

Table 3-10

Bit

31

Field

GR

Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions (Part 1 of 2)

Description

Global reset clear bit

0 = Writing a 0 has no effect.

1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

82 Device Configuration Copyright 2014 Texas Instruments Incorporated

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