1 TMS320C6671 Features and Description TMS320C6671 Fixed and Floating-Point Digital Signal Processor

TMS320C6671

Fixed and Floating-Point Digital Signal Processor

SPRS756E—March 2014

7.7 DD3 PLL

The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

DDR3 PLL power is supplied externally via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone I Devices in

‘‘Related

Documentation from Texas Instruments’’ on page 72. For the best performance, TI recommends that all the PLL

external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI filter).

Figure 7-23

shows the DDR3 PLL.

Figure 7-23 DDR3 PLL Block Diagram

PLLD

DDR3 PLL xPLLM

DDRCLK(N|P)

0

PLLOUT

DDR3

PHY

1

BYPASS

7.7.1 DDR3 PLL Control Register

The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs

(memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through

an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.4

‘‘PLL Boot

Configuration Settings’’

on page 38. See section 3.3.4

‘‘Kicker Mechanism Register (KICK0 and KICK1)’’ on page 80 for the address location of the registers and locking and unlocking sequences for accessing the registers. This

register is reset on POR only.

.

Figure 7-24 DDR3 PLL Control Register 0 (DDR3PLLCTL0)

(1)

31

BWADJ[7:0]

RW-0000 1001

24 23

BYPASS

RW-0

22 19

Reserved

RW-0001

18

PLLM

RW-0000000010011

6 5

PLLD

0

RW-000000

Legend: RW = Read/Write; -n = value after reset

1 This register is reset on POR only. The regreset, reset, and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

Table 7-27

Bit Field

31-24 BWADJ[7:0]

23 BYPASS

DDR3 PLL Control Register 0 Field Descriptions (Part 1 of 2)

22-19 Reserved

Description

BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) - 1

Enable bypass mode

0 = Bypass disabled

1 = Bypass enabled

Reserved

150 Peripheral Information and Electrical Specifications Copyright 2014 Texas Instruments Incorporated

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